JPH021934U - - Google Patents

Info

Publication number
JPH021934U
JPH021934U JP7888288U JP7888288U JPH021934U JP H021934 U JPH021934 U JP H021934U JP 7888288 U JP7888288 U JP 7888288U JP 7888288 U JP7888288 U JP 7888288U JP H021934 U JPH021934 U JP H021934U
Authority
JP
Japan
Prior art keywords
address
binary data
data
utility
ary
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7888288U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7888288U priority Critical patent/JPH021934U/ja
Publication of JPH021934U publication Critical patent/JPH021934U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Stored Programmes (AREA)
  • Manipulation Of Pulses (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例の構成を示すブロツ
ク図、第2図は第1図に示したROMにおけるア
ドレス(被変換データ)と変換データの対照を示
す概念図、第3図は変換回路の一従来例を示す回
路ブロツク図である。 1……上位ROM、2……下位ROM、3……
上位ラツチ回路、4……下位ラツチ回路。
Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a conceptual diagram showing the contrast between the address (data to be converted) and conversion data in the ROM shown in Fig. 1, and Fig. 3 is a conversion diagram. 1 is a circuit block diagram showing a conventional example of a circuit. FIG. 1... Upper ROM, 2... Lower ROM, 3...
Upper latch circuit, 4...lower latch circuit.

Claims (1)

【実用新案登録請求の範囲】 2進データをアドレスとするアドレス手段と、 前記アドレスに該当する番地に、予め前記2進
データに相当するn進データを記憶する記憶手段
と を具えたことを特徴とする2進データ/n進デ
ータ変換回路。
[Claims for Utility Model Registration] The utility model is characterized by comprising: address means that uses binary data as an address; and storage means that stores n-ary data corresponding to the binary data in advance at an address corresponding to the address. A binary data/n-ary data conversion circuit.
JP7888288U 1988-06-16 1988-06-16 Pending JPH021934U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7888288U JPH021934U (en) 1988-06-16 1988-06-16

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7888288U JPH021934U (en) 1988-06-16 1988-06-16

Publications (1)

Publication Number Publication Date
JPH021934U true JPH021934U (en) 1990-01-09

Family

ID=31303775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7888288U Pending JPH021934U (en) 1988-06-16 1988-06-16

Country Status (1)

Country Link
JP (1) JPH021934U (en)

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