JPH021940Y2 - - Google Patents
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- Publication number
- JPH021940Y2 JPH021940Y2 JP19452483U JP19452483U JPH021940Y2 JP H021940 Y2 JPH021940 Y2 JP H021940Y2 JP 19452483 U JP19452483 U JP 19452483U JP 19452483 U JP19452483 U JP 19452483U JP H021940 Y2 JPH021940 Y2 JP H021940Y2
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- power supply
- output
- transistor
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000003990 capacitor Substances 0.000 claims description 14
- 238000010586 diagram Methods 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000005856 abnormality Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000007599 discharging Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
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- Control Of Electrical Variables (AREA)
- Amplifiers (AREA)
Description
【考案の詳細な説明】
考案の技術分野
本考案は交互に切換えられるマルチ電源用の集
積回路に関し、電源切換時に信号を出力させて該
信号によりポツプ音防止などを簡単に行なえるよ
うにしようとするものである。[Detailed Description of the Invention] Technical Field of the Invention The present invention relates to an integrated circuit for multiple power supplies that can be switched alternately, and attempts to output a signal when the power supply is switched so that the signal can be used to easily prevent popping noises, etc. It is something to do.
従来技術と問題点
AM/FMラジオのAMからFMへまたはこの逆
への切換え、及びトランシーバにおける送信/受
信切換えには電源も切換えられるが、この切換え
を機械的な接点を有するリレーでなく、トランジ
スタを用いた電子回路で行なうことが実施されて
いる。本考案者は集積回路化したこの種切換回路
を開発し、提案した(実開昭53−163639号公報)。Prior Art and Problems When switching from AM to FM in an AM/FM radio or vice versa, and when switching between transmitting and receiving in a transceiver, the power supply is also switched, but this switching is performed using transistors rather than relays with mechanical contacts. This is being done using electronic circuits using . The present inventor developed and proposed this type of switching circuit as an integrated circuit (Japanese Utility Model Publication No. 163639/1983).
ところで電源オンオフ時にはブスツという雑音
(ポツプ音)がスピーカから流れる傾向があり、
これを防止するには信号回路とグランドとの間に
接続したトランジスタを切解時にオンにして信号
をグランドへ落とす、増幅器の利得調整回路を作
動させて利得を落とす、等の手段がとられてい
る。このミユート用の信号は、本考案者が案出し
た上記切換回路から簡単に導出できることが分つ
た。 By the way, when the power is turned on and off, there is a tendency for a popping noise to come from the speakers.
To prevent this, measures can be taken such as turning on the transistor connected between the signal circuit and ground when disconnecting to drop the signal to ground, or activating the amplifier's gain adjustment circuit to reduce the gain. There is. It has been found that this mute signal can be easily derived from the switching circuit devised by the present inventor.
考案の目的
本考案はかゝる点に着目したものであつて、上
記切換用集積回路に二、三の回路素子を付加する
という簡単な手段で、電源切換時に発生して異常
音防止などに供せる信号を出力可能にしようとす
るものである。Purpose of the invention The present invention focuses on this point, and uses a simple method of adding a few circuit elements to the switching integrated circuit described above to prevent abnormal noises that occur when switching the power supply. The aim is to make it possible to output signals that can be provided.
考案の構成
本考案は、基準電圧及び負帰還電圧を受けて第
1の電源用電圧を発生する第1の増幅器と、基準
電圧及び負帰還電圧を受けて第2の電源用電圧を
発生する第2の増幅器と、これらの増幅器へ加え
られる基準電圧とグランドへ落とすトランジスタ
および当該電源を立上げる制御信号が入力しかつ
他の電源の電圧が所定値以下のとき該トランジス
タをオフにして前記基準電圧を増幅器へ入力させ
る論理ゲートを備えるマルチ電源用集積回路にお
いて、コンデンサを充電するトランジスタと、前
記基準電圧をグランドへ落とすトランジスタが共
にオンのとき該充電用トランジスタをオンにして
前記充電を行なわせる論理ゲートを備え、該コン
デンサの電圧を外部へ出力するようにしてなるこ
とを特徴とするが、次に実施例を参照しながらこ
れを詳細に説明する。Structure of the invention The present invention includes a first amplifier that receives a reference voltage and a negative feedback voltage and generates a first power supply voltage, and a first amplifier that receives a reference voltage and a negative feedback voltage and generates a second power supply voltage. 2 amplifiers, a reference voltage applied to these amplifiers, a transistor to be grounded, and a control signal for starting up the power supply, and when the voltage of the other power supply is below a predetermined value, the transistor is turned off and the reference voltage is lowered. In a multi-power integrated circuit that includes a logic gate that inputs the reference voltage to an amplifier, when a transistor that charges a capacitor and a transistor that drops the reference voltage to ground are both on, the charging transistor is turned on and the charging is performed. The capacitor is characterized by having a gate and outputting the voltage of the capacitor to the outside, which will be described in detail below with reference to embodiments.
考案の実施例
第1図はマルチ電源用集積回路の要部を示し、
鎖線より上部が既提案回路である。この回路及び
その変形例などの詳細は前記公報で説明されてい
るが、概要と説明すると、端子T1,T2が出力端
子で、これより出力される電圧V01,V02は前述
のAM/FMラジオのAM部およびFM部の電源あ
るいはトランシーバの送信部および受信部の電源
となる。勿論この出力V01,V02はかゝる電源の
スイツチ制御信号として大電力を処理できるよう
にしてもよい。こゝではV01,V02は第1、第2
の電源とする。A1,A3は電圧V01,V02を出力す
る増幅器で、基準電圧VRに比例した該電圧V01,
V02を生じる。この部分の制御つまり定電圧制御
の態様は周知の通りで、例えば基準電圧VRをそ
のまゝあるいは分圧して差動増幅器A1の正入力
端子に加え、出力電圧V02をそのまゝあるいは分
圧して該差動増幅器A1の負入力端子に加え、負
帰還制御により出力電圧V02を基準電圧VRに比例
した一定値に維持する。比例係数は上記分圧の比
により定まる。本回路ではこれを簡単に抵抗R1
で表わしている。出力電圧V01についても同様
で、抵抗R2はその比例係数を表わす。Embodiment of the invention Figure 1 shows the main parts of a multi-power supply integrated circuit,
The circuit above the chain line is the already proposed circuit. The details of this circuit and its modifications are explained in the above-mentioned publication, but to give an overview, the terminals T 1 and T 2 are output terminals, and the voltages V 01 and V 02 outputted from these are the above-mentioned AM /Powers the AM and FM sections of an FM radio or the transmitter and receiver of a transceiver. Of course, the outputs V 01 and V 02 may be used as switch control signals for such a power supply so as to be able to handle large amounts of power. Here, V 01 and V 02 are the first and second
It is used as a power source. A 1 and A 3 are amplifiers that output voltages V 01 and V 02 , and the voltages V 01 and V 02 are proportional to the reference voltage VR .
Produces V 02 . The control of this part, that is, the mode of constant voltage control, is well known. For example, the reference voltage V R is applied as is or after being divided and applied to the positive input terminal of the differential amplifier A 1 , and the output voltage V 02 is applied as is or as a divided voltage. The voltage is divided and applied to the negative input terminal of the differential amplifier A1 , and the output voltage V02 is maintained at a constant value proportional to the reference voltage VR by negative feedback control. The proportionality coefficient is determined by the ratio of the above partial pressures. In this circuit, this can be easily done by using the resistor R 1
It is expressed as The same applies to the output voltage V 01 , and the resistance R 2 represents its proportional coefficient.
端子T3は切換制御電圧Vcを入力する端子であ
る。制御電圧VcをH(ハイ)レベルにし、そして
増幅器A4の出力もHレベルであるとすると、ナ
ンドゲートG1の出力はL(ロー)レベルとなり、
トランジスタT3はオフ、従つて基準電圧VRが増
幅器A1に入力して前述の出力電圧V02を生じる。
このときインバータG4の出力はLレベル、従つ
てナンドゲートG2の出力はHレベルで、トラン
ジスタTR4はオン、このため増幅器A3の基準電
圧入力端子はトランジスタTR4によりグランドへ
落されて該増幅器A3の出力電圧V01は0ボルトで
ある。負入力端に入いるこの電圧V01が0なら増
幅器A4は正入力端子に受ける閾値電圧VTHにより
Hレベル出力を生じ、これはナンドゲートG1の
入力に加わる。即ち上記のA4出力H、G1出力L
の条件は維持される。即ちVc=Hにすれば本回
路は出力電圧V02を生じ、V01は0にする。 Terminal T3 is a terminal to which switching control voltage Vc is input. When the control voltage Vc is set to H (high) level and the output of amplifier A4 is also at H level, the output of NAND gate G1 is set to L (low) level,
Transistor T 3 is off, so the reference voltage V R is input to amplifier A 1 producing the aforementioned output voltage V 02 .
At this time, the output of the inverter G4 is at the L level, and therefore the output of the NAND gate G2 is at the H level, and the transistor TR4 is turned on.Therefore, the reference voltage input terminal of the amplifier A3 is grounded by the transistor TR4, and the output of the NAND gate G2 is at the H level. The output voltage V 01 of amplifier A 3 is 0 volts. If this voltage V 01 entering the negative input terminal is 0, the amplifier A 4 produces an H level output due to the threshold voltage V TH received at the positive input terminal, which is applied to the input of the NAND gate G 1 . That is, the above A 4 output H, G 1 output L
conditions will be maintained. That is, when Vc=H, this circuit produces an output voltage V 02 and V 01 is set to 0.
制御電圧VcをLにすると、ナンドゲートG1の
出力はH、トランジスタTR3はオン、増幅器A1
の出力V02は0となる。しかし電源回路は一般に
コンデンサを有し、給電が停止しても該コンデン
サが放電を終了するまで電圧は0にならない。電
圧V02が正常値であるとこれは閾値電圧VTHより
高いので(VTHをそのように定める)増幅器A2の
出力はLレベルであり、この点でもナンドゲート
G2の出力はHレベルであつたが、Vc=L、従つ
てG4の出力がHになるとG2はその出力をLレベ
ルにする条件の1つが満たされる。しかし電源電
圧V02が閾値電圧VTH以下に下らない限り増幅器
A2の出力はLレベルであるから、ナンドゲート
G2の出力はHを保ち、トランジスタTR4はオン
である。このため増幅器A3の基準電圧入力端は
グランドに落されたまゝであり、出力V01は0を
保つ。 When the control voltage Vc is set to L, the output of NAND gate G1 is H, transistor TR3 is on, and amplifier A1
The output V 02 becomes 0. However, a power supply circuit generally includes a capacitor, and even if power supply is stopped, the voltage does not become zero until the capacitor finishes discharging. If the voltage V 02 is a normal value, it is higher than the threshold voltage V TH (V TH is defined as such), so the output of the amplifier A 2 is at L level, and at this point also the NAND gate
The output of G2 was at H level, but Vc=L, so when the output of G4 becomes H, one of the conditions for G2 to set its output to L level is satisfied. However, unless the supply voltage V 02 falls below the threshold voltage V TH, the amplifier
Since the output of A2 is L level, the NAND gate
The output of G2 remains high and transistor TR4 is on. Therefore, the reference voltage input terminal of the amplifier A3 remains grounded, and the output V01 remains at zero.
コンデンサの放電が進んでV02がVTH以下にな
ると増幅器A2の出力はHとなり、G4の出力もH
であるからナンドゲートG2の出力はLレベルと
なり、トランジスタTR4をオフする。この結果増
幅器A3には基準電圧VRが入力し、該増幅器A3は
前述の電圧V01を出力する。こうして電源はV02
からV01へ切換わる。電源を更にV01からV02へ切
換えには制御電圧VcをHレベルに戻せばよく、
この場合も電圧V01が閾値電圧VTHより低くなつ
て始めて切換えが行なわれる。 When the discharge of the capacitor progresses and V 02 becomes less than V TH , the output of amplifier A 2 becomes H, and the output of G 4 also becomes H.
Therefore, the output of NAND gate G2 becomes L level, turning off transistor TR4 . As a result, the reference voltage V R is input to the amplifier A 3 , and the amplifier A 3 outputs the aforementioned voltage V 01 . Thus the power supply is V 02
to V 01 . To further switch the power supply from V 01 to V 02 , all you have to do is return the control voltage Vc to the H level.
In this case as well, switching takes place only when the voltage V 01 becomes lower than the threshold voltage V TH .
第2図はこれを図示説明するもので、時点t1で
制御電圧Vcが立上る(Hになる)と増幅器A3の
出力は0にない、電圧V01はコンデンサの放電に
つれて下降する。時点t2でV01VTHになると増
幅器A4の出力はHレベルになり、ナンドゲート
G1の出力がL、トランジスタTR3がオフとなつ
て増幅器A1は電圧V02を出力する。 FIG. 2 illustrates and explains this. When the control voltage Vc rises (becomes H) at time t1, the output of the amplifier A3 is not at 0, and the voltage V01 falls as the capacitor discharges. When V 01 V TH is reached at time t2, the output of amplifier A4 becomes H level, and the NAND gate
The output of G1 is L, the transistor TR3 is turned off, and the amplifier A1 outputs a voltage V02 .
電源が直ちには切換えられず、稼動中の電源の
電圧が充分下つてから次の電源が入るようにする
上記制御は、既提案回路の主題であつて、これに
より両系が同時に動作する、例えばトランシーバ
であれば自己の送信信号の末端が受信されて雑音
を生じるという問題がなくなる。リレー接点での
切換えでなく、電子的な切換えを行なうと、切換
動作が速やかなので上記問題が生じやすく、本回
路はこれを防ぐのに有効である。 The above-mentioned control, in which the power supply is not switched immediately and the next power supply is turned on only after the voltage of the currently operating power supply has dropped sufficiently, is the subject of previously proposed circuits, and this allows both systems to operate simultaneously, e.g. A transceiver eliminates the problem of noise being generated by receiving the end of its own transmitted signal. If electronic switching is performed instead of switching using relay contacts, the above-mentioned problem is likely to occur because the switching operation is quick, and this circuit is effective in preventing this problem.
ところで上述の説明にあつたようにV02から
V01へ切換わるとき、トランジスタTR3とTR4が
共にオンである期間がある。この期間は第2図で
言えば時点t1から時点t2までである。電源をV01
からV02へ切換える場合も同様である。電源を切
換える、換言すれば電源を接、断するときは、周
知のようにポツプ音が発生し、これを防止すべく
ミユーテイング回路が開発されている。ポツプ音
の抑制には、電源接断時に信号回路をグランドへ
落とすあるいは増幅器の利得を低下させるのが有
効であり、完全な抑制をするにはかゝる制御を行
なう回路を電源接、断の前、後に亘る所定期間中
作動させればよい。かゝる制御回路は単純にはト
ランジスタ1個で構成でき、簡単であるが、該ト
ランジスタの制御信号の作成が、特別の付加手段
を要したりして厄介である。しかし本回路では上
述のように期間t1〜t2でトランジスタTR3,TR4
を共にオンという現象がある。本考案はこれを利
用して簡単に上記制御信号を発生しようとするも
のである。 By the way, as explained above, from V 02
When switching to V 01 , there is a period in which transistors TR 3 and TR 4 are both on. In FIG. 2, this period is from time t1 to time t2. Power supply V 01
The same applies when switching from V 02 to V 02 . As is well known, when switching the power source, in other words, when connecting or disconnecting the power source, a popping sound is generated, and muting circuits have been developed to prevent this. To suppress pop noise, it is effective to ground the signal circuit or lower the gain of the amplifier when the power is disconnected.To completely suppress the pop noise, disconnect the circuit that performs such control when the power is connected or disconnected. What is necessary is to operate it during a predetermined period spanning before and after. Although such a control circuit is simple and can be constructed simply from one transistor, it is troublesome to create a control signal for the transistor because it requires special additional means. However, in this circuit, as mentioned above, the transistors TR 3 and TR 4 are switched off during the period t1 to t2.
There is a phenomenon where both are turned on. The present invention attempts to utilize this to easily generate the control signal.
第1図の鎖線より下が本考案の実施例回路を示
す。G3はノアゲートで、その2個の入力端はト
ランジスタTR3,TR4のコレクタに接続され、出
力端はトランジスタTR5のベースに接続される。
トランジスタTR5のコレクタはこの集積回路の電
源Vccへ接続され、エミツタは出力端T4に接続
される。出力端T4とグランドとの間には負荷抵
抗RとコンデンサCが接続される。これらのR,
Cまで集積回路内に収めてもよいが、これらは外
付けとしてもよい。 The circuit below the chain line in FIG. 1 shows an embodiment of the present invention. G3 is a NOR gate, and its two input terminals are connected to the collectors of transistors TR3 and TR4 , and its output terminal is connected to the base of transistor TR5 .
The collector of the transistor TR 5 is connected to the power supply Vcc of this integrated circuit, and the emitter is connected to the output terminal T 4 . A load resistor R and a capacitor C are connected between the output terminal T4 and the ground. These R,
Although up to C may be included in the integrated circuit, these may also be externally attached.
この回路の動作は上述の説明から明らかであろ
うが、トランジスタTR3,TR4が共にオン、従つ
てそれらのコレクタがLレベルのときノアゲート
G3の出力はHレベルとなり、トランジスタTR5
がオンにする。従つてコンデンサCは充電され
る。トランジスタTR3,TR4が共にオンである期
間(t2−t1)は1μS程度の短い時間であり、この
期間が経過するとノアゲートG3の出力はLレベ
ルに戻り、トランジスタTR5はオフになる。しか
しコンデンサCが充電されたのでこれが放電する
までは出力電圧V03は0にならない。即ち電圧
V03は第2図に示すようにRC放電曲線を画いて
漸減し、ミユート回路などは閾値Vthまで有効と
するとこの期間(t3−t1)の間該回路を作動させ
ることができる。このコンデンサCにより出力
V03のパルス幅は適宜拡大できる。出力V03の発
生タイミングは制御電圧VcのH,L切換えタイ
ミングにはほゞ等しい。 The operation of this circuit will be clear from the above explanation, but when both transistors TR 3 and TR 4 are on, and their collectors are at L level, the NOR gate is activated.
The output of G3 becomes H level, and the transistor TR5
turns on. Capacitor C is therefore charged. The period (t2-t1) during which both transistors TR 3 and TR 4 are on is a short time of about 1 μS, and after this period, the output of NOR gate G 3 returns to L level and transistor TR 5 is turned off. However, since the capacitor C has been charged, the output voltage V 03 will not become 0 until it is discharged. i.e. voltage
V 03 gradually decreases with an RC discharge curve as shown in FIG. 2, and if the miute circuit or the like is enabled up to the threshold value Vth, the circuit can be operated during this period (t3-t1). This capacitor C outputs
The pulse width of V 03 can be expanded as appropriate. The generation timing of the output V 03 is approximately equal to the H/L switching timing of the control voltage Vc.
考案の効果
以上説明したように本考案によれば、マルチ電
源切換回路の一部を利用して簡単に電源切換時に
発生する異常を阻止する信号を発生でき、甚だ有
効である。Effects of the Invention As explained above, according to the present invention, it is possible to easily generate a signal to prevent an abnormality that occurs when switching power sources by using a part of the multi-power switching circuit, and it is extremely effective.
第1図は本考案の実施例を示す回路図、第2図
は動作説明用の波形図である。
図面でVRは基準電圧、V01,V02は第1、第2
の電源用電圧、A1,A2は該電源用電圧を発生す
る増幅器、TR3,TR4は基準電圧のグランドへ落
とすトランジスタ、Vcは制御電圧、G1,G2
は論理ゲート、Cはコンデンサ、TR5はその充電
用トランジスタ、G3はTR5制御用論理ゲートで
ある。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram for explaining the operation. In the drawing, V R is the reference voltage, V 01 and V 02 are the first and second
A 1 and A 2 are amplifiers that generate the power supply voltage, TR 3 and TR 4 are transistors that connect the reference voltage to the ground, Vc is a control voltage, and G1 and G2 are
is a logic gate, C is a capacitor, TR 5 is a charging transistor, and G 3 is a logic gate for controlling TR 5 .
Claims (1)
電圧を発生する第1の増幅器と、基準電圧及び負
帰還電圧を受けて第2の電源用電圧を発生する第
2の増幅器と、これらの増幅器へ加えられる基準
電圧をグランドへ落とすトランジスタおよび当該
電源を立上げる制御信号が入力しかつ他の電源の
電圧が所定値以下のとき該トランジスタをオフに
して前記基準電圧を増幅器へ入力させる論理ゲー
トを備えるマルチ電源用集積回路において、 コンデンサを充電するトランジスタと、前記基
準電圧をグランドへ落とすトランジスタが共にオ
ンのとき該充電用トランジスタをオンにして前記
充電を行なわせる論理ゲートを備え、該コンデン
サの電圧を外部へ出力するようにしてなることを
特徴とするマルチ電源用集積回路。[Claims for Utility Model Registration] A first amplifier that receives a reference voltage and a negative feedback voltage and generates a first power supply voltage; and a first amplifier that receives a reference voltage and a negative feedback voltage and generates a second power supply voltage. A second amplifier, a transistor that lowers the reference voltage applied to these amplifiers to the ground, and a control signal for turning on the power supply is input, and when the voltage of the other power supply is below a predetermined value, the transistor is turned off and the reference voltage is grounded. In a multi-power supply integrated circuit equipped with a logic gate that inputs a voltage to an amplifier, when a transistor that charges a capacitor and a transistor that drops the reference voltage to ground are both on, the charging transistor is turned on to perform the charging. A multi-power supply integrated circuit comprising a logic gate and outputting the voltage of the capacitor to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19452483U JPS60101810U (en) | 1983-12-16 | 1983-12-16 | integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19452483U JPS60101810U (en) | 1983-12-16 | 1983-12-16 | integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60101810U JPS60101810U (en) | 1985-07-11 |
| JPH021940Y2 true JPH021940Y2 (en) | 1990-01-18 |
Family
ID=30418088
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19452483U Granted JPS60101810U (en) | 1983-12-16 | 1983-12-16 | integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60101810U (en) |
-
1983
- 1983-12-16 JP JP19452483U patent/JPS60101810U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60101810U (en) | 1985-07-11 |
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