JPH02194730A - Digital/analogue converter - Google Patents

Abstract

PURPOSE:To realize a D/A converter having high resolution and a high converting rate by combining the D/A converters of a pulse width modulation PWM system and the D/A converter of a weight resistance system. CONSTITUTION:The subject converter is constituted with latches 1-5, flip flops 6, 7, 13 and 14, an input bus 8, a free run counter 9, comparators 10-12, switches 15 and 16, the D/A converting circuit 17 of the weight resistance system and a low pass filter 18. The upper (n-m)-bit signals of input digital signals with (n) bits are D/A converted in the D/A converting circuits 1-16 of the PWM system, lower (m)-bit signals are D/A converted in the D/A converting circuit 17 of the weight resistance system. The signals are added and addition signals are smoothed in the low pass filter 18, whereby they are set to be analogue output signals. Thus, the defect of the D/A converting circuits of the PWM system is complemented, and the D/A converter having high resolution and the high speed converting rate can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to an improvement of a digital-to-analog converter (hereinafter referred to as a D/A converter).

<Prior Art> Some direct drive motor control circuits output a speed command signal and a speed detection signal via a D/A converter in performing feedback control of the rotational speed of the motor.

Examples of this D/A converter include a weighted resistance type D/A converter and a ladder resistance type D/A converter.

However, commercially available D/A converters are expensive.

In order to solve this problem, the D/A converter is configured as a gate array, and a pulse width modulation type (hereinafter referred to as PWM) D/A converter is built in, and a low-pass filter is added to the D/A converter. By externally attaching D
/A converter can be configured.

Problems to be Solved by the Present Invention> However, in PWM type D/A converters, there has been a problem in that when the resolution is increased, the conversion rate is reduced.

The present invention has been made to solve these problems, and combines a PWM type D/A converter and a weighted resistance type D/A converter to provide a D/A converter with high resolution and high conversion rate.
The purpose is to realize a /A converter.

Means for Solving the Problem> The present invention pulse width modulates the upper (nm) bit signal (n, m are integers) of an n-bit input digital signal, and modulates the pulse width according to the upper bit signal. A digital-to-analog conversion circuit using a pulse width modulation method that generates a modulated signal, and a conversion circuit using a weighted resistor to convert the lower m bits of the input digital signal into digital to analog, and converting the converted signal into a digital-to-analog conversion circuit using the pulse width modulation method. A digital-to-analog conversion circuit comprising: a weighted resistance type digital-to-analog conversion circuit that adds to the pulse width modulation signal generated by the digital-to-analog conversion circuit; and a low-pass filter that smoothes this added signal and outputs it as an analog output signal. vessel.

<Operation> In the present invention, the upper (nm) bit signals of an n-bit input digital signal are D/A converted by a PWM type D/A conversion circuit, and the lower m bit signals are converted by a weighted resistance type D/A conversion circuit. A D/A conversion circuit performs D/A conversion, these converted signals are added, and the added signal is smoothed by a low-pass filter to produce an analog output signal.

<Example> The present invention will be explained below using the drawings.

FIG. 1 is a block diagram of an embodiment of a D/A converter according to the present invention.

In the figure, latches 1 to 5 and flip-flops 6.7 latch a 14-bit input digital signal. Since the input bus 8 has 8 bits, the 14-bit input digital signal is latched in a time-division manner, that is, the lower 8 bits of the input digital signal are first held in latches 1 and 2. The held data is further held in latch 3.4, and the upper 6 bits of the input digital signal are transferred to latch 5 and flip-flop 6.
．． Hold at 7. As a result, 14-bit data is held. Latches 1.2 and 3.4 constitute a double latch.

9 is a 12-bit free-run counter that counts up over time from the minimum count, and when the count reaches the maximum count, returns to the minimum count and counts up again.

10 to 12 are comparators, and the upper one of the input digital signals
The 2-bit data is compared with the count of the free run counter 9. The comparison result signal of comparator 10 is given to comparator 11, and the comparison result signal of comparator 11 is given to comparator 12.

Clip-flops 13 and 14 hold the comparison result signal of the comparator 12 and output it in synchronization with the clock.

15 and 16 are analog switches to which reference voltages +8V and -8V are applied to one end, and are opened and closed by the output of the flip-flop 14.

This analog switch is composed of, for example, a CMO3.

These components 1 to 16 constitute a PWM type D/A conversion circuit.

17 is a weighted resistance type D/A conversion circuit.

In this circuit, U is a summing amplifier, the voltage obtained by opening and closing the switches 15 and 16 is applied to the inverting input terminal, and the weight resistors R1 and R2 are connected to the non-inverting input terminal. The lower two bits of the input digital signal are applied to the resistors R1 and R2. The summing amplifier U adds the conversion signal from the PWM type D/A converter and the conversion signal from the weighted resistance type D/A converter.

18 is a low-pass filter (hereinafter referred to as L) using an OP amplifier.
PF), and at the same time constitutes a third-order Butterworth filter. This filter smoothes the output of the summing amplifier U. The smoothed signal becomes the analog output of the D/A converter.

Next, the operation of such an A/A converter will be explained.

First, the operation of the PWM type D/A conversion circuit will be explained.

FIG. 2 is a time chart of each signal of the conversion circuit of FIG. 1.

As shown in Figure (b), the free run counter 9 counts up from a minimum count of 0 and a maximum count of 409
When it reaches 5, it returns to the minimum count and counts up again.

The comparators 10 to 12 compare the count of the free run counter with the value of the upper 12 input digital signals held in the latches as shown by diagonal lines in the figure (b), and as a comparison result, (a) It is converted into a PWM signal as shown in the figure.

Here, the free run counter is a 12-bit counter with 2
Since the count is increased every time a 4 MHz clock is applied, the conversion rate fe of the PWM type D/A conversion circuit is given by the following equation.

fe = 24xlo'/2-2 = 5.86 [kHzl] The PWM signal generated in this way causes the switch 15.
16 is opened and closed, and reference voltages of 18V and 18V are applied. The applied voltage is given to the inverting input terminal of the summing amplifier U.

Next, the operation of the weighted resistance type D/A conversion circuit will be explained.

FIG. 3 is a block diagram of a weighted resistance type D/A conversion circuit.

In the figure, vP is the voltage signal obtained by opening and closing switches 15 and 16.

The lower 2 bits of the input digital signal, that is, the resistor R1
The voltages V, , V2 applied to and R2 are D of the PWM system.
Since the gate array of the /A conversion circuit has a CMO3'''C'' configuration, the amplitude is approximately equal to the power supply voltage of the conversion circuit.

Here, the voltage vP is a conversion signal of the upper 12 bits of the input digital signal and is obtained based on the reference voltage of ±8V, so the ILSB of the voltage vP is (8+8)/2" = It becomes 3.9 [mV].

When this ILSB is interpolated with 2 bits of a weighted resistance type D/converter, the ILSB is 1 [m out of 3.9/22
V].

Here, if the offset of the OP amplifier U is ignored, the following equation holds true.

(V' Vp)/Rd=(Vo V')/R5Vo
” (R5/Ra)V'+V'(R5/R4)V
P V': Voltage V applied to the non-inverting input terminal of OP amplifier U, ): Output voltage of OP amplifier U R,, R,: Resistance value of resistors R4 and R5 Here, when R, = R5 is set, . =2V'Vp.

To set 2V' in 1mV steps, R3<R,,
Assuming R, (KH2), V' may be operated in 0.5 mV steps, where R+, R2, and R3 are the resistance values of resistors R+, R2, and R3.

The relationship between each resistance value for operation in this step is as follows.

That is, assuming that V, , V2 are digital signals at a logic level of 5V, the following equation holds true.

R3/(R2+R3) Ki R3/R2 =2X0.5X10"215 Therefore, R2-=5000R:i R3/ (R+ + R3) KiRko /R+ =0.5X10'15 Therefore, R+=10000Rco An example of the resistance value is as follows.

R+ = IMΩ, R2 = 500Ω R3 = 100Ω, Ra = R5 = 100 kΩ In this way, with a 14-bit input digital signal, the upper 12
The bit signal is D/A converted by a PWM type D/A converter, the lower 2 bit signal is D/A converted by a weighted resistance type D/A converter, and these converted signals are added to produce an analog output signal. is obtained.

Note that the PWM type D/A conversion circuit may not be built into the gate array, but may be constructed using random logic.

In addition, a PWM type D/A conversion circuit and a weighted resistance type D/A conversion circuit are also available.
The number of bits of the input digital signal allocated to the /A conversion circuit may be at a ratio other than 12:2.

Further, the number of bits of the digital signal handled by the D/A converter may be other than the number shown in the embodiment.

Effect〉 According to the present invention, the following effects can be obtained.

Since it combines a PWM type D/A conversion circuit and a weighted resistance type D/A conversion circuit, the drawbacks of the PWM type D/A conversion circuit are compensated for, and D/A conversion with high resolution and a fast conversion rate is possible. It is possible to realize a vessel.

For example, when the lower χ bit of an input digital signal is processed by a weighted resistance type D/A converter, the conversion rate fH is:
The following relationship holds true for the conversion rate fc when all input digital signals are processed by a PWM D/A conversion circuit.

fH=fcX2χ Additionally, the characteristics required of the LPF inserted in the output section are relaxed, and as a result, the number of parts is reduced.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a D/A converter according to the present invention, and FIGS. 2 and 3 are diagrams illustrating the operation of the D/A converter of FIG. 1. 1 to 5...Latch, 6,7,13.14...Flip-flop, 8...Input bus, 9...Free run counter, 10 to 12...Comparator, 15.16.・・・
Switch, 17... weighted resistance type D/A conversion circuit,
18...LPF.

Claims (1)

[Claims] A pulse width that pulse width modulates the upper (nm) bit signal (n, m are integers) of an n-bit input digital signal to generate a pulse width modulated signal according to the upper bit signal. A digital-to-analog conversion circuit using a modulation method, and a conversion circuit using a weighted resistor to convert the lower m bits of the input digital signal into a digital-to-analog conversion circuit, and converting the converted signal into a digital-to-analog conversion circuit using a pulse width modulation method. A digital-to-analog converter comprising: a weighted resistance type digital-to-analog conversion circuit that adds to a generated pulse width modulation signal; and a low-pass filter to smooth the added signal and output it as an analog output signal.