JPH02196377A - Mounting design checking method and automatic mounting method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Industrial Application Field] The present invention relates to a mounting design checking method and an automatic mounting method in an automatic mounting design system for printed circuit boards, etc. The present invention relates to a mounting design checking method suitable for use in checking . . . and an automatic mounting method using such a checking method.

[Prior art] As a conventional technology related to a method for checking a failed mounting design of automatic mounting method 1 for printed circuit boards, etc., for example, Japanese Patent Laid-Open No. 61
A technique described in Japanese Patent No. 196373 and the like is known. In this type of conventional technology, in mounting design, components are placed on a printed circuit board, etc., and then signal lines extending from inside the component to the outside of the component are actually assigned to component pins provided to connect one component to another. In this method, temporary wiring is performed beforehand, and this temporary wiring is checked using the circuit delay and the theoretical length (Manhattan length) from the wiring result. [Problems to be Solved by the Invention] The above-mentioned prior art The check was performed individually (single layer) for each component or for each motherboard on which the component is mounted, and no consideration was given to checking as an interlayer net. Therefore, although the above-mentioned conventional technology is effective as a check performed at the stage before implementation design, it is not effective as a check at each stage of implementation design.
In particular, there was a problem in that the expected effect could not be obtained when checking interlayer nets.

An object of the present invention is to solve the problems of the prior art described above, and to provide an implementation that makes it possible to discover basic defects more accurately and early at each stage of designing the interlayer net to the minimum necessary level. The object of the present invention is to provide a design checking method and an automatic implementation method.

[Means for Solving the Problems] According to the present invention, the above object is to ensure that the wiring state of the signal net in the component or the motherboard is different from the bin to be connected.
Determine the design stage of pin opening, whether or not the line is in the above-mentioned line state with pin number assignment, whether it is in the wiring state after pin assignment and before wiring, and whether it is in the wiring state after wiring, Also,
At this time, the wiring information of the most subsequent process in these wiring states is extracted, and the wiring lengths of the inter-layer nets 1 to 1 are calculated by summing the wiring lengths between the pins of each layer for the upper signal net, and these results are calculated. This is achieved by checking using .

[Operation] Generally, when designing the implementation of a large-scale logic circuit used in a large-scale computer, etc., LS1. The mounting design is carried out from the lower hierarchy to the upper hierarchy, such as the printed circuit board on which the LSI is mounted, and the motherboard on which the printer 1 to board are mounted. However, within a limited development period, starting the implementation design of the upper layer after completing all the implementation design of the lower layer requires a long development period.

The present invention enables the implementation design of the upper layer to be started from the pre-dissection stage when carrying out the implementation design from the lower layer to the upper layer. [Recommendation] Since it is possible to perform a check, defects can be detected more accurately and the check results can be quickly fed back to the implementation equipment in the upper or lower hierarchy.

[Embodiment] Hereinafter, an embodiment of the mounting design checking method and automatic mounting method according to the present invention will be described in detail with reference to the drawings.

Fig. 1 is a flowchart explaining the processing procedure of the automatic mounting design system to which the present invention is applied, Fig. 2 is a flowchart explaining the method of calculating the wiring length for each wiring state, and Fig. 3 is a flowchart explaining the method of calculating the wiring length for each wiring state. , is a diagram showing an example of inter-layer network connection. In FIG. 3, ] is a motherboard, 2 is a printed circuit board, 3 is a logic element, and 4 is a logic circuit gate 1-.

In the processing flow shown in FIG. 1, the present invention is characterized by having steps 13, 16, and 18 surrounded by double lines. A check is performed when the combination of printed circuit board mounting design stages is different. This processing flow will be explained below.

(1) After completing the logic design of the logic circuit, the logic circuit is functionally divided and distributed to the printer 1 to the boards a to Q (step 10).

(2) The printed circuit boards a""-c to which the divided logic circuits are distributed are arranged on the motherboard "2" using a conventional arrangement method (step 11).

(3) Using the conventional automatic wiring method, each printed circuit board a
Logic elements are placed within -c. At this time, it is assumed that in each printed circuit board, actual pins of logic elements have not yet been assigned to some signal lines, and there are signals from temporary pins (step]-2).

(4) For each signal net, connect the pre-wiring net of motherboard 1- in the upper layer between layers, calculate the wiring length of the inter-layer net, and check each printed circuit board a to c (
Step 13).

(5) If the result of the check in step 13 is NG, execute steps 11 and 12 again to rearrange the logic elements on the printed circuit boards a-c.

(6) If the check result in step 13 is OK, assign the logic element pins of the printed circuit board s and c;
Execute the wiring of printed circuit board C, and use the same method as step 13 to connect the motherboard's pre-wiring net I, the pin assignment of printed circuit board a to the front net, the pin assignment of printed circuit board A to the rear net, and the pre-wiring net. After wiring the printed circuit board C, connect each layer between layers, calculate the wiring length of the interlayer net, and check it (Step) -4~''-
6).

(7) If the check result in step 16 is NG, execute steps 14 and 15 again to reallocate the logic element pins of printed circuit boards I and C, and
Execute rewiring of board C.

(8) If the result of the check in step 16 is ○, execute the allocation of logic element pins on the printer 1 and board a and the wiring between the printer 1 and the board a, and use the conventional automatic wiring method. to wire the motherboard (step 14)
', 15', 17).

(9) Next, the interlayer network connection is performed and checked using the same method as in step 13.16.

If the result of this check is NG, step 14
', 15', and 17 are re-executed.

The automatic mounting design system using the present invention performs the mounting design of the printer 1 to the board and the mounting setting H1 of the motherboard 1 by continuing the processing as described above. In the process flow described above, there are three printed circuit boards a to c, but in the present invention, there may be any number of printed circuit boards in the print 1,
Furthermore, the checks in steps 13, 16, 18, etc. may be performed in any state in which each printed circuit board is mounted.

Next, details of the wiring length calculation process in the check process in steps 13, 16, and 1.8 described above will be explained according to the flow shown in FIG.

Before starting the wiring length calculation process shown in FIG. Search the design file, then search the file for the same pin number as net 1- of the motherboard, and extract the signal net connected to that pin number. Then, the motherboard 1 of the upper layer and the net 1 of the motherboard 1 of the lower layer and the net 1 of the circuit board of the lower layer
2 to create an inter-layer connection net, and calculate the wiring length of this inter-layer connection net according to the flow shown in FIG. The processing flow shown in FIG. 2 shows a method for calculating wiring lengths for each wiring state.

(1) Determine whether wiring has been completed between pins or not based on the presence or absence of post-wiring data, and if wiring has been completed between pins, calculate the actual wiring length after wiring (steps 20 and 24).
．． ).

(2) In step 20, if there is no wiring between pins,
The pin to be connected is assigned to the front or not, and the pin number is assigned to the front by whether or not there is a symbol. If both pins are assigned to the rear (real pins), the pin assignment is After that, the wiring length (Manhattan length) before wiring is calculated (step 21.23).

(3) In step 21, if it is determined that the pin to be connected has a previous pin, the pin assignment assumes the previous pin position (pin coordinates) to be the center position of the logic element ( Step 22).

(4) Calculate the Manhattan length between pins and hypothetical pins or between hypothetical pins (step 25).

Through the above-described processing, it is possible to calculate the wiring length of the previous pin or a certain interlayer net for pin assignment.

In one embodiment of the present invention, an interlayer network I.
Identify the wiring status between pins to net 1 in the upper and lower layers, calculate the wiring length as described above, and use the total wiring length to calculate signal propagation delay time, load interval, total wiring length, etc. [Mounting film H] check.

In FIG. 3, which shows an example in which printed circuit boards 2 (2□, 2□) are mounted on the motherboard 1 and connected to a network between layers, logic elements 3□ are mounted on the printed circuit boards 1 to 2□, and the printed circuit boards 2 Logic elements 32 and 33 are mounted on □. It is assumed that the pins P□ to P3 arranged on the printed circuit board 2□ are already allocated pins, and the wiring between these pins has already been routed. Also, pin P4. Assume that P5 has been allocated and the wiring between them is unwired, pin P6 is allocated at the front, and the wiring between pins P5 and P6 is unwired. Furthermore, it is assumed that the wiring between the wiring connection points E and E2 on the motherboard 1 is also unwired.

In the case of the example shown in FIG. 3, one embodiment of the present invention calculates the wiring length of the interlayer net by the wiring length after wiring of pins P1 to P3 and the connection point E1. The wiring length before wiring is calculated from the Manhattan length between E2 and pin P4゜25, and the temporary allocation to the center position of the logic circuit gate 4 is calculated from the previous Manhattan length between pin P6 and pin 25. The pin assignments and previous wiring lengths are totaled, and the mounting design is checked based on the results.

As described above, according to an embodiment of the present invention, it is possible to perform a mounting check at any time during many stages of mounting design, and it is possible to detect and deal with mounting defects at an early stage. be.

[Effects of the Invention] As explained above, according to the present invention, in the automatic mounting design of logic circuits, it is possible to perform the mounting installation check of the printed circuit board and the motherboard at the stage H1 of each mounting film of the printed circuit board and the motherboard. Moreover, since it is possible to check the latest wiring status, defects can be discovered early at each mounting design stage, reducing the amount of design changes due to defects and shortening product development time. It is possible to reduce development costs and improve reliability.

[Brief explanation of the drawing]

Figure 1 is a flowchart 1 explaining the processing procedure of an automatic mounting design system to which the present invention is applied, Figure 2 is a flowchart explaining a method for calculating wiring lengths for each wiring state, and Figure 3 is a flowchart explaining how to calculate the wiring length for each wiring state. Implement and interlayer screw 1
It is a diagram showing an example of connection. 1...mother boat, 2 pudding 1~board, 3...
...Logic element, 4...Logic circuit gate.

Claims (2)

[Claims] 1. In the implementation design check method for interlayer nets, the wiring of interlayer nets is divided into routed parts and unrouted parts, the actual wiring length of the routed parts and the predicted wiring length of the unrouted parts are calculated, and these actual wiring lengths are calculated. An implementation design checking method characterized by performing a check based on a wiring length of an interlayer net obtained by adding a wiring length and a predicted wiring length. 2. An automatic mounting method for a circuit configured in a hierarchical structure, characterized in that the mounting design check according to claim 1 is performed at any of a plurality of mounting design stages.