JPH02201901A - Manufacture of laminated ceramic varister - Google Patents
Manufacture of laminated ceramic varisterInfo
- Publication number
- JPH02201901A JPH02201901A JP1019783A JP1978389A JPH02201901A JP H02201901 A JPH02201901 A JP H02201901A JP 1019783 A JP1019783 A JP 1019783A JP 1978389 A JP1978389 A JP 1978389A JP H02201901 A JPH02201901 A JP H02201901A
- Authority
- JP
- Japan
- Prior art keywords
- varistor
- ceramic
- powder
- fine powder
- manufacture
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- Thermistors And Varistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、積層方法を改良した積層セラミックバリスタ
の製造法に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a multilayer ceramic varistor using an improved lamination method.
〔従来技術及びその問題点]
酸化亜鉛を主成分とするセラミソクバリスクは、その抵
抗値が印加電圧によって著しく変化し、良好な電流−電
圧非直線性を示す。このため、従来より、各種電子機器
のサージ吸収用、電圧の安定化素子として幅広く使用さ
れてきた。[Prior Art and its Problems] Ceramisovarisk, whose main component is zinc oxide, has a resistance value that changes significantly depending on the applied voltage, and exhibits good current-voltage nonlinearity. For this reason, it has been widely used for surge absorption in various electronic devices and as a voltage stabilizing element.
最近では、機器の小型化、及び低電圧化が進み、これに
対応して小型で、低バリスタ電圧、高サージ耐量の特性
を有する積層セラミックバリスタが注目され、種々検討
されている。In recent years, devices have become smaller and lower in voltage, and in response to this trend, multilayer ceramic varistors that are compact, have low varistor voltage, and high surge resistance have attracted attention, and various studies have been conducted.
しかしながら従来の積層セラミックバリスタは、例えば
特開昭54−106894号公報に記載されているよう
に、焼結後に焼結体を切断し、更に研磨して得られる素
子は、もれ電流の増加やαの低下がみられることから、
その製造は以下のような方法により行われている。すな
わち、焼結することにより電圧非直線性を示す組成から
なる仮焼粉末をドクターブレード法によりシート化し、
この生シートに白金、パラジウムなどの高融点金属から
なる内部電極をスクリーン印刷し、ついでこれを積層し
、熱圧着、後、所定形状に切断する。これを空気中で焼
結し、この焼結体の両端に外部電極を焼き付けて積層セ
ラミックバリスタを得てい名。However, as described in JP-A No. 54-106894, for example, conventional multilayer ceramic varistors are manufactured by cutting the sintered body after sintering and polishing it. Since a decrease in α is observed,
Its manufacture is carried out by the following method. That is, a calcined powder having a composition that exhibits voltage nonlinearity when sintered is made into a sheet by a doctor blade method,
Internal electrodes made of a high-melting point metal such as platinum or palladium are screen-printed on this raw sheet, which is then laminated, thermocompressed, and then cut into a predetermined shape. This is sintered in air, and external electrodes are baked on both ends of this sintered body to obtain a multilayer ceramic varistor.
このように従来の積層セラミックバリスタは内部電極を
生シートの焼結と同時に形成するため、焼結時に生シー
トが収縮し内部電極との間にひずみを生じ、積層シート
間でデラミネーションが発生し、得られた素子は十分な
性能を果たすことができないことがあった。特に低バリ
スタ電圧を実現するためには、薄膜シートの成形が必須
となるが、このシート成形体の収縮が問題であった。ま
た内部電極材料としては、高い焼結温度で電極を焼付け
るため高価な金、白金、パラジウムといった高融点金属
を主成分とする必要があり積層セラミックバリスタの製
造コストを大幅に上げることになり、実用化の上で大き
な問題になっていた。In this way, in conventional laminated ceramic varistors, the internal electrodes are formed at the same time as the raw sheet is sintered, so the raw sheet contracts during sintering, creating strain between the raw sheet and the internal electrode, and delamination between the laminated sheets. However, the obtained device may not be able to achieve sufficient performance. In particular, in order to achieve a low varistor voltage, it is essential to form a thin film sheet, but shrinkage of this sheet form has been a problem. Furthermore, as the internal electrode material is baked at a high sintering temperature, it is necessary to use expensive high-melting point metals such as gold, platinum, and palladium as the main component, which significantly increases the manufacturing cost of multilayer ceramic varistors. This was a major problem in practical application.
本発明者らは以上の如き従来技術の問題点を解決するた
めに鋭意研究を行った結果、本発明に到った。The present inventors conducted extensive research to solve the problems of the prior art as described above, and as a result, they arrived at the present invention.
本発明は、積層セラミックバリスタの製造において、バ
リスタ特性を有するセラミック微粉末に、有機接着剤、
またはガラス粉末及び溶媒を加えてペースト状とし、こ
れを表裏両面に電極を形成した絶縁基板、ヒに塗布し、
これを積層後、熱処理を行うことにより基板同士を接着
することを特徴とする積層セラミックバリスタの製造法
に関する。In the production of a multilayer ceramic varistor, the present invention involves adding an organic adhesive to a fine ceramic powder having varistor properties.
Alternatively, add glass powder and a solvent to make a paste, and apply this to an insulating substrate with electrodes formed on both the front and back sides.
The present invention relates to a method for manufacturing a laminated ceramic varistor, characterized in that the substrates are bonded together by heat treatment after lamination.
本発明に使用するバリスタ特性を有するセラミック微粉
末は、例えば特開昭62−190801号公報に記載さ
れているような方法により製造されるものが好適に使用
される。すなわち酸化亜鉛の微粒子を700〜1300
°Cで焼成した後、焼結した酸化亜鉛を0.5〜50μ
mの粒子径に粉砕し、その酸化亜鉛微粉末に、酸化マン
ガン等の添加物を0゜0001〜10IIlo1χ添加
し、600〜1400’Cで焼成した後、粉砕分級して
得られる。その粒径は必要とするバリスタ電圧に応じて
適宜選択することができ、通常的1200°C度のもの
が好適に使用される。The fine ceramic powder having varistor properties used in the present invention is preferably produced by a method such as that described in JP-A-62-190801. That is, 700 to 1300 fine particles of zinc oxide
After baking at °C, sintered zinc oxide is added to 0.5-50μ
Zinc oxide fine powder is ground to a particle size of m, and additives such as manganese oxide are added to the zinc oxide fine powder in an amount of 0°0001 to 10IIlo1χ, calcined at 600 to 1400'C, and then crushed and classified. The particle size can be appropriately selected depending on the required varistor voltage, and a particle size of 1200° C. is preferably used.
有機接着剤としては、特に限定されないが、ポリイミド
樹脂、エポキシ樹脂、ゲイ素樹脂、フェノール樹脂等を
好適に挙げることができる。The organic adhesive is not particularly limited, but suitable examples include polyimide resins, epoxy resins, gay resins, phenol resins, and the like.
ガラス粉末としては、電極材料同士を接着させるような
ガラス組成であればよく、具体例とじては、酸化ビスマ
ス、酸化ケイ素、酸化ホウ素からなるような組成のガラ
スフリットを挙げることができる。The glass powder may have a glass composition that allows the electrode materials to adhere to each other, and specific examples include glass frit having a composition of bismuth oxide, silicon oxide, and boron oxide.
またバリスタ特性を有するセラミック微粉末と、有機接
着剤、またはガラス粉末及び溶媒の使用割合は、特に限
定されないがセラミック微粉末100重量部当たり10
〜100重量部使用される。Further, the proportion of the ceramic fine powder having varistor properties, the organic adhesive, or the glass powder and the solvent used is not particularly limited, but is 10 parts by weight per 100 parts by weight of the ceramic fine powder.
~100 parts by weight are used.
絶縁基板としては、ガラス基板、アルミナ基板、酸化ベ
リア基板等を好適に挙げることができる。Suitable examples of the insulating substrate include a glass substrate, an alumina substrate, an oxidized Beria substrate, and the like.
また基板上に形成する電極材料としては、金、白金、パ
ラジウム、銀、アルミニウム等の種々の金属を使用する
ことができるが、製造コストの面からは銀のような安価
な金属が好ましい。Further, various metals such as gold, platinum, palladium, silver, and aluminum can be used as the electrode material formed on the substrate, but an inexpensive metal such as silver is preferable from the viewpoint of manufacturing cost.
さらに詳細には、以下のような方法により製造すること
ができる。まず、バリスタ特性を有するセラミック微粉
末を調製し、これに有機接着剤、またはガラス粉末と溶
媒を加えペースト状とし、これを、表裏両面に電極を形
成した絶縁基板上にスクリーン印刷のような印刷法、ス
プレー法、浸漬法等により塗布し、ついで積層し、35
0〜600°C程度の温度で熱処理を行うことにより基
板同士を接着し積層体を得る。ついで積層体の端面に銀
ペースト等の外部電極材料を塗布し、500〜600°
C程度の温度で熱処理することにより容易に積層セラミ
ックバリスタを製造できる。More specifically, it can be manufactured by the following method. First, ceramic fine powder with varistor properties is prepared, an organic adhesive or glass powder and a solvent are added to it to form a paste, and this is printed by screen printing on an insulating substrate with electrodes formed on both the front and back sides. Coating by method, spray method, dipping method, etc., then laminating, 35
By performing heat treatment at a temperature of about 0 to 600°C, the substrates are bonded together to obtain a laminate. Next, an external electrode material such as silver paste is applied to the end face of the laminate, and an angle of 500 to 600°
A multilayer ceramic varistor can be easily manufactured by heat treatment at a temperature of approximately C.
以下、添付図面である第1図〜第3図に示す一実施例を
用いて本発明の積層セラミックバリスタの製造法を詳述
する。EMBODIMENT OF THE INVENTION Hereinafter, the manufacturing method of the laminated ceramic varistor of this invention will be explained in detail using one Example shown in FIGS. 1-3 which are attached drawings.
図において、1は絶縁基板、2は絶縁基板上の両端面に
形成した内部電極である。3はバリスタ特性を有するセ
ラミック微粉末に有機接着剤、またはガラス粉末と溶媒
を加え、ペースト状にした後に熱処理を行うことによっ
て得られるセラミックバリスタ層である。4は積層化し
た時、内部電極2の一端部と接続している外部電極であ
る。In the figure, 1 is an insulating substrate, and 2 is an internal electrode formed on both end surfaces of the insulating substrate. 3 is a ceramic varistor layer obtained by adding an organic adhesive or glass powder and a solvent to ceramic fine powder having varistor properties, making it into a paste, and then heat-treating the mixture. Reference numeral 4 denotes an external electrode that is connected to one end of the internal electrode 2 when stacked.
実施例1
粒子径0.05〜1μmの酸化亜鉛粉末をペレットに成
形後、1200°Cで2時間焼成を行った後、粉砕、分
級し、粒子径1〜20!Jmの粒子を得た。Example 1 After molding zinc oxide powder with a particle size of 0.05 to 1 μm into pellets, it was fired at 1200°C for 2 hours, and then crushed and classified. Particles of Jm were obtained.
この酸化亜鉛粉末に、酸化ビスマス、酸化マンガン、酸
化コバルト、酸化アンチモン、酸化アルミニウムをそれ
ぞれ、0.0001〜10molX添加、混合し、これ
を800〜1400°Cで焼成した後、軽く粉砕して、
2〜20μmの粒径となるように分級し、バリスタ特性
を有するセラミック微粉末を得た。0.0001 to 10 molX of each of bismuth oxide, manganese oxide, cobalt oxide, antimony oxide, and aluminum oxide are added and mixed to this zinc oxide powder, and after baking this at 800 to 1400°C, it is lightly pulverized.
The particles were classified to have a particle size of 2 to 20 μm to obtain a ceramic fine powder having varistor properties.
このセラミック微粉末100重量部に対してガラスフリ
ット50重量部、エチルセルロース5重量部、ブチルカ
ルピトール40重量部をそれぞれ加えて混合しペースト
状とした。To 100 parts by weight of this fine ceramic powder, 50 parts by weight of glass frit, 5 parts by weight of ethyl cellulose, and 40 parts by weight of butyl calpitol were added and mixed to form a paste.
一方、ガラス基板の表裏両面にスクリーン印刷により銀
ペーストを塗布後、500°Cで焼付けを行い、第1図
のような内部電極2を形成したガラス基板1上に上記の
ペースト状のバリスタ特性を有するセラミック微粉末を
スクリーン印刷により塗布し、これらを第3図のように
必要枚数、重ね合わせた。On the other hand, silver paste was applied to both the front and back sides of the glass substrate by screen printing, and then baked at 500°C to impart the above-mentioned paste-like varistor properties onto the glass substrate 1 on which the internal electrodes 2 as shown in Fig. 1 were formed. Ceramic fine powder was applied by screen printing, and the required number of sheets were stacked on top of each other as shown in FIG.
次に、この重ね合わせた積層体を350〜600°Cの
温度で熱処理した後、第3図に示すように積層体の端面
に銀ペーストを塗布し、外部電極4を形成した。そして
、これを大気中で、500°Cの温度で熱処理して積層
枚数が3枚の積層セラミックバリスタを得た。このセラ
ミック微粉末の1層の厚みは20μmであった。Next, the stacked laminate was heat-treated at a temperature of 350 to 600°C, and then, as shown in FIG. 3, a silver paste was applied to the end face of the laminate to form external electrodes 4. Then, this was heat-treated in the atmosphere at a temperature of 500°C to obtain a multilayer ceramic varistor having three layers. The thickness of one layer of this ceramic fine powder was 20 μm.
このようにして製造した積層セラミックバリスタのバリ
スタ電圧(1mAの電流が流れる電圧値、VlmA)は
、IOVであり、またこのときの非直線係数は20であ
った。The varistor voltage (voltage value at which a current of 1 mA flows, VlmA) of the multilayer ceramic varistor manufactured in this manner was IOV, and the nonlinear coefficient at this time was 20.
実施例2
バリスタ特性を有するセラミック微粉末100重量部に
対してポリイミド樹脂50重量部を加えたペーストを使
用した以外は実施例1と同様な方法により積層枚数が3
枚の積層セラミックバリスタを製造した。Example 2 The number of laminated sheets was 3 in the same manner as in Example 1 except that a paste was used in which 50 parts by weight of polyimide resin was added to 100 parts by weight of ceramic fine powder having varistor properties.
A multilayer ceramic varistor was manufactured.
この積層セラミックバリスタのバリスタ電圧は、10V
であり、またこのときの非直線係数は20であった。The varistor voltage of this multilayer ceramic varistor is 10V.
, and the nonlinear coefficient at this time was 20.
本発明によると、バリスタ特性を示すセラミック微粉末
を使用し、低い熱処理温度で積層セラミックバリスタを
製造するため、従来の製造法におけるような内部電極と
生シートとを同時に焼成することによるひずみが生じる
ことがなく、十分な性能を有する素子を得ることができ
、特に薄膜シートの場合のような低バリスタ電圧を有す
る積層セラ゛ミックバリスクを好適に製造することがで
きる。また内部電極材料として銀のような低融点材料が
使用可能であり、低コスト化に大いに貢献できる。According to the present invention, a ceramic fine powder exhibiting varistor properties is used to manufacture a laminated ceramic varistor at a low heat treatment temperature, so distortion occurs due to simultaneous firing of internal electrodes and raw sheets as in conventional manufacturing methods. Therefore, it is possible to obtain a device with sufficient performance, and in particular, it is possible to suitably manufacture a laminated ceramic varisque having a low varistor voltage as in the case of a thin film sheet. Furthermore, a low melting point material such as silver can be used as the internal electrode material, which can greatly contribute to cost reduction.
第1図は本発明に係る絶縁基板上に内部電極を塗布した
ものの平面図、第2図は上記絶縁基板の断面図、第3図
は上記絶縁基板とバリスタ特性を有するセラミック微粉
末を積層化し、その端面に外部電極を塗布したときの積
層セラミックバリスタの断面図である。
1;絶縁基板、2:内部電極、3:バリスタ特性を有す
るセラミック微粉末、4:外部電極特許出願人 宇部
興産株式会社
第 2
図Fig. 1 is a plan view of an insulating substrate according to the present invention coated with internal electrodes, Fig. 2 is a cross-sectional view of the insulating substrate, and Fig. 3 is a lamination of the insulating substrate and ceramic fine powder having varistor properties. , is a cross-sectional view of a multilayer ceramic varistor with external electrodes coated on its end face. 1: Insulating substrate, 2: Internal electrode, 3: Fine ceramic powder with varistor properties, 4: External electrode Patent applicant Ube Industries, Ltd. Figure 2
Claims (1)
性を有するセラミック微粉末に、有機接着剤、またはガ
ラス粉末及び溶媒を加え、ペースト状とし、これを表裏
両面に電極を形成した絶縁基板上に塗布し、これを積層
後、熱処理を行うことにより基板同士を接着することを
特徴とする積層セラミックバリスタの製造法。In manufacturing multilayer ceramic varistors, an organic adhesive or glass powder and a solvent are added to ceramic fine powder with varistor properties to form a paste, and this is applied onto an insulating substrate with electrodes formed on both the front and back sides. A method for manufacturing a laminated ceramic varistor, characterized in that the substrates are bonded together by heat treatment after lamination.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019783A JPH02201901A (en) | 1989-01-31 | 1989-01-31 | Manufacture of laminated ceramic varister |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1019783A JPH02201901A (en) | 1989-01-31 | 1989-01-31 | Manufacture of laminated ceramic varister |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02201901A true JPH02201901A (en) | 1990-08-10 |
Family
ID=12008926
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1019783A Pending JPH02201901A (en) | 1989-01-31 | 1989-01-31 | Manufacture of laminated ceramic varister |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02201901A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100309597B1 (en) * | 1998-03-17 | 2001-09-26 | 무라타 야스타카 | Material and Paste for Producing Internal Electrode of Varistor, Laminated Varistor, and Method for Producing the Varistor |
-
1989
- 1989-01-31 JP JP1019783A patent/JPH02201901A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100309597B1 (en) * | 1998-03-17 | 2001-09-26 | 무라타 야스타카 | Material and Paste for Producing Internal Electrode of Varistor, Laminated Varistor, and Method for Producing the Varistor |
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