JPH02202178A - Phase locked signal extraction circuit for television signal - Google Patents

Abstract

PURPOSE:To execute the stable extraction of a phase locked signal even when the phase locked signal of positive polarity is adopted to a recording/reproducing system by setting an initial phase and an initial frequency in a horizontal phase locked loop circuit based on the internal phase and frequency after an auxiliary phase locked loop circuit achieves a normal state and executing the initial lead-in operation of the horizontal phase synchronization circuit. CONSTITUTION:In the normal state of an auxiliary phase locked loop circuit 5, the phase and frequency of an auxiliary phase locked signal in an input television signal S1 are almost equal with the internal phase and internal frequency of the auxiliary phase locked loop circuit 5. Accordingly, when the initial pull-in of a horizontal phase locked loop circuit 4 is next executed, the initial phase and initial frequency can be initially set based on the internal phase and internal frequency of the auxiliary phase locked loop circuit 5 and for the horizontal phase locked loop circuit 4, not only the initial phase but also the initial frequency are set to a value extremely close to those of the horizontal phase locked loop signal in the input television signal S1. Thus, even in the case of the recording/reproducing system, for which the difference of the initial frequency is large between a horizontal phase locked reference signal and the horizontal phase locked signal in the input television signal, the stable extraction of the phase locked signal can be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a synchronization extraction circuit for television signals that extracts at least a horizontal synchronization signal from a television signal.

(Prior Art) In recent years, a method called positive polarity synchronization method has been adopted as a format for horizontal and vertical synchronization signals included in television signals, especially when recording and transmitting high-definition television signals. It's coming. The positive polarity synchronization method is a synchronization signal format in which the signal levels of the horizontal and vertical synchronization signals are included in the range of signal levels in which a video signal can exist.

FIG. 4 shows an example of a synchronization signal waveform using the positive polarity synchronization method, and FIG. 5 shows an example of a synchronization signal waveform using the conventional negative polarity synchronization method. As shown in FIG. 5, in the case of the negative polarity synchronization method, the signal level of the horizontal synchronization signal 106 is lower than the signal level range 104 in which the video signal can exist, so it is necessary to separate the input television signal and synchronization signal. By comparing with the reference voltage 105, it is possible to separate the synchronization signal from the container. Further, the horizontal synchronization signal 106 and the vertical synchronization signal 107 can be easily separated by changing the pulse length. However, in the case of the positive polarity synchronization method, the synchronization signal cannot be separated by such a comparison operation between the input television signal and the reference voltage.

FIG. 6 shows the configuration of a synchronization extraction circuit for television signals using the conventionally known positive polarity synchronization method. In the figure, a vertical synchronization signal detection circuit 64 detects a vertical synchronization signal from an input television signal S1, and generates a vertical synchronization identification signal S2 at the time of detection. The vertical synchronization signal waveform of the positive polarity synchronization method is a special pattern that has an extremely low probability of existing in the video signal, for example, as shown at 102 in FIG. 4, the black level and white level of the video signal are changed at a predetermined period. A repeating rectangular wave pattern with black level between lines,
A two-line repeating pattern is set in which the position of the white level is reversed. By extracting this special pattern, the vertical synchronization signal can be detected.

On the other hand, in the horizontal phase synchronization circuit 60, the phase comparator 61
A phase comparison is performed between the horizontal synchronization signal 101 shown in FIG. 4 in the input television signal Sl and the horizontal synchronization reference signal SB which is the output of the frequency division counter 64, and both signals S2.
A phase comparison output S3 corresponding to the phase difference of S8 is supplied to the loop filter 62. The output voltage S4 of the loop filter 62 is supplied as a control input to a voltage controlled oscillator (VCO) 73 to control the frequency of the signal S5 supplied from the voltage controlled oscillator 63 to the frequency divider counter 65.

A positive horizontal synchronization signal is extracted by such a feedback system.

The problem with such a configuration is that the horizontal synchronization signal 101 in the input television signal Sl and the horizontal synchronization reference signal S6
If the phase difference between the phase comparator 61 and the phase comparator 61 exceeds the range in which the phase can be compared, The problem is that the video signal gets mixed in, making it impossible to obtain a normal phase comparison output.

Therefore, when the horizontal phase synchronization circuit 60 starts the pull-in operation, the vertical synchronization identification signal S2 indicates that the phase difference of the horizontal synchronization reference signal S6 is zero with respect to the positive horizontal synchronization signal that is first input after the detection of the vertical synchronization signal. The internal state of the frequency division counter 65 is initialized so as to be close to . Frequency division counter 6
5 divides the output S5 of the voltage controlled oscillator 63 to generate the horizontal synchronization reference signal S6, and the initial value thereof is set to an appropriate value at the time of initial setting. In addition, the loop filter 6
2, the internal state of the voltage controlled oscillator 63 is set so that the output S4 is initially set to a voltage value such that the frequency of the output S5 of the voltage controlled oscillator 63 is set to the center value of the frequency range defined as the frequency of the input signal. be done.

FIG. 7 is a graph showing temporal changes in the phase 7 of the input television signal and the internal phase 72 of the horizontal phase synchronization circuit, with t on the horizontal axis and phase φ on the vertical axis. Since the initial phase difference between 71° and 72 is set close to zero at the time 73 when the vertical synchronization signal is detected, normal pull-in operation will not occur unless the phase difference exceeds the phase comparison range 74 in the transient state during pull-in. Realized.

In this way, in the positive polarity synchronization method, although the synchronization separation method is somewhat complicated, it is possible to allocate the entire signal dynamic range allowed by the transmission path to the video signal. Therefore, for a transmission line of the same quality, adopting the positive polarity synchronization method has the advantage of improving the signal-to-noise ratio of the video signal compared to using the negative polarity synchronization method. Synchronous methods are becoming widely adopted.

By the way, when performing synchronous extraction using the configuration shown in FIG. 6, the initial phase difference can be set to a value close to zero;
The horizontal phase synchronization circuit also has an initial frequency difference, that is, the seventh
There is a difference in slope between the phase change curve 71 of the input television signal and the internal phase change curve 72 of the horizontal phase synchronization circuit in the figure, and the initial frequency difference between the two may become large. In such a case, there is a possibility that the above-mentioned phase difference exceeds the phase comparison possible range 74 during the pull-in operation, making normal operation impossible.

In a transmission system, this initial frequency difference can be estimated to be small to some extent, but for example, in a video tape recorder (
In recording and reproducing systems such as VTRs and video disc players (VDPs), it is necessary to estimate the initial frequency difference largely due to vibrations in the mechanical system.

One possible method for achieving normal pull-in operation even in a state of large initial frequency difference is to increase the loop gain of the phase-locked circuit. By increasing the loop gain, it is possible to reduce the phase difference during the pull-in operation.

However, in the case of a horizontal phase locked circuit, there is a limit to increasing the loop gain. This is because the horizontal synchronization signal used for phase comparison is input only discretely in each horizontal scanning period, so if the loop gain is made too large, the stability conditions of the feedback system for the discrete value series will no longer be satisfied, and the horizontal phase synchronization signal This is because it becomes unstable.

Furthermore, widening the phase comparison range for the horizontal synchronizing signal is also effective in widening the range in which the pull-in operation can be performed normally. However, in order to widen the phase comparison range, it is necessary to lengthen the section length of the horizontal synchronizing signal and shorten the section length of the video signal, so there is a limit in practice.

(Problems to be Solved by the Invention) As mentioned above, when performing the initial pull-in operation of the horizontal phase synchronization circuit using a positive horizontal synchronization signal (7. In order to operate normally without the phase difference of the horizontal synchronization reference signal exceeding the phase comparison range, the conventional method of setting only the initial phase of the horizontal synchronization reference signal by the detection timing of the vertical synchronization signal Appropriate initial settings cannot be made for the initial frequency difference between the horizontal synchronization reference signals.

Therefore, when a conventional synchronization signal extraction circuit is applied to a system where the initial frequency difference may be large, such as a television signal recording/reproducing system, there is a risk that normal pull-in operation may not be achieved. A dot had appeared.

The present invention provides a synchronization extraction circuit for television that can realize normal pull-in operation even when the initial frequency difference between the horizontal synchronization signal in the input television and the horizontal synchronization reference signal in the horizontal phase synchronization circuit is large. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) In addition to a vertical synchronization signal detection circuit and a horizontal phase synchronization circuit, the present invention uses The main point is to provide an auxiliary phase synchronization circuit that extracts an auxiliary synchronization signal that repeats the same waveform in a short period.

This auxiliary phase synchronized circuit performs an initial pull-in operation after the initial phase and initial frequency are set at the vertical synchronization signal detection timing of the vertical synchronization signal detection circuit. After the initial phase and initial frequency are set based on the frequency,
Perform initial pull-in operation.

The initial phase and initial frequency in the auxiliary phase-locked circuit are set by, for example, initializing the internal state of the frequency division counter and the output of the loop filter in the auxiliary phase-locked circuit at the vertical synchronization signal detection timing of the vertical synchronization signal detection circuit. achieved by

Further, the initial phase and initial frequency in the horizontal phase synchronized circuit are set by, for example, initializing the internal state of the frequency division counter in the horizontal phase synchronized circuit at the end timing of the auxiliary synchronization signal extracted by the auxiliary phase synchronized circuit, and This is done by initializing the output of the loop filter in the horizontal phase-locked circuit based on the output of the loop filter in the auxiliary phase-locked circuit.

(Function) Since the phase comparison period of the auxiliary phase-locked circuit is shorter than the horizontal scanning period, which is the phase comparison period of the horizontal phase-locked circuit, it is possible to maintain stability conditions even under a larger loop gain compared to the horizontal phase-locked circuit. Since the customer is satisfied, the time required for retraction is also shortened. For example, set the period of the auxiliary synchronization signal to 17 times the horizontal scanning period.
If it is 100, even if the loop gain of the auxiliary phase-locked circuit is set to 100 times the loop gain of the horizontal phase-locked circuit, the stability of both is the same, and the pull-in time is 1/100.

Therefore, in the auxiliary phase synchronization circuit, the pull-in operation is performed stably within the vertical retrace section, and moreover, the steady state is easily achieved.

In addition, in the steady state of the auxiliary phase-locked circuit, the phase and frequency of the auxiliary synchronization signal in the input television signal and the internal phase and internal frequency of the auxiliary phase-locked circuit are almost equal. When performing this, the initial phase and initial frequency are adjusted to the internal phase and
Initial settings can be made based on the internal frequency. As a result, not only the initial phase but also the initial frequency of the horizontal phase synchronization circuit is set to a value extremely close to that of the horizontal synchronization signal in the input television signal, so that the horizontal synchronization reference signal and the horizontal synchronization signal in the input television signal are Even in the case of a recording/reproducing system where the initial frequency difference is large, normal pull-in operation is performed.

(Embodiment) FIG. 1 shows a configuration diagram of a television signal synchronization extraction circuit according to an embodiment of the present invention. In Figure 1, terminal 1
A television signal S1 including a positive polarity synchronizing signal as shown in FIG. 2 is input to the terminal. This input television signal 1 is converted into a digital signal by an A/D converter 2 and then input to a vertical synchronization signal detection circuit 3, a horizontal phase synchronization circuit 4, and an auxiliary phase synchronization circuit 5.

The vertical synchronization signal detection circuit 3 receives an input television signal Sl.
A positive polarity vertical synchronization signal 102 shown in FIG. 2 is detected to generate a vertical synchronization identification signal S2.

The horizontal phase synchronization circuit 4 includes a first phase comparator 11, a first loop filter 12, and a first voltage controlled oscillator (VCO) 1.
3 and a first frequency division counter 14 as a horizontal synchronization reference signal generation circuit. The phase comparator 11 detects the horizontal synchronizing signal 10 shown in FIG. 1 in the input television signal Sl.
1 and the horizontal synchronization reference signal S which is the output of the frequency division counter 14.
6 and outputs a phase comparison signal S3 corresponding to the phase difference between the two. This phase comparison signal S3 passes through the loop filter 12 and becomes a control voltage S4 that controls the oscillation frequency of the voltage controlled oscillator 13.

The output signal S5 from the voltage controlled oscillator 13 is frequency-divided by the frequency division counter 14, and becomes the horizontal synchronization reference signal S6.

The auxiliary phase locked circuit 5 includes a second phase comparator 21, a second loop filter 22, and a second voltage controlled oscillator (VCO) 2.
3 and a second frequency division counter 24 as an auxiliary synchronization reference signal generation circuit. The phase comparator 21 detects the auxiliary synchronization signal 10 shown in FIG. 1 in the input television signal St.
3 and the auxiliary synchronization reference signal S which is the output of the frequency division counter 24.
12 and outputs a phase comparison signal S9 corresponding to the phase difference between the two. This phase comparison signal S9 passes through the loop filter 22 and becomes a control voltage S10 that controls the oscillation frequency of the voltage controlled oscillator 23.

The output signal Sll from the voltage controlled oscillator 23 is frequency-divided by the frequency division counter 24 to become the auxiliary synchronization reference signal S12.

The vertical synchronization identification signal S2 output from the vertical synchronization signal detection circuit 3 is supplied to the auxiliary phase synchronization circuit 5, and the initial phase of the auxiliary phase synchronization circuit 5 is determined at the timing of this vertical synchronization identification signal S2 (vertical synchronization signal detection timing). and an initial frequency are set.

That is, in the vertical phase synchronization circuit 5, the phase difference between the first auxiliary synchronization reference signal S12 generated after receiving the vertical synchronization identification signal S2 and the first auxiliary synchronization signal 103 that arrives after the vertical synchronization signal 102 is The initial phase is set by setting the internal state of the frequency division counter 24 so that it is close to zero. Further, the frequency of the output signal Sit of the voltage controlled oscillator 23 is
The initial frequency is set by initializing the output voltage SlO of the loop filter 22 so that it becomes the center value of the frequency range assumed to be the frequency of .

After the auxiliary phase synchronization circuit 5 is initialized in this way,
An initial pull-in operation is started in response to the auxiliary synchronization signal 103. As shown in FIG. 2, the auxiliary synchronizing signal waveform], 03 is located within the vertical retrace interval and after the vertical synchronizing signal]02, and is a signal waveform that repeats the same waveform at a period shorter than the horizontal scanning period. In the auxiliary phase synchronization circuit 5, the auxiliary synchronization signal 103 in the input television signal Sl and the auxiliary synchronization reference signal S12 outputted from the frequency dividing counter 24 are passed to the phase comparator 2.
1, the phase comparison signal S9 output from the phase comparator 21 is input to the loop filter 22, and the frequency of the output signal Sll of the voltage controlled oscillator 23 is controlled by the output voltage SIO of the loop filter 22, thereby providing feedback. Configure the system and perform the pull-in operation.

Here, for the auxiliary phase-locked circuit 5, the initial phase is set in the same way as the horizontal phase-locked circuit in the conventional example, and the initial frequency is simply set to the center value of the expected frequency range. Since the second comparison period (the repetition period of the auxiliary synchronization signal 103) is shorter than the horizontal scanning period, the loop gain of the auxiliary phase synchronization circuit 5 is set larger than that of the horizontal phase synchronization circuit in the conventional example. However, the retracting operation can be performed in a short time without losing stability.

After the auxiliary phase synchronization circuit 5 reaches a steady state, the frequency division counter 24 generates the auxiliary synchronization end identification signal S13 at the timing when the auxiliary synchronization signal SL2 ends. At the timing of this auxiliary synchronization end identification signal S13, the initial phase and initial frequency of the horizontal phase synchronization circuit 4 are set based on the steady phase and steady frequency in the auxiliary phase synchronization circuit 5.

That is, in the horizontal phase synchronization circuit 4, after the vertical synchronization end identification signal S13 is applied, the first horizontal synchronization reference signal S6 generated and the first positive horizontal synchronization signal 101 after the end of the auxiliary synchronization signal 103 are combined. The initial phase is set by setting the internal state of the first frequency dividing counter 14 so that the phase difference is close to zero. Also,
Auxiliary phase synchronization circuit 5 at the end of the auxiliary synchronization signal 103
Based on the output voltage SIO of the loop filter 22 in the
The loop filter in the horizontal phase-locked circuit 4 is configured such that the frequency of the output signal S4 of the voltage-controlled oscillator 13 in the horizontal phase-locked circuit 4 is the same as the frequency of the output signal Sll of the voltage-controlled oscillator 23 in the auxiliary phase-locked circuit 5. 12 output voltage S4
By initializing , the initial frequency is set.

After the horizontal phase synchronization circuit 4 is initialized in this way, it receives the positive horizontal synchronization signal 101 as in the conventional example.
Performs an initial pull-in operation.

In this way, in the horizontal phase synchronization circuit 4, not only the initial phase but also the initial frequency are set to values close to the phase and frequency of the horizontal synchronization signal 101 in the input television signal Sl, and then the pull-in operation is performed. Compared to the case where only the initial phase is set as in , it is possible to expand the frequency range of the input television signal in which the pull-in normally operates.

In the steady state after the initial pull-in operation is normally performed as described above, a signal correctly synchronized with the horizontal synchronization signal 101 in the input television signal St is obtained from the frequency division counter 14 in the horizontal phase synchronization circuit 4. and output from terminal 7 as a horizontal synchronizing signal S7. Furthermore, by dividing the horizontal synchronization signal S7 by the frequency division counter 6,
A vertical synchronization signal S8 correctly synchronized with the horizontal synchronization signal 102 in the input TVIL signal St is obtained and output from the terminal 8.

In FIG. 1, the sampling clock pulse of the A/D converter 2 is provided with an output signal S5 of the voltage controlled oscillator 13 in the horizontal phase synchronization circuit 4. Further, the digitized input television signal S1 outputted from the A/D converter 2 is sent to a next-stage signal processing circuit (not shown) together with a signal S5 serving as a clock signal and processed.

FIG. 3 shows a block diagram of a television signal synchronization extraction circuit according to another embodiment of the present invention. In this embodiment, the horizontal phase synchronization circuit and the auxiliary phase synchronization circuit use the same loop filter 32. The voltage controlled oscillator 33 is shared, and the switch 31 selectively selects either the output S3 of the phase comparator 11 in the horizontal phase-locked circuit or the output S13 of the phase comparator 21 in the auxiliary phase-locked circuit to the loop filter 32. The input signal S14 is set as the input signal S14.

Signal S by switch 31 3. Which one of S13 to select is controlled by the mode determination signal S17 output from the mode determination circuit 34. That is, the mode determination circuit 34 inputs the vertical synchronization identification signal S2 from the vertical synchronization signal detection circuit 3 and the auxiliary synchronization end identification signal S13 from the frequency division counter 24 in the auxiliary phase synchronization circuit 5, and outputs the vertical synchronization identification signal Auxiliary synchronization end identification signal S from the time of generation of S2
13, the switch 31 selects the output S13 of the phase comparator 21 in the auxiliary phase synchronization circuit, and after the generation of the auxiliary synchronization end identification signal S13, the output S13 of the phase comparator 21 in the horizontal phase synchronization circuit is selected. A mode determination signal S17 is output so that the output S3 of No. 11 is selected. Furthermore, the mode determination signal S17 is transmitted to the loop filter 32.
The parameters (filter coefficients, etc.) of the loop filter 32 are set to optimal values for each phase-locked loop of the horizontal and auxiliary phase-locked circuits.

In the case of this embodiment, the output voltage S15 of the loop filter 32 immediately before transition to the horizontal phase-locked loop is a voltage corresponding to the input signal frequency extracted in the auxiliary phase-locked loop, so in the embodiment of FIG. Similarly, the initial frequency is set in the horizontal phase-locked loop.

[Effects of the Invention] According to the present invention, an auxiliary phase synchronization circuit is provided which operates on an auxiliary synchronization signal having a repetition period shorter than the horizontal scanning period, which is inserted into a vertical retrace interval of an input television signal, and By setting the initial phase and initial frequency in the horizontal phase synchronization circuit based on the internal phase and frequency after the phase synchronization circuit reaches a steady state, and performing the initial pull-in operation of the horizontal phase synchronization circuit, the positive polarity synchronization signal is Even when the frequency range assumed as the frequency of the input television signal upon extraction is wide, the pull-in operation can be performed normally. Therefore, the present invention enables stable synchronization signal extraction even when a positive polarity synchronization signal is employed in a recording/reproduction system in which the initial frequency difference between the frequency of the television signal and the frequency in the horizontal phase synchronization circuit is large.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a synchronization extraction circuit for television signals according to an embodiment of the present invention, FIG. 2 is a diagram showing an example of a synchronization signal waveform of a positive synchronization method including an auxiliary synchronization signal, and FIG. A configuration diagram of a television synchronization extraction circuit according to another embodiment of the present invention, FIG. 4 shows an example of a synchronization signal waveform in a positive polarity synchronization method, and FIG. 5 shows an example of a synchronization signal waveform in a negative polarity synchronization method. 6 is a block diagram of a conventional synchronization extraction circuit for a positive polarity synchronization type television signal, and FIG. 7 is a diagram showing the time course of the input television signal phase and the internal phase of the horizontal synchronization circuit. DESCRIPTION OF SYMBOLS 1... Television signal input terminal, 2... A/D converter, 3... Vertical synchronization signal detection circuit, 4... Horizontal phase synchronization circuit, 5... Auxiliary phase synchronization circuit, 6. ... Frequency division counter, 7... Horizontal synchronizing signal output terminal, 8... Vertical synchronizing signal output terminal, 11.21... 15th. Second phase comparison 5.12.22...1st. second loop filter, 13.23...first. a second voltage controlled oscillator;
14°24...1st. Second frequency dividing counter, 31...
- Switcher, 32... Loop filter, 33... Voltage controlled oscillator, 34... Mode determination circuit, 101...
Positive polarity horizontal synchronization signal, 102... Positive polarity vertical synchronization signal, 103... Auxiliary synchronization signal. Applicant's agent Patent attorney Takehiko Suzue

Claims (3)

[Claims] (1) A horizontal phase synchronization circuit that extracts a horizontal synchronization signal having the same waveform for each horizontal scanning period in an input television signal, and a vertical synchronization signal having the same waveform for each frame or field period in the input television signal. and an auxiliary phase synchronization circuit that extracts an auxiliary synchronization signal that repeats the same waveform a plurality of times with a period shorter than a horizontal scanning period inserted into the vertical retrace interval of the input television signal. , the auxiliary phase synchronized circuit performs an initial pull-in operation after the initial phase and initial frequency are set at the vertical synchronization signal detection timing of the vertical synchronization signal detection circuit, and the horizontal phase synchronization circuit performs a steady state in the auxiliary phase synchronization circuit. A synchronization extraction circuit for a television signal, characterized in that an initial pull-in operation is performed after an initial phase and an initial frequency are set based on a phase and a steady frequency. (2) a first phase comparator, a first loop filter whose input is the output of the first phase comparator, a first voltage-controlled oscillator whose control input is the output of the first loop filter, and a first
A first frequency dividing counter divides the output of the voltage controlled oscillator, and a first phase comparator divides the output of the voltage controlled oscillator into a horizontal synchronizing signal having the same waveform for each horizontal scanning period in the input television signal.
By comparing the phase with the output of the dividing counter,
a horizontal phase synchronization circuit that extracts a horizontal synchronization signal in the input television signal; a vertical synchronization signal detection circuit that detects a vertical synchronization signal having the same waveform for each frame or field period in the input television signal; a second phase comparator, a second loop filter whose input is the output of the second phase comparator, a second voltage controlled oscillator whose control input is the output of the second loop filter, and a second voltage controlled oscillator. A second frequency division counter that divides the output, and a second phase comparator that helps repeat the same waveform multiple times at a period shorter than the horizontal scanning period inserted into the vertical retrace interval of the input television signal. an auxiliary phase synchronization circuit that extracts an auxiliary synchronization signal from the input television signal by comparing the phases of the synchronization signal and the output of the second frequency division counter, the auxiliary phase synchronization circuit extracting the auxiliary synchronization signal from the vertical synchronization signal; After the internal state of the second frequency division counter and the output of the second loop filter are initialized at the vertical synchronization signal detection timing of the detection circuit, an initial pull-in operation is performed, and the horizontal phase synchronization circuit is connected to the auxiliary phase synchronization circuit. After the internal state of the first frequency division counter is initialized at the end timing of the auxiliary synchronization signal extracted in and the output of the first loop filter is initialized based on the output of the second loop filter, A synchronization extraction circuit for television signals characterized by performing a pull-in operation. (3) The television signal synchronization extraction circuit according to claim 1 or 2, wherein at least one of the loop filter and the voltage controlled oscillator is shared by the horizontal phase synchronization circuit and the auxiliary phase synchronization circuit.