JPH02208964A - semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a semiconductor memory device and a technology for increasing its speed, and relates to a technology that is effective when applied to, for example, a DRAM (dynamic random access memory). [Prior art] Semiconductor storage device, for example, DRAM using MISFET
When writing/reading data to/from any memory cell of the above-mentioned DRAM, which has a memory cell array in which a plurality of memory cells are arranged in a matrix, the row address decoder and column address decoder correspond to external address signals. A word driver drives the word line of the row to be selected to a selection level in response to a selection signal from a six-row address decoder which selects a row and column and addresses memory cells. The word line serves as the gate electrode of the selection MISFET of the memory cell. The gate electrode serves as a mask when forming the source or drain electrode of the selection MISiFET by ion implantation. The gate electrode is used in the heat treatment process after ion implantation. Since it is necessary to withstand the heat, it is formed of polycrystalline silicon, for example. As the degree of integration of the semiconductor memory device increases. Memory cell arrays become larger and word lines become longer. Polycrystalline silicon has a high resistance value, so the resistance value of the word line is very high, and the CR time constant is also large, causing a delay in the signal arrival time from the word driver. A word shunt line made of a material with a low resistance value, such as aluminum, is provided in parallel with the word line immediately adjacent to the word line, and the word line drive signal is transmitted by connecting the food shunt line and the word line. Techniques for reducing delays can be adopted. An example of a document describing a word shunt line is Japanese Patent Laid-Open No. 106693/1983. [Problems to be Solved by the Invention] In order to improve the degree of integration of semiconductor memory devices, it is necessary to reduce the dimensions of memory cells and also reduce the width of interconnects, such as word shunt lines, that are coupled to the memory cells. In a 16 Mbit DRAM, which must be formed thin, the word shunt line width is expected to be approximately 0.6 to 0.8 cm. Word shunt lines are often made of aluminum, but when such thin aluminum is used as electrical wiring, disconnection occurs due to the so-called electromigration phenomenon in which the wiring metal exchanges kinetic energy with carriers and moves. Simply EM
The inventor has discovered that there is a problem in that wire breakage due to so-called stress migration (hereinafter simply referred to as SMD) in which strain occurs in the wiring material due to stress from an interlayer insulating film, etc. becomes noticeable. . An object of the present invention is to provide a semiconductor memory device that can prevent EMD and SMD of word shunt lines in response to the demand for higher integration. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. [Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows. That is, adjacent word shunt lines are vertically shifted and formed in separate layers. In addition, the sum of undesirable loads to be driven by the word driver, such as the parasitic capacitance and wiring resistance of multiple word shunt lines selected simultaneously from the stacked word shunt lines of the semiconductor memory device, is calculated for each word line. For example, if the word shunt line is a two-layer wiring, when selecting an even number of word shunt lines from among the word shunt lines at the same time, the upper layer wiring One or more pairs of word shunt lines are selected, with the constructed food shunt line and the word shunt line constructed from the lower layer wiring as a pair. (Function) According to the above-mentioned means, since adjacent word shunt lines are formed above and below in separate layers with insulating films interposed therebetween, it is necessary to provide a distance to insulate the adjacent word shunt lines. Therefore, the width of the word shunt line can be made wider by, for example, the above-mentioned separation distance or more, thereby achieving improved resistance to EMD and SMD. If the upper and lower layers are formed in separate layers, the undesired load on the word shunt line formed in the lower layer will be larger than that of the word shunt line formed in the upper layer.The memory cell array is divided into scattered memory mats. In such a case, when word shunt lines are selected simultaneously in each memory mat, the word shunt lines selected at the same time are driven by a word driver according to the selection signal of the address decoder. The above address decoder, which has a selection logic that always makes the load on the entire line the same, keeps the load that the word driver must drive constant in any addressing operation, which guarantees stable access operations and high-speed access. [Embodiment] Fig. 2 shows the basic configuration of a DRAM equipped with a word shunt line, which is an embodiment of the present invention. In the center of the DRAM shown in this figure, a memory mat 30A,
30B, and the memory mats 30A, 30B are, for example, one-transistor type memory cells 31A, 31B.
It is constructed by arranging it in a matrix. Memory mat 30A
, the selection terminals of memory cells arranged in a matrix are coupled to corresponding word lines 8A for each row, and the data input/output terminals of the memory cells are coupled to complementary bit lines 14A, 14B. It is made of polycrystalline silicon and also serves as the gate electrode of the selection transistor of the memory cell. The word line 8A is divided in the middle, and the divided word line 8A is commonly connected to a word shunt line 10A made of aluminum having a lower resistance than polycrystalline silicon. The word line 8A is divided into a plurality of pieces so that disconnection of the word shunt line 10A can be detected at the wafer stage. Since the word line 8A is divided, the word shunt line 10 is subjected to a continuity test or a function test.
It becomes easy to detect the disconnection of A, and it is possible to eliminate defective wafers before sending them to the assembly process. Since the aluminum constituting the word shunt line 10A has a lower resistance value than the polycrystalline silicon constituting the word line 8A, the CR time constant of the word shunt line 10A is determined by forming the word line 8A only from polycrystalline silicon. The drive signal or selection signal from the word driver is transmitted to the word shunt line 10A.
can be transmitted at high speed up to terminals. Similarly, in the memory mat 30B, the memory cell 31B
The data input/output terminals of are coupled to complementary bit lines 15A and 15B, and the word lines 8B forming the same row are separated in the middle and commonly connected to a word shunt line 10B. Here, the word lines 8A and 8B are not limited to polycrystalline silicon, but may be made of a high melting point metal such as W, Ti, Ta, Mo, or a multilayer film of polycrystalline silicon and the above-mentioned high melting point metal. Note that in each memory mat 30A, 30B, memory cells 31A, 31B and word lines 8A, 8B. Word shunt line 10A, IOB, bit line 14A, 1
A portion of each of 4B, 15A, and 15B is representatively illustrated. The word shunt lines 10A and IOB are coupled to the output terminals of the word driver 34 and are connected to the one-row address recorder 33.
Based on the output selection signal of , a total of two wires, one for each memory mat, are driven to the selection level at the same time. Complementary bit line 14A on the side of memory mat 30A. 14B is connected to the common data line 45 via the column selection circuit 42A.
A, 45B are commonly connected, and similarly memory mat 3
The complementary bit lines 15A and 15B on the 0B side are also connected to the column selection circuit 42.
It is commonly connected to common data lines 46A and 46B via B. Each common data line is coupled to read/write circuit 44 via multiplex circuit 60. The read/write circuit 44 is connected to the outside via a data input/output buffer 50. To access any memory cell of the DRAM of this embodiment, first, a row address signal is applied to the row address buffer 32 from the outside, and an internal complementary address signal output from the row address buffer 32 is sent to the row address decoder 33. Based on the signal from the row address decoder 33, the word driver 34 selects and drives one word line 8A, 8B for each of the two divided memory mats 30A, 30B. Next, the column address signal is applied to a column address buffer 40 and converted into an internal complementary address signal, which is decoded by a column address decoder 41. The column selection circuit 42A uses the decoded signal. Necessary complementary bit lines 14A, 14B, and 15A are connected via selection switches (not shown) included in 42B. Common data lines 45A respectively correspond to 15B. 45B, 46A, and 46B are made conductive. This results in
Memory cell 31A in memory mat 30A and memory cell 31B in memory mat 30B are addressed. In the DRAM, which of the two addressed memory cells is accessed is not particularly limited, but is determined by a predetermined 1 bit of a column address signal supplied from the outside. The multiplex circuit 60 is selectively controlled and one of the common data lines 45A, 45B, or 46A, 46B is connected to the read/write circuit 44. Therefore, write data is given to one of the two memory cells selected by the 5th row address signal and the column address signal, or the data of one of the memory cells is Output to the outside. In DRAM, memory cell data is refreshed within a certain period of time to prevent the stored information stored in the storage capacitor of the memory cell in the form of charge from decreasing and being lost over time. It is necessary to play the . In order to refresh all memory cells in the memory mats 30A and 30B, a built-in refresh counter (not shown) sequentially generates refresh address signals while activating a sense amplifier (not shown), and supplies the refresh address signals to the row address decoder 33. The word shunt lines are selected one after another. In particular, as in this embodiment, the memory cell array corresponding to 1 bit of data to be read/written is configured with 3OA and 30B in two memory mats, and one word line selection operation simultaneously selects two lines. If configured to drive the word shunt line, the operating time to refresh the entire DRAM can be halved, and the system The operational efficiency of DRAM can be improved. FIG. 3 shows a plan view of the main part of the memory mat of the DRAM, and this figure shows a memory cell forming region 1 and a shunt region 2. The memory cell forming region 1 will be explained based on FIG. 3 and FIG. 4, which is a sectional view taken along the line B--B of the memory cell forming region 1. The memory cells formed in the memory cell formation region 1 are of a one-transistor type, although not particularly limited, and include an N-channel type selection MISFET Qi formed on the P-type semiconductor substrate 3 and a planar type storage device directly connected thereto. It is composed of a capacitive element Ci. The source or drain electrodes 4 and 5 of the M I S F E T Q i are formed on the surface of the semiconductor substrate 3 with a required interval between them, and a gate insulating film 19 made of silicon oxide is interposed between them to form polycrystalline silicon. A gate electrode 6 consisting of, for example, is formed to also serve as a word line 8 in an even numbered column. For example, word lines 8' in odd columns are formed in adjacent rows of memory cells arranged in the same row. On the upper layer of the word line 8, in parallel with the word line 8, word shunt lines 1o in even columns, for example, are formed using a second layer of aluminum wiring. Further, in the upper layer of the word line 8' there is a word shunt line 8' in parallel with the word line 8', for example, a word shunt line 1 in an odd column.
0' is 3F! The word shunt line 10' is formed of aluminum wiring, but the word shunt line 10' is formed from the word shunt line 1o.
It is formed in the upper layer of the wiring layer in which is formed. That is, the plurality of word shunt lines typically shown in FIG. Adjacent ones are formed in separate layers by shifting them up and down. One source electrode or drain electrode 5 of the M I S F E T Q i is a planar storage capacitor element Ci.
It is connected to the. The planar storage capacitor element Ci includes a lower electrode 7 formed on the semiconductor substrate 3 and a plate electrode 17 formed on the surface of the semiconductor substrate. and a dielectric film 16 formed between the lower electrode 7 and the plate electrode 17. The plate electrode 17
An opening 17A is formed in the upper layer of the MISFETQi. On the upper layer of the plate electrode 17, word lines 8' made of polycrystalline silicon, for example, in odd columns are formed with an insulating film interposed therebetween. An interlayer insulating film 20 is deposited on the surface of the semiconductor substrate including the storage capacitor element Ci and the word line 8', and the interlayer insulating film 20 is connected to the source or drain electrode 4 through a contact hole 9. A bit line 14 is formed. An interlayer insulating film 21 is deposited on the upper layer of the interlayer insulating film 20 including the bit line 14, and on the interlayer insulating film 21, for example, word shunt lines 1 in even columns are deposited.
0 is formed. An interlayer insulating film 22 is deposited on the upper layer of the interlayer insulating film 21 including the word shunt lines 10, and on the interlayer insulating film 22, for example, odd columns of word shunt lines 10' are formed. A passivation film 23 is formed on the upper layer of the interlayer insulation fl122 including the word shunt line 10'. Note that 18 is an insulating film for isolation between elements made of silicon oxide. Next, the shunt region 2 shown in FIG. 3 will be explained based on FIG. 3 and FIG. 1, which is a sectional view taken along the line A-A of the shunt region 2. As already mentioned, word lines 8 in even columns, for example, are connected in shunt regions to word shunt lines 10 in even columns, and word lines 8', for example in odd columns, are connected in shunt regions to word shunt lines 10 in odd columns, for example. It is connected to the shunt line 10'. An interlayer insulating film 20 made of silicon oxide is deposited on the word lines 8, 8', and a contact hole 20a is formed in the interlayer insulating film 20 at a position corresponding to the word line 8, 8'. ing. The above contact hole 20a
Pad electrodes 11 and 11' made of aluminum are respectively formed on the interlayer insulating film 20 so as to be connected to the word line 8.8' via the pad electrodes 11 and 11'. Above pad electrode 1
1 and 11' are formed at the same time when forming the bit line 14 composed of the first layer aluminum wiring. An interlayer insulating film 21 made of silicon oxide is deposited on the interlayer insulating film 20 including the pad electrodes 11 and 11'.
Through holes 21a and 21b are formed in this interlayer insulating film 21 at positions corresponding to the pad electrodes 11 and 11'. Even-numbered rows of word shunt lines 10 are formed on the interlayer insulating film 21 so as to be connected to the pad electrodes 11 through the through holes 21a. Further, the pad electrode 1 is connected to the pad electrode 1 through the through hole 21b.
Pad electrode 1 made of aluminum to be connected to 1'
2 is formed. Word shunt line 1 in the even numbered columns above
0 and the pad electrode 12 are formed at the same time. An interlayer insulating film 22 made of silicon oxide is deposited on the interlayer insulating film 21 including the word shunt line 10 and the pad electrode 12, and a through hole 22a is formed in the interlayer insulating film 22 on the pad electrode 12. It is formed. For example, word shunt lines 10' made of aluminum and arranged in odd numbers are formed on the interlayer insulating film 22 so as to be connected to the pad electrodes 12 through the through holes 22a. The shunt is performed in the shunt region 2 where no memory cell exists, and this is because the first or second aluminum wiring layer is used to form the pad electrode. In this way, since the adjacent word shunt lines 10 and 10' are formed in separate layers above and below with an insulating film in between, it is possible to reduce the lateral distance between the adjacent word shunt lines, This allows the width of the word shunt line to be made wider than before to prevent EMD and SM, even when achieving the same or even higher degree of integration than before.
It becomes possible to improve resistance to D. In addition, since adjacent word shunt lines are formed in separate layers above and below, it is possible to increase the distance between adjacent word shunt lines compared to conventional methods while improving resistance to EMD and SMD in relation to the required degree of integration. is also possible. This makes it possible to reduce undesired coupling capacitance between adjacent word shunt lines. When a word shunt line to be selected is driven to a selection level, the potential of an adjacent word shunt line that should not be selected increases undesirably due to the action of the coupling capacitance, causing the threshold of the selection transistor to rise. If the value voltage is exceeded, multiple word lines in different rows will be selected at the same time, leading to memory cell data conflict and data write/write errors.However, as mentioned above, the coupling capacitance should be reduced. By doing so, the risk of such an abnormality occurring can be eliminated. A passivation film 23 made of, for example, nitride is formed on the interlayer insulating film 22 including, for example, the odd-numbered word shunt lines 10'. As explained with reference to FIG. 2, in the memory cell selection operation of this embodiment, one word shunt line is selected from each of the two divided memory mats 30A and 30B. When selecting a word shunt line formed in the upper layer, the load for driving it is such that the capacitance of the upper layer shunt line with respect to the semiconductor substrate is smaller than the load for driving the word shunt line in the lower layer. Because it is smaller than that of the shunt wire, it becomes smaller. In this way, the load on the word shunt line formed in the upper layer and the load on the word shunt line formed in the lower layer are slightly different; The row address decoder is provided with selection logic such that one of the lines is a word shunt line formed in an upper layer and the other is a word shunt line formed in a lower layer. That is, when a required address signal is supplied to the row address decoder, one of the word shunt lines selected one by one from each memory mat in response to this address signal is the word shunt line formed in the upper layer. , the other is a word shunt line formed in the lower layer. In particular, in this embodiment, the word shunt lines of the memory mat 30A are formed alternately in the order of the lower layer and the upper layer from the left, and the word shunt lines of the memory mat 30B are formed alternately in the order of the upper layer and the lower layer from the left.
Upper layer word shunt lines and lower layer word shunt lines are alternately coupled to each output terminal of the word driver in pairs. Therefore, regardless of the row address signal supplied to the row address decoder, the loads on the two word shunt lines to be driven by the word driver are always constant, enabling high-speed operation. If the word shunt lines selected at the same time are both upper layer word shunt lines and lower layer word shunt lines, the case where two lower layer word shunt lines are selected is compared to the case where two upper layer word shunt lines are selected. Since the load is larger, the CR time constant is also larger, and the arrival time of the drive signal is relatively delayed. Therefore, internal timing settings must be adjusted to match the slow access time when two lower layer word shunt lines are selected. According to the above embodiment, the following effects are obtained. (1) Adjacent word shunt lines 10 and 10' are formed in separate layers with vertical shifts via an insulating layer.
The distance between the word shunt lines corresponding to adjacent memory cells can be reduced, and the word shunt lines 10 and 10
' can be formed wider than before to improve resistance to EMD and SMD. (2) Since the distance between adjacent word shunt lines 10 and 10' can be made wider than before, the undesired coupling capacitance formed by the two can be reduced.
A word shunt line that should be unselected is not erroneously set to a selected level, and thereby data read/write abnormalities due to coupling capacitance can be prevented. (3) The row address decoder 33 has one word shunt line 10A from each of the two memory mats. When selecting 10B, two word shunt lines formed in different wiring layer areas above and below are always selected, so the overall load of the two selected word shunt lines is always the same, achieving high-speed access. can do. Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that the present invention is not limited thereto and can be modified in various ways without departing from the gist of the invention. For example, in this embodiment, the storage capacitance element of the memory cell is of a planar type, but it is not necessarily limited to this, and a stacked type or trench type storage capacitance element can be adopted as appropriate. FIG. 5 shows a cross-sectional view of the essential parts of a memory cell when a stacked storage capacitor element is used.The stacked storage capacitor element Cs shown in the figure has a three-dimensional structure, so it is better than a planar type one. A large storage capacity can be obtained with a small cell area. In addition, since the charge storage capacitor part does not require a diffusion layer region, it is expected that the soft error occurrence rate due to alpha rays can be improved. The other electrode of the storage capacitor element Cs which is also common to the elements is shown. Further, the same reference numerals are used for the same members as in this embodiment, and detailed description thereof will be omitted. FIG. 6 shows a cross-sectional view of the main part of a memory cell when a trench-type storage capacitor element is used. The trench-type storage capacitor element Ct shown in the figure is formed by digging a groove in a semiconductor substrate. Therefore, a large storage capacity can be obtained with a smaller cell area than a stacked type. As memory cells become smaller in this way, there is an increasing need for techniques for forming every other word shunt line in a separate layer, as shown in this application. In FIG. 6, 25 is one electrode of the trench type storage capacitance element Ct, 26 is the other electrode of the storage capacitance element Ct which is also common to other storage capacitance elements, 27 is the lining film, and 28 is the above electrode. 26 shows a conductive area for connecting two comrades. Incidentally, in FIGS. 5 and 6, the same reference numerals are used for the same members as in this embodiment, and detailed description thereof will be omitted. Furthermore, in this embodiment, the memory mat is divided into two parts for one bit of read/write data. The invention is not necessarily limited to this, and the number of divisions may be further increased, or a memory mat may be configured for each bit. Further, in this embodiment, the word shunt lines are formed in two layers, upper and lower, but the word shunt lines are not necessarily limited to this, and may be formed in 3M or 4M layers. In this case, it is necessary to take into consideration the disadvantage that the address decoding logic for always keeping the load constant across the plurality of word shunt lines to be selected becomes complicated. Further, in this embodiment, the material of the word shunt wire is aluminum, but it is not necessarily limited to this, and high-melting point metals such as tungsten and molybdenum, or silicides thereof may be used as appropriate. Further, in this embodiment, a pad electrode was used to connect the word shunt line and the word line, but the invention is not limited to this, and a contact hole penetrating two or three layers of interlayer insulating film may be formed. However, there is no problem in adopting a method of connecting the word shunt line and the word line through the contact hole. In the above explanation, the invention made by the present inventor was mainly applied to DRAM, which is the background field of application, but the present invention is not limited thereto, and can be applied to other semiconductors such as SRAM. The present invention, which can be widely used in storage devices, can be applied to at least those having a word shunt line.

【Effect of the invention】

Among the inventions disclosed in this application, the effects obtained by typical ones are as follows. In other words, since adjacent word shunt lines are formed in separate layers above and below, the width of the word shunt lines can be made wider;
This has the effect of preventing EMD and SMD from occurring in the word shunt line. In addition, since the coupling capacitance between adjacent word shunt lines can be reduced, it is possible to prevent a situation where a word shunt line that should be unselected becomes actually selected and causes an abnormality in read/write data. It has the effect of being able to. Furthermore, when the row address decoder selects multiple word shunt lines at the same time, a selection logic is developed so that the load on the multiple word shunt lines to be selected is always constant regardless of the address signal. By providing the above-mentioned row address decoder, it is effective in stabilizing the access operation and guaranteeing high-speed access in the semiconductor memory device.

[Brief explanation of the drawing]

FIG. 1 is a longitudinal cross-sectional view showing an example of a structure in which word shunt lines are arranged in upper and lower layers in a DRAM according to an embodiment of the present invention, and FIG. 2 is a block diagram showing an example of the DRAM according to the present embodiment as a whole. 3 is a plan view showing the main part of the memory mat of the DRAM of this embodiment; FIG. 4 is a sectional view of the memory cell part of the main part of the memory mat shown in FIG. 3; and FIG. 5 is another embodiment of the present invention. FIG. 6 is a vertical cross-sectional view showing the main parts of a DRAM having a stacked storage capacitor element as an example; FIG. It is. 1... Memory cell formation region, 2... Shunt region,
3...P-type semiconductor substrate, 6...gate electrode, 8...
・Word line, 10,10'...Word shunt line, 1
4... Bit line, 20, 21. 22... Interlayer insulating film, 3°... Memory mat, 31... Memory cell, 3
3... Word decoder, 34... Word driver,
Qi...selection MISFET, Ci...storage capacitor element. Figure 1 Figure 3

Claims (1)

[Claims] 1. A multilayer wiring structure having a word line coupled to a selection terminal of a memory cell and a word shunt line having a lower resistance than the word line and electrically connected to the word line. A semiconductor memory device in which adjacent word shunt lines are vertically shifted and formed in separate layers. 2. In order to access the memory cell, a plurality of word shunt lines are simultaneously selected from among the word shunt lines formed in multiple layers, and the plurality of word shunt lines to be selected. 2. The semiconductor memory device according to claim 1, further comprising an address decoder provided with selection logic that makes the overall load always the same. 3. The word shunt lines are made up of two-layer wiring alternately formed in separate layers, and when the address decoder simultaneously selects an even number of word shunt lines from among the word shunt lines, the word shunt lines located in the upper layer 3. The semiconductor memory device according to claim 2, wherein the number of lines and the number of word shunt lines located in the lower layer are selected to be equal.