JPH02210985A - Drive circuit for matrix type liquid crystal display device - Google Patents

Abstract

PURPOSE:To prevent the deterioration in the picture quality of a moving picture due to the effect of after image by applying a voltage in response to an input picture signal to a signal line for a write period and applying a voltage fed to a picture element for a blanking period reaches a threshold level or below of the picture element to the signal line. CONSTITUTION:A picture signal for each horizontal scanning period started by a pulse being a horizontal synchronizing signal is sampled by a shift register 31 of an odd number field source driver 3 and a sample-and-hold circuit 32 and stored. The voltage in response to the amplitude of the stored picture signal is fed to a signal line 12 via a multiplexer 33 and an output buffer 34 for a 1st half write period of the horizontal scanning period. On the other hand, a voltage fed to the picture element and reaches a threshold level of the picture element or below is fed to the signal line 12 by an output buffer 44 of an even number field source driver 4 for the blanking period. Thus, the period storing simultaneously the voltages of the odd and even number of picture elements is reduced and in the case of displaying the moving picture, the deterioration in the picture quality is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a drive circuit for a matrix type liquid crystal display device.

(Prior Art) Matrix-type liquid crystal display devices are solidifying their position as display devices comparable to CRTs due to rapid technological advances in recent years. Matrix-type liquid crystal display devices have excellent features such as being thin and lightweight, and have low power consumption, so they are currently used in display parts of television receivers,
It is expected to have a wide range of uses, such as display devices for information devices such as personal computers.

FIG. 5 shows an example of a conventional matrix type liquid crystal display device. In the matrix type liquid crystal display device shown in FIG. 5, active elements for driving picture elements are T P T
(Thin F ■Transistor). The TFT liquid crystal panel 100 includes liquid crystal picture elements (hereinafter abbreviated as "picture elements") 103 arranged in a matrix of 1 row and m columns. In the vicinity of each picture element 103, T
FTs 104 are provided, and the drain electrodes of the TPTs 104 are connected to the electrodes of the picture elements 103. A common counter electrode 105 is arranged between the electrodes of all the picture elements 103.

A TFT single crystal panel has 100 scanning lines 101 arranged in parallel. The first scanning line 101 is connected to the gate electrode (opening/closing terminal) of the j-th TFT 104. m signal lines 10 perpendicular to the scanning line 101
2 are arranged in parallel. The source electrode (signal input terminal) of the TPTIO4 in the first column is connected to the first signal line 102.

The TFT liquid crystal panel 100 is driven by a drive circuit including a gate driver 200 and a source driver 300. The gate driver 200 and source driver 300 are T
They are connected to the scanning line 101 and signal line 102 of the FT panel 100, respectively. The image signal is source driver 30
It is input to 0. Control signals such as a scanning pulse input to the gate driver 200 and a sampling clock input to the source driver 300 are provided from a mount control circuit (not shown).

FIG. 6 shows part of the display timing within one field or one frame in the matrix type liquid crystal display device shown in FIG. The source driver 300 samples the serially inputted image signal in each horizontal scanning period started by a pulse of the horizontal synchronization signal. Voltage Vs(L 1) (1==1. 2.
=-, m) is j+1 100th horizontal scanning period (J
+I) is applied in parallel to the signal line 102 during H. On the other hand,
The gate driver 200 applies a pulse to the first scanning line during the horizontal scanning period (J+1)H (in FIG. 6,
gj indicates the voltage of the first scanning line 101).

As a result, T connected to the first scanning line 101
TR(J, 1> (1=1゜2,・
...+m) is turned on, and vs(J, 1) is generated at the drain electrode of TR(J, 1). Therefore, TR(J,
1) The voltage e applied to the picture element 103 connected to
(J, l) is the difference voltage between vslt t) and the voltage v0 applied to the counter electrode 105, that is, vs(j, i)
It is vo. The above operation will be referred to as "writing" below. Writing is performed sequentially in the first to mth horizontal scanning periods, thereby completing the display of one frame or one field.

Since the picture element 103 has capacitance, the written voltage is held for a certain period of time. In each field, a voltage of opposite polarity to the voltage applied to the signal line lO2 in the immediately previous field is used. That is, AC driving is performed in which one AC cycle is closed in two fields. The reason why AC driving is performed is to avoid deterioration of the picture element 103 due to application of a DC voltage to the picture element 103.

(Problems to be Solved by the Invention) Display methods using drive circuits for matrix-type liquid crystal display devices include interlaced scanning (interlaced scanning) and non-interlaced scanning, as in the case of CRT.

In non-interlaced scanning, all scanning lines 101 are sequentially scanned in each frame. As shown in FIG. 7, in non-interlaced scanning, if a certain picture element 103 is focused on, writing is performed on that picture element 103 in each frame.

On the other hand, in interlaced scanning, one frame is divided into an odd field corresponding to an odd numbered scanning line 101 and an even number field corresponding to an even numbered scanning line 101, and scanning of an odd field and scanning of an even field are performed. are performed alternately. The NTSC system, which is the television system adopted in Japan, uses ink-lace scanning.

As shown in FIG. 8, in interlaced scanning, the voltage e(2
-1, I) is retained during the scan of the immediately following even field. Similarly, the voltage e (2k) written to the picture elements of even rows in even fields.

(2) is held during the scan of the immediately following odd field. Therefore, display by writing in the odd field and display by writing in the even field are performed during one field period tv (in the case of the NTSC system, tv=16.7 m5). This causes a problem in that the image quality deteriorates when displaying moving images. That is, when a still image is displayed as a straight line as shown in FIG. Figure (b
), a deviation of one dot or more occurs between the display on the odd-numbered scanning line and the display on the even-numbered scanning line,
Distortion occurs in the image. As mentioned above, the TFT liquid crystal panel 100 has the function of holding the write voltage for a long time, so it can effectively improve the flicker that is a problem in CRTs, but this function causes strong afterimages. This actually has a negative effect on the video display.

Non-increment scanning does not cause such a problem. However, when displaying an image signal compatible with interlaced scanning such as the NTSC system, the matrix type liquid crystal display device needs to be equipped with a frame memory or field memory for storing sampled image signals. Furthermore, a high-speed A/D converter and a circuit for three-dimensional signal processing are required. In addition, since it is necessary to drive twice as many scanning lines within one field period compared to interlaced scanning, it is possible to speed up the operation of the drive circuit including the source driver and gate driver, and to increase the speed of the operation of the liquid crystal panel. There is also a need for faster operation. Therefore, even if non-interlaced scanning were possible with existing technology, the drive circuitry and display would be significantly more expensive.

The present invention was made in view of the current situation, and
The purpose is to provide a drive circuit for a matrix type liquid crystal display device that can improve image quality deterioration of moving images due to the influence of afterimages even when performing interlaced scanning.

(Means for Solving the Problems) A drive circuit for a matrix type liquid crystal display device of the present invention includes liquid crystal picture elements arranged in a matrix, switching elements connected to each liquid crystal picture element, and switching elements arranged in one direction. Driving a matrix type liquid crystal display device including a liquid crystal panel having a scanning line connected to an opening/closing terminal of an element group and a signal line connected to a signal input terminal of a switching element group arranged in a direction intersecting the scanning line. A circuit that selectively drives any scanning line in a group of scanning lines corresponding to a field being scanned during a write period provided within one horizontal scanning period, and within the horizontal scanning period. The writing period is an erasing period provided in a time-division manner, and includes an opening/closing terminal driving means for selectively driving at least one scanning line in a scanning line group that does not correspond to the field being scanned; During the write period, a voltage according to the input image signal is applied to the signal line, and during the erase period, a voltage for applying a voltage below the threshold of the liquid crystal picture element to the liquid crystal picture element is applied to the signal line. The above object is achieved by comprising means for driving a signal input terminal for applying a signal.

(Example) The invention will now be described with reference to examples.

FIG. 1 shows a block diagram of a matrix type liquid crystal display device equipped with an embodiment of the present invention. TPT liquid crystal panel 1 is the fifth
The structure is similar to the conventional one shown in the figure. In addition, in addition to the TPT mentioned above, MIM and MOS are used for switching picture elements.
) Switching elements such as transistors are used. The drive circuit 6 includes a gate driver 2, two source drivers 3
．． 4 and a control circuit 5 for controlling them. Control circuit 5 generates a control signal based on a synchronization signal input from the outside, and supplies this to gate driver 2 and source driver 3.4. The control signal input to the gate driver 2 includes a scanning pulse, and the control signal input to the source drivers 3 and 4 includes a sampling pulse. The gate driver 2 has a shift register 21, a level shifter 22, and an output buffer 23. The output buffer 23 is connected to n scanning lines 11 of the TFT liquid crystal panel 1.

The source driver 3 includes a shift register 31, a sample
It has a hold circuit 32, a multiplexer 33, and an output buffer 34. The output buffer 34 is connected to m signal lines 12 of the TPT liquid crystal panel 1. Like the source driver 3, the source driver 4 includes a shift register 41, a sample/hold circuit 42, and a multiplexer 4.
3 and an output buffer 44. Output buffer 4
4 is also connected to the signal line 12 of the TFT liquid crystal panel 1. Image signals are input to both source drivers 3.4.

The drive circuit 6 drives the TPT liquid crystal panel 1 using an interlaced scanning method that alternately scans odd fields and scans even fields. However, unlike the conventional technique, as shown in FIG. 2, a writing period and an erasing period are provided in a time-sharing manner within each horizontal scanning period. In the following, the drive circuit 6
Explain the operation.

FIG. 3 shows part of the display timing within an odd field in the matrix type liquid crystal display device of FIG. 1. In FIG. In each horizontal scanning period started by a pulse of the horizontal synchronizing signal, a serially inputted image signal is sampled and held by the shift register 31 and sample-and-hold circuit 32 of the source driver 3 for odd fields. Voltage vs (2k 1. 1) (1
=1°2,..., rn) is transmitted to the signal line 1 via the multiplexer 33 and the output buffer 34 during the first half writing period in the k+1st horizontal scanning period (k+1)H.
2 in parallel. On the other hand, the gate driver 2 applies a pulse to the 11th scanning line 11 in 2 during the writing period within the horizontal scanning period (k+1)H (in FIG. 3,
g2 indicates the voltage of the second scanning line 11).

As a result, TR(2-1,1) (1=1.2.
=, m) is turned on, and vs (2k -1, i) is generated at the drain electrode of TR (2 to -1,1). Therefore, the voltage e (-1 to 2, i) applied to the picture element connected to TR (2k -1, 1) is Vs (-1 to 2
, D and the voltage v0 applied to the counter electrode 15, that is, v, (2k 1. 1) - va. Writing is performed in this manner.

In the erase period in the latter half of the horizontal scanning period (k+1)H,
The gate driver 2 applies a pulse to the second scanning line 11 adjacent to the selected scanning line 11 during the writing period within the same horizontal scanning period.

During the erasing period, the output buffer 44 of the source driver 4 for even fields applies a voltage V to the picture element.
A voltage is applied to the signal line 12 such that , is less than the threshold of the picture element. As a result, the picture element on the second scanning line 11 becomes erased.

This operation will be referred to as "erasing" below. The multiplexer 33.43 selectively sends the voltage output from the sample-and-hold circuit 32.42 and the voltage for setting the picture element to the erased state to the output buffer 34.44 according to the control signal from the control circuit 5. They are set up for the benefit of each. Control circuit 5 to multiplexer 3
3 and 43 are supplied with a switching timing pulse (see FIG. 3) whose level changes at the start and end of each write period. During the erasing period, the signal line 12
The voltage applied to the pixel to erase the picture element is applied to the multiplexers 33 and 43 from the control circuit 5 or from outside the drive circuit 6.

The time allocation to the writing period and the erasing period within one horizontal scanning period and the order thereof can be appropriately determined by taking into consideration the characteristics of the picture elements and the like.

In scanning an even field, the role of the source driver 3 for odd fields and the role of the source driver 4 for even fields are exchanged. Also, gate driver 2
drives the even-numbered scanning lines 11 during the writing period and the odd-numbered scanning lines 11 during the erasing period.

FIG. 4 shows the voltages applied to picture elements over multiple fields. Writing is performed on picture elements in odd-numbered rows during the scanning period of odd-numbered fields, and erasing is performed during the scanning period of even-numbered fields. The opposite is true for picture elements in even rows. In this way, according to the drive circuit 6 of this embodiment, the period during which the picture elements in the odd rows and the picture elements in the even rows simultaneously hold the written voltages is significantly shortened. Therefore, deterioration in image quality when displaying moving images is greatly improved.

In order to facilitate understanding of the present invention, an embodiment including two source drivers 3 and 4 has been described, but the configuration of the drive circuit of the present invention is not limited to this. 1st
FIG. 0 shows a block diagram of a matrix type liquid crystal display device equipped with a second embodiment of the present invention. The drive circuit 8 shown in FIG. 10 includes one source driver 7. The drive circuit 8 shown in FIG. Like the source driver 3 or 4 in FIG. 1, the source driver 7 includes a shift register 71, a sample/hold circuit 72,
It has a multiplexer 73 and an output buffer 74. The operation of source driver 7 is similar to that of source driver 3 or 4. However, the source driver 7
Unlike the source driver 3 or 4 shown in the figure, a voltage corresponding to the image signal is applied to the signal line 12 during the writing period in both odd and even fields, and picture elements are erased during the erasing period. The voltage for setting the signal N
512.

The scope of application of the present invention is not limited to drive circuits that perform 2:1 interlaced scanning such as the NTSC system.

(Effects of the Invention) According to the present invention, there is provided a drive circuit for a matrix type liquid crystal display device that can significantly improve image quality deterioration when displaying moving images despite performing interlaced scanning. provided.

4 No. 1 FIG. 1 is a block diagram showing a schematic configuration of a matrix type liquid crystal display device equipped with an embodiment of the present invention, and FIG. FIG. 3 is a timing chart showing part of the display timing within one odd field in the matrix type liquid crystal display device of FIG. 4 is a diagram showing the voltage applied to the picture element in the matrix type liquid crystal display device of FIG. 1 over multiple fields, and FIG. 5 is a diagram showing an example of a conventional matrix type liquid crystal display device. The figure is a timing chart showing part of the display timing within one field in the matrix type liquid crystal display device of Figure 5, and Figure 7 is the voltage applied to the picture element in the matrix type liquid crystal display device of Figure 5. Figure 8 shows the voltage applied to the picture element in the matrix type liquid crystal display device of Figure 5 over multiple fields in the case of interlaced scanning. The figures shown above, FIGS. 9(b) and 9(b) are diagrams showing an example of displaying a still image and a displaying example of a moving image, respectively, in a conventional matrix type liquid crystal display device, and FIG. FIG. 1 is a block diagram of a matrix type liquid crystal display device including an embodiment of the present invention.

l...TPT liquid crystal panel, 2...gate driver (
opening/closing terminal driving means), 3.4.7... source driver (signal input terminal driving means), 5... control circuit, 6.8... drive circuit, 11... scanning line, 12...
・Signal 11A, 2x...Shift register, 22...
Level shifter, 23... Output buffer, 31.4L
71...Shift register, 32.42.72...
Sample and hold circuit, 33.43.73... Multiplexer, 34.44.74... Output buffer, 1
03...Liquid crystal picture element, 104...TFT (switching element).

that's all

Claims (1)

[Claims] 1. Liquid crystal picture elements arranged in a matrix, switching elements connected to each liquid crystal picture element, scanning lines connected to opening/closing terminals of a group of switching elements arranged in one direction; A drive circuit for a matrix type liquid crystal display device including a liquid crystal panel having signal lines connected to signal input terminals of switching element groups arranged in a direction intersecting the scanning line, the drive circuit being provided within one horizontal scanning period. During the writing period, one of the scanning lines in the scanning line group corresponding to the field being scanned is selectively driven, and within the horizontal scanning period, the writing period is time-divided into an erasing period. , opening/closing terminal driving means for selectively driving at least one scanning line in the scanning line group that does not correspond to the field being scanned;
During the writing period, a voltage according to the input image signal is applied to the signal line, and during the erasing period, a voltage for applying a voltage equal to or lower than the threshold of the liquid crystal picture element to the liquid crystal picture element is applied to the signal line. A drive circuit for a matrix type liquid crystal display device, which includes a signal input terminal drive means for applying a signal to the drive circuit.