JPH02214115A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH02214115A
JPH02214115A JP3374589A JP3374589A JPH02214115A JP H02214115 A JPH02214115 A JP H02214115A JP 3374589 A JP3374589 A JP 3374589A JP 3374589 A JP3374589 A JP 3374589A JP H02214115 A JPH02214115 A JP H02214115A
Authority
JP
Japan
Prior art keywords
contact
polysilicon layer
layer
formation region
amorphous silicon
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3374589A
Other languages
Japanese (ja)
Inventor
Isao Murakami
村上 勇雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP3374589A priority Critical patent/JPH02214115A/en
Publication of JPH02214115A publication Critical patent/JPH02214115A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To eliminate deterioration of contact characteristic by a method wherein an amorphous silicon layer is formed, by a heat treatment, on another polysilicon layer united to a polysilicon layer and a contact between the polysilicon layer and a silicon single-crystal substrate is formed in a contact- formation region. CONSTITUTION:An amorphous silicon layer 4 is applied to and formed on an insulating film 2 and a contact-formation region 3 by a CVD operation; in addition, a polysilicon layer 5 is applied to and formed on the amorphous silicon layer 4 by the CVD operation. After that, a heat treatment is executed; the amorphous silicon layer 4 is transformed into a polysilicon layer; a polysilicon layer 6 united to the polysilicon layer 6 is formed; a contact between the layer and a silicon single crystal of a silicon single-crystal substrate 1 is formed in the contact-formation region 3. Thereby, a P-N junction reverse-current value in the contact-formation region 3, i.e., a leakage current value, can be suppressed by one digit or above as compared with ordinary cases.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、シリコン基板とポリシリコン層との良好なコ
ンタクトを形成する半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device that forms good contact between a silicon substrate and a polysilicon layer.

(従来の技術) 第2図は、従来の半導体装置の製造方法を示す工程断面
図である。
(Prior Art) FIG. 2 is a process cross-sectional view showing a conventional method for manufacturing a semiconductor device.

従来の製造方法は、まず、第2図(a)のように、シリ
コン単結晶基板21上に絶縁膜22を形成させ、それを
選択的にフォトエツチングして開口することによりコン
タクト形成領域23を形成し、その後、第2図(b)の
ように、CVDにより全面にポリシリコン層24を被着
形成し、さらに熱処理してシリコン単結晶基板21と上
記ポリシリコン層24とのコンタクトを形成していた。
In the conventional manufacturing method, first, as shown in FIG. 2(a), an insulating film 22 is formed on a silicon single crystal substrate 21, and a contact forming region 23 is formed by selectively photoetching the insulating film 22 to open it. Thereafter, as shown in FIG. 2(b), a polysilicon layer 24 is deposited on the entire surface by CVD, and a contact between the silicon single crystal substrate 21 and the polysilicon layer 24 is formed by further heat treatment. was.

(発明が解決しようとする課題) しかしながら、上述の従来の製造方法では、第2図(c
)に示す領域25に結晶欠陥を発生し、コンタクト特性
が劣化する欠点を有していた。
(Problems to be Solved by the Invention) However, in the above-mentioned conventional manufacturing method, as shown in FIG.
), crystal defects were generated in the region 25 shown in ), resulting in deterioration of contact characteristics.

これは、熱処理したことによりポリシリコン層24内の
結晶構造が破壊され、シリコン単結晶内、特にコンタク
ト形成領域23に歪を発生することに起因するものであ
る。
This is because the crystal structure within the polysilicon layer 24 is destroyed by the heat treatment, causing strain within the silicon single crystal, particularly in the contact formation region 23.

本発明は、上述のようなコンタクト特性の劣化を排除す
る半導体装置の製造方法の提供を目的とする。
An object of the present invention is to provide a method for manufacturing a semiconductor device that eliminates the deterioration of contact characteristics as described above.

(課題を解決するための手段) 本発明は上記の目的を、半導体装置の製造において、シ
リコン単結晶基板の表面に絶縁膜を形成し、これを選択
エツチングすることにより開口部を形成してコンタクト
形成領域とし、その後、上記絶縁膜を含む上面全体に順
次にアモルファスシリコン層およびポリシリコン層を被
着形成させ、これに熱処理を施すことによって上記アモ
ルファスシリコン層を上記ポリシリコン層と一体の他の
ポリシリコン層に形成させ、その形成されたポリシリコ
ン層と上記シリコン単結晶基板とのコンタクトを上記コ
ンタクト形成領域に形成することによって達成する。
(Means for Solving the Problems) The present invention achieves the above-mentioned object in manufacturing a semiconductor device by forming an insulating film on the surface of a silicon single crystal substrate and selectively etching the insulating film to form an opening and making contact. After that, an amorphous silicon layer and a polysilicon layer are successively deposited on the entire upper surface including the insulating film, and heat treatment is performed on the amorphous silicon layer to form another layer integral with the polysilicon layer. This is achieved by forming a polysilicon layer and forming a contact between the formed polysilicon layer and the silicon single crystal substrate in the contact formation region.

(作 用) 本発明によれば、熱処理の際にアモルファスシリコン層
が下地の単結晶の結晶軸を保存しなから固相エピタキシ
ャル成長を始め、ポリシリコン層内の結晶構造の破壊に
対しては緩衝層として機能してポリシリコン化を開始し
、最終的には単一のポリシリコン層に形成される。した
がって、前述したようなコンタクト欠陥が排除され、特
性の安定した半導体装置が製造される。
(Function) According to the present invention, during heat treatment, the amorphous silicon layer starts solid phase epitaxial growth without preserving the crystal axis of the underlying single crystal, and provides a buffer against destruction of the crystal structure within the polysilicon layer. It acts as a layer to initiate polysiliconization and ultimately forms a single polysilicon layer. Therefore, contact defects as described above are eliminated, and a semiconductor device with stable characteristics is manufactured.

(実施例) 以下1本発明の一実施例を第1図の製造工程断面図を用
いて説明する。
(Example) An example of the present invention will be described below using the manufacturing process cross-sectional diagram of FIG. 1.

本発明の製造方法は、まず、第1図(a)のように、シ
リコン単結晶基板の表面に絶縁膜2を形成し、それを選
択的にフォトエツチングすることにより開口部を形成さ
せ、これをコンタクト形成領域3とする。
In the manufacturing method of the present invention, first, as shown in FIG. 1(a), an insulating film 2 is formed on the surface of a silicon single crystal substrate, and an opening is formed by selectively photoetching the insulating film 2. is defined as a contact formation region 3.

次に、同図(b)のように、絶縁膜2およびコンタクト
形成領域3上に550℃の温度でCVDによってアモル
ファスシリコン層4を被着形成させる。
Next, as shown in FIG. 2B, an amorphous silicon layer 4 is deposited on the insulating film 2 and the contact formation region 3 by CVD at a temperature of 550°C.

さらに、同図(0)のように、CVDによって温度62
0℃で上記アモルファスシリコン層4上にポリシリコン
層5を被着形成させ、その後、900℃の熱処理を施す
ことにより上記アモルファスシリコン層4をポリシリコ
ン層化し、上記ポリシリコン層5と一体なポリシリコン
層6に形成し、これとシリコン単結晶基板1のシリコン
単結晶のコンタクトをコンタクト形成領域3において形
成させる。
Furthermore, as shown in the same figure (0), temperature 62
A polysilicon layer 5 is formed on the amorphous silicon layer 4 at 0° C., and then heat treatment is performed at 900° C. to convert the amorphous silicon layer 4 into a polysilicon layer. A contact between the silicon layer 6 and the silicon single crystal of the silicon single crystal substrate 1 is formed in the contact formation region 3 .

本発明は、以上のようにコンタクトを形成するが、コン
タクト形成領域におけるPN接合逆方向電流値、すなわ
ちリーク電流値は従来方法によるよりも1桁以上も抑制
することができた。
Although the present invention forms a contact as described above, the PN junction reverse current value, that is, the leakage current value in the contact forming region can be suppressed by more than one order of magnitude compared to the conventional method.

(発明の効果) 以上から明らかなように、本発明によれば、結晶欠陥の
発生しない、シリコン単結晶とポリシリコン層とのコン
タクトが容易に形成でき、したがって、コンタクト特性
の良好な半導体装置が歩留りよく製造可能な効果が発揮
できる。
(Effects of the Invention) As is clear from the above, according to the present invention, a contact between a silicon single crystal and a polysilicon layer without crystal defects can be easily formed, and therefore a semiconductor device with good contact characteristics can be obtained. The effect of manufacturing with high yield can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す工程断面図、第2図は
従来の製造方法を説明する工程断面図である。 1・・・シリコン単結晶基板、 2・・・絶縁膜。 3・・・コンタクト形成領域、 4・・・アモルファス
シリコン層。 層・ 5.6・・・ポリシリコン 特許出願人 松下電子工業株式会社 第 図 第 図
FIG. 1 is a process sectional view showing an embodiment of the present invention, and FIG. 2 is a process sectional view explaining a conventional manufacturing method. 1...Silicon single crystal substrate, 2...Insulating film. 3... Contact formation region, 4... Amorphous silicon layer. Layer 5.6...Polysilicon patent applicant Matsushita Electronics Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の製造において、シリコン単結晶基板の表面
に絶縁膜を形成し、これを選択エッチングすることによ
り開口部を形成してコンタクト形成領域とし、その後、
上記絶縁膜を含む上面全体に順次にアモルファスシリコ
ン層およびポリシリコン層を被着形成させ、これに熱処
理を施すことによって上記アモルファスシリコン層を上
記ポリシリコン層と一体の他のポリシリコン層に形成さ
せ、その形成されたポリシリコン層と上記シリコン単結
晶基板とのコンタクトを上記コンタクト形成領域に形成
することを特徴とする半導体装置の製造方法。
In the manufacture of semiconductor devices, an insulating film is formed on the surface of a silicon single crystal substrate, and an opening is formed by selectively etching it to form a contact formation region.
An amorphous silicon layer and a polysilicon layer are sequentially deposited on the entire upper surface including the insulating film, and heat treatment is performed on the amorphous silicon layer to form another polysilicon layer integral with the polysilicon layer. A method of manufacturing a semiconductor device, comprising forming a contact between the formed polysilicon layer and the silicon single crystal substrate in the contact formation region.
JP3374589A 1989-02-15 1989-02-15 Manufacture of semiconductor device Pending JPH02214115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3374589A JPH02214115A (en) 1989-02-15 1989-02-15 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3374589A JPH02214115A (en) 1989-02-15 1989-02-15 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH02214115A true JPH02214115A (en) 1990-08-27

Family

ID=12394953

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3374589A Pending JPH02214115A (en) 1989-02-15 1989-02-15 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH02214115A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118726948A (en) * 2024-06-07 2024-10-01 环晟光伏(江苏)有限公司 Graphite boat assembly and solar cell for PECVD coating

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118726948A (en) * 2024-06-07 2024-10-01 环晟光伏(江苏)有限公司 Graphite boat assembly and solar cell for PECVD coating

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