JPH02216836A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent fuzz generation of a gate electrode at the bottom of the upper part in the case of deposition of a metallic film and to suppress rush-down of metallic particles at the eaves part of the lower part so as to enable accurate dimension control of the gate length by forming an eaves in each of the upper and lower parts of the inner face of the opening of a photoresist which has a hexagonal inversed pattern opening. CONSTITUTION:A thin first insulating film 15 to become a base layer is overlaid on the whole faces of an N layer 12 and an N<+> layer 13 which are formed on the main face of an semiinsulating GaAs substrate 11, and after application of first photoresist 16 on this insulating film 15 a reversely tapered pattern opening 17 is formed by patterning according to the formative position of a gate electrode, and the inside of this opening is filled up with a second insulating film so as to flatten it, whereby an inversed pattern 18 which is trapezoid in cross section is formed. Thereafter, a second photoresist 20, a metallic film 19, and a remaining resist are removed so as to form an inversed pattern 22 which is hexagonal in cross section. Next, by removing this pattern 22 by etching, eaves 23a and 23b are formed respectively at the upper and lower parts of the inner face of the opening. And by these eaves fuzz generation at the gate electrode 25 and rush-down of metallic particles are suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a field effect transistor constructed using a compound semiconductor substrate 1, such as a semi-insulating GaAs substrate. (FE
T) relates to a method for forming a gate electrode with high reliability and excellent dimensional accuracy.

(Prior art) GaAs crystal, which is the substrate material for this type of GaAs IG, is known to be significantly inferior in acid resistance when compared to Si crystal.
In manufacturing FETs, the lift-off method is generally widely used to form gate electrodes.

In this lift-off method, after forming a photoresist pattern using photolithography, a vapor-deposited metal film is deposited, and then an organic solvent is used to remove unnecessary parts of the metal film along with the photoresist pattern. This is an extremely simple technical means that allows the formation of any metal film, such as a gate electrode, in a required area by removing the photoresist pattern. Since it is used as a mask material, the metal film to be formed, that is, in the case of a GaAs FET, specifications such as the cross-sectional shape and dimensional accuracy of the gate electrode strongly depend on the profile of the patterned photoresist. It was something that would become.

Next, we will discuss a conventional example of G
The main manufacturing steps for forming a gate electrode in an aAs FET will be described with reference to FIGS. 2(a) to 2(d).

That is, in this conventional method, first, an N layer 2 and an N1 layer 3 are formed on the main surface of a semi-insulating GaAs substrate 1 by ion implantation, and this N layer 2 and an N1 layer 3 are formed by ion implantation.
An ohmic electrode 4 is selectively formed on the 0 layer 3 (
As shown in FIG. 2(a)), by photolithography, a photoresist 5 is coated, and a pattern opening corresponding to the gate electrode formation position becomes a dummy pattern (inverted pattern) with a reverse tapered shape. The portion 6 is selectively formed (FIG. 6(b)).

Next, these N layer 2 and N1 layer 3. and ohmic electric Vj! A metal film 7 is formed on the entire surface of 4 by metal vapor deposition means.
At this time, the patterned photoresist 5 acts as a mask, and the pattern opening also forms a predetermined area on the N'' layer 3 in which the dummy pattern (inverted pattern) is formed. Then, using an organic solvent, the unnecessary part of the metal wA7a is removed together with the photoresist 5 by the lift-off method described above. As a result ((d) in the same figure), the GaAs
This forms the gate electrode of the FET.

[Problem to be solved by the invention]

In the normal lift-off method according to the conventional example described above, in order to suppress the generation of fluff during the formation of the gate electrode 7, a photo film is used as shown in FIG. 2(b). Pattern openings in resist 5 6. In other words, the profile of the inverted pattern serving as the dummy pattern is finished in an inverted tapered shape.

However, on the other hand, when adopting such a method for forming a gate electrode of a GaAs FET, the cross-sectional shape of the gate electrode 7 to be formed depends on the maximum incident angle of metal particles during vapor deposition and the photoresist pattern. Because it is determined by the overhang angle of the opening 6,
This causes the following problems.

That is, first of all, there is a substantial increase in the gate length due to the penetration of metal particles during metal vapor deposition for forming a gate electrode.
This is a fatal flaw in improving the performance of AsFET. Second, when the gate electrode has a multilayer electrode structure, the metal particles of the top layer electrode run down onto the GaAs surface (actually, the N layer);
This is a serious drawback related to the basis of its (g-sensitivity), such as a drop in gate breakdown voltage during operation of the s FET.

This invention was made to solve these conventional problems, and its purpose is to accurately and reliably control the dimensional accuracy of the gate length when forming the gate electrode. Reliability can be ensured. An object of the present invention is to provide a method for manufacturing a semiconductor device of this type, in particular a method for forming a gate electrode.

[Means for Solving the Problems] In order to achieve the above object, a method for manufacturing a semiconductor device according to the present invention includes selectively forming an active layer and an ohmic electrode on the main surface of a compound semiconductor substrate. and applying a first insulating film on the first insulating film, and forming an opening in a reverse tapered pattern at a predetermined position. filling the inside of the pattern opening with a second insulating film by low-temperature CVD or the like, and flattening this to form a dummy pattern having a trapezoidal cross section; and filling the entire surface of these with a metal thin film. A second photoresist is applied on this metal thin film, and a second photoresist is applied on this metal thin film.
a step of patterning the photoresist so as to selectively leave it only on the dummy pattern having a trapezoidal cross-section; and a step of patterning the patterned second photoresist, using the metal thin film as a mask, to give a predetermined irradiation angle. A step of selectively removing and forming the lower hem of the dummy pattern having a trapezoidal cross section diagonally inward using a strong charged particle beam to form a dummy pattern having a hexagonal cross section, and then removing the mask; A third photoresist is applied to the entire upper surface including the ohmic electrode and the dummy pattern with a hexagonal cross section, and the dummy pattern is exposed by etching back, and the dummy pattern with a hexagonal cross section is removed. forming an inverted pattern opening with the same cross section to selectively expose a predetermined portion of the operating layer; depositing a vapor-deposited metal film on the entire surface of the opening; and lifting it off to expose the exposed operating layer. The method is characterized in that it includes a step of forming a gate electrode on the layer.

[For production]

That is, in the method of the present invention, an inverted tapered pattern opening is formed at a predetermined position on the main surface of a compound semiconductor substrate, and the inside of this pattern opening is filled with an insulating film and flattened to form a trapezoidal cross section. After forming a dummy pattern with a trapezoidal cross section, the lower half of the dummy pattern is selected diagonally inward using a highly directional charged particle beam at a predetermined irradiation angle using a photoresist mask. Then, a photoresist is applied including the dummy pattern with a hexagonal cross section and etched back to expose the dummy pattern. The dummy pattern is removed to form a hexagonal inverted pattern opening in the photoresist, and this inverted pattern opening is used as a photoresist mask for metal film evaporation and lift-off. Since the gate electrode is formed by forming a gate electrode, the photoresist which has a hexagonal inverted pattern opening with an inverted opening cross section serves as a mask. The eaves are formed,
When depositing a metal film, the upper eave prevents fuzz from forming on the gate electrode, and the lower eave prevents avalanche of metal particles during vapor deposition, allowing accurate dimensions of 5 gate lengths. It is possible to control it.

〔Example〕

Hereinafter, one embodiment of the method for manufacturing a semiconductor device according to the present invention will be described in detail with reference to FIG.

FIGS. 1(a) to 1) are cross-sectional views sequentially showing the main steps of a method for forming a gate electrode in a GaAs FET to which the method of this embodiment is applied.

That is, in this embodiment method, first, on the main surface of a semi-insulating GaAs substrate (FIG. 1(a) > 11), 8 layers 12 and an N+ layer 13, which will become active layers, are formed by ion implantation. (Figure (b))
), selectively form a microelectrode 14 on the top layer 3 of this N'' layer 1, and also
A thin first insulating film 15 serving as an underlayer is deposited on the entire surface of the substrate 3 (FIG. 3(C)).

Next, a first photoresist 16 is applied onto the first insulating film 15 by photolithography, and an inversely tapered pattern opening 17 is patterned corresponding to a predetermined gate electrode formation position. Let it form (see figure (d)
)), and the inside of this pattern opening 17, for example,
Low temperature CVD (Chemical Vapor Depos)
tion) method, etc., to fill with a second insulating film,
By flattening this, a dummy pattern (inverted pattern) 18 having a trapezoidal cross section is formed (FIG. 2(e)), and subsequently, these first photoresists 16. and a metal thin layer 11 on the entire surface of the dummy pattern 18.
ij 19 is deposited, and a second photoresist 20 is applied on this metal thin film 19 by the same photolithography technique (FIG. 1(f)).
The photoresist 20 is patterned and formed so as to selectively remain only on the dummy pattern (inverted pattern) 18 having a trapezoidal cross section, and the metal fit film!
9 is also selectively removed by etching using the patterned second photoresist 20 as a mask (FIG. 9(g)).

In this case, the role of the metal thin film 19 is to prevent the first photoresist 16 and the second photoresist 20 from mixing with each other.

Next, the bottom half of the dummy pattern (reversed pattern) +8 having a trapezoidal cross section, which is an important point in the method of this embodiment, is selectively removed diagonally inward. Form into the desired hexagonal cross section. For this shaping, a highly directional charged particle beam having a predetermined irradiation angle is used to cover the patterned second photoresist 20. This is carried out using the metal thin film I9 below it as a mask and using the collision energy of the charged particles.

In other words, in the case of this embodiment method, specifically, the dummy pattern (inverted pattern) having the trapezoidal cross section in
As the molding means of No. 18, for example.

Using ion milling using argon (^"0) ions, the semi-insulating GaAs substrate 11 is irradiated with the ion beam 21 at a constant irradiation angle in accordance with the shaping angle, as described above. This is done by using a two-layer film as a mask, consisting of the second photoresist 20 patterned and formed and the metal thin film 19 underneath.
and the lower first insulator 11i15 are completely removed, leaving only a small portion of the photoresist 16 in the upper half of each corresponding to the area outside the irradiation angle of the ion beam 21 on the dummy pattern 18. ((h) in the same figure),
After that, the second photoresist 1 used for these masks
-20. The remaining photoresist 16 portions, such as the metal thin film 19, are removed respectively, and a dummy pattern (reversed pattern) is formed into a hexagonal cross-section as expected.
22 can be formed ((i) in the same figure).

Subsequently, the ohmic electrode 14. and a dummy pattern (reversed pattern) 22 each having a hexagonal cross section, a third photoresist 23 is applied using the atmosphere plate making technique as described above, and this is etched back. Then, using a hydrofluoric acid etching solution, this dummy pattern (reversed pattern) 22 with a hexagonal cross section and the first pattern below it are removed using a hydrofluoric acid etching solution. By etching and removing the insulating film 15, an inverted pattern opening 24 of the dummy pattern 22 having a hexagonal cross section is formed, and a predetermined portion of the N+ layer 13 is selectively exposed (as shown in the figure). (k)) Furthermore, by depositing a metal film 25a on these entire surfaces by metal vapor deposition means, the inside of the inverted pattern opening 24 is formed.

In other words, the intended gate electrode 25 can be formed on the N'' layer 13 exposed through the opening of the inverted pattern opening 24 of the dummy pattern 22 having a hexagonal cross section ((1) in the figure), and then , using an organic solvent, remove the unnecessary portion of the metal film 25a together with the third photoresist 23,
Even with a saw, it is removed by the above-mentioned foot-off method ((II+) in the same figure), and in this way, the gate electrode of the GaAs FET can be formed as expected.

In the step (k), in order to simplify the explanation, explanations about so-called adjusting the drain current to a desired value and forming the groove structure are omitted.

Therefore, in the method of the embodiment described above, the third pattern obtained by etching and removing the dummy pattern 22 having a hexagonal cross section to form the inverted pattern opening 24
an opening in the photoresist 23.

In other words, the cross section of the opening that serves as a mask for forming the intended gate electrode 25 has an inverted hexagonal shape, and the eaves 23a, J3 and 23b is formed, and when the metal WA 25a is deposited for forming the gate electrode 25, the upper eave portion 23a can prevent the formation of fuzz on the gate electrode 25, as in the case of the conventional method. Depending on the lower eaves portion 23b, it is possible to suppress the avalanche of metal particles, which could not be achieved with the conventional method, and to achieve accurate dimensional control of the gate length.

In the above embodiment method, a field effect transistor using a semi-insulating GaAs substrate was described, but it can also be applied to a field-effect transistor using other compound semiconductor substrates 1, for example, a semi-insulating 1nP substrate. , similar actions and effects can be obtained.

〔Effect of the invention〕

As detailed above, according to the method of the present invention, an inverted tapered pattern opening is formed at a predetermined position on the main surface of a compound semiconductor substrate, and the inside of this pattern opening is covered with an insulating film. After embedding and flattening to form a dummy pattern with a trapezoidal cross section, the dummy pattern with a trapezoidal cross section is exposed underneath using a photoresist mask with a highly directional charged particle beam given a predetermined irradiation angle. The half hem part is selectively removed diagonally inward to form a dummy pattern with a hexagonal cross section, and then photoresist is applied including the dummy pattern with a hexagonal cross section and etched back to expose the dummy pattern. Then, this dummy pattern with a hexagonal cross section is removed to form an inverted hexagonal pattern opening in the photoresist, and the photoresist with the inverted pattern opening is masked. Used for vapor deposition of metal films.

The photoresist, which has a hexagonal inverted pattern opening with an inverted opening cross section, is used as a mask during metal vapor deposition to form a gate electrode as expected.
The upper part of the inner surface of the opening.

An eaves portion is formed on each of the upper and lower portions, and during vapor deposition of the metal film, depending on the bottom portion of the upper portion, generation of fluff on the gate electrode to be formed is well prevented.
Depending on the lower eaves, the avalanche of metal particles can be effectively suppressed in hot and humid conditions, allowing accurate dimensional control of the gate length, resulting in improved dimensional accuracy. It has excellent features such as making it possible to miniaturize the gate length even more than that, making it possible to achieve high-density integration, and at the same time, greatly improving the reliability of the device.

[Brief explanation of the drawing]

1(a) to 1(m) are cross-sectional views sequentially schematically showing the main steps of a method for forming a gate electrode in a GaAs FET to which an embodiment of the method of the present invention is applied, and FIG. 2(a) to 2(d) are cross-sectional views sequentially schematically illustrating the main steps of a method for forming a gate electrode in a GaAs FET according to a conventional example of the company. 11... Semi-insulating GaAs substrate, 12... N layer, 13... N3 layer, 14... Ohmic electrode,
15...first insulating film, 16...first photoresist, 17...pattern opening, ]8...
Dummy pattern with trapezoidal cross section, 19...Metal thin film, 20...Second photoresist, 2!・・・・・・
Argon (Ar") ion beam, 22...Dummy pattern with a hexagonal cross section, 23...Third photoresist, 23a, 23b...Third photoresist upper and lower portions of the inner surface of the opening Bottom, 24... Inverted pattern opening with hexagonal cross section, 25a... Metal film, 25... Gate electrode. 7f Tresist 17, No Tashi PF'1t1579 ball i) Arrangement I Niro〈Σ(2 Damino J turn figure (Iku 3) 1 den ~

Claims (1)

[Claims] A step of selectively forming an active layer and an ohmic electrode on the main surface of the compound semiconductor substrate, and depositing a first insulating film on the entire surface thereof; and a step of depositing a first insulating film on the first insulating film. A process of coating a photoresist and forming an inversely tapered pattern opening at a predetermined position, filling the inside of the pattern opening with a second insulating film by low-temperature CVD, and flattening this. a step of forming a dummy pattern having a trapezoidal cross-section; depositing a metal thin film on the entire surface of the pattern; applying a second photoresist on the metal thin film; selectively leaving only on the dummy pattern having a trapezoidal cross-section; A step of selectively removing and molding the lower half of the dummy pattern having a trapezoidal cross-section obliquely inward using a charged particle beam to form a dummy pattern having a hexagonal cross-section, and then removing the mask; , and the entire surface including the dummy pattern with a hexagonal cross section, and after etching back to expose the dummy pattern, the dummy pattern with a hexagonal cross section is removed, and the dummy pattern with the same cross section is removed. forming an inverted pattern opening to selectively expose a predetermined portion of the active layer; depositing a vapor-deposited metal film on the entire surface thereof; and lifting it off onto the exposed active layer. 1. A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode.