JPH0221701U - - Google Patents
Info
- Publication number
- JPH0221701U JPH0221701U JP10049888U JP10049888U JPH0221701U JP H0221701 U JPH0221701 U JP H0221701U JP 10049888 U JP10049888 U JP 10049888U JP 10049888 U JP10049888 U JP 10049888U JP H0221701 U JPH0221701 U JP H0221701U
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- internal
- internal conductor
- electrode
- electrically connected
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004020 conductor Substances 0.000 claims description 5
- 239000000758 substrate Substances 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Non-Adjustable Resistors (AREA)
Description
第１図は本願考案の実施例の拡大平面図、第２
図は第１図の―線断面図、第３図ａおよび第
３図ｂは製造工程説明図である。
２…チツプ基板、３…第一の内部導体層、４…
誘電体層、５…第二の内部導体層、７，８…電極
。
Figure 1 is an enlarged plan view of the embodiment of the present invention;
The figure is a sectional view taken along the line -- in FIG. 1, and FIGS. 3a and 3b are illustrations of the manufacturing process. 2... Chip substrate, 3... First internal conductor layer, 4...
Dielectric layer, 5... second internal conductor layer, 7, 8... electrode.
補正 昭６３．１０．２４
図面の簡単な説明を次のように補正する。
明細書第９ページ１６行目の「製造工程説明図
である。」を「製造工程説明図、第４図は従来例
を示す斜視図である。」と補正する。Amendment October 24, 1983 The brief description of the drawing is amended as follows. In the 16th line of page 9 of the specification, "This is a manufacturing process explanatory diagram." is corrected to "The manufacturing process explanatory diagram, FIG. 4 is a perspective view showing a conventional example."
Claims (1)
、上記チツプ基板の表面に、一方の電極に導通す
る第一の内部導体層と、この第一の内部導体層を
覆う内部誘電体層と、他方の電極に導通し、内部
誘電体層を覆う第二の内部導体層とを積層印刷形
成したことを特徴とする、超高抵抗チツプ型抵抗
器。 electrodes are formed on both sides of the square chip substrate, a first internal conductor layer electrically connected to one electrode on the surface of the chip substrate, and an internal dielectric layer covering the first internal conductor layer; An ultra-high-resistance chip resistor characterized in that a second internal conductor layer that is electrically connected to the other electrode and that covers the internal dielectric layer is formed by laminated printing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988100498U JPH0521842Y2 (en) | 1988-07-27 | 1988-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988100498U JPH0521842Y2 (en) | 1988-07-27 | 1988-07-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0221701U true JPH0221701U (en) | 1990-02-14 |
| JPH0521842Y2 JPH0521842Y2 (en) | 1993-06-04 |
Family
ID=31328625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988100498U Expired - Lifetime JPH0521842Y2 (en) | 1988-07-27 | 1988-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0521842Y2 (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50143061A (en) * | 1974-05-04 | 1975-11-18 |
-
1988
- 1988-07-27 JP JP1988100498U patent/JPH0521842Y2/ja not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50143061A (en) * | 1974-05-04 | 1975-11-18 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0521842Y2 (en) | 1993-06-04 |