JPH0221757U - - Google Patents
Info
- Publication number
- JPH0221757U JPH0221757U JP10029488U JP10029488U JPH0221757U JP H0221757 U JPH0221757 U JP H0221757U JP 10029488 U JP10029488 U JP 10029488U JP 10029488 U JP10029488 U JP 10029488U JP H0221757 U JPH0221757 U JP H0221757U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- voltage
- power supply
- supply terminal
- regulator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims 1
- 238000007599 discharging Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の実施例の回路図、第２図は５
Ｖレギユレータの特性図である。
Fig. 1 is a circuit diagram of an embodiment of the present invention, and Fig. 2 is a circuit diagram of an embodiment of the present invention.
It is a characteristic diagram of a V regulator.
Claims (1)
た電源が供給されるＣ―ＭＯＳ ＩＣ２のラツチ
アツプ解除回路において、 入力電圧Ｖｉｎで充電される積分回路Ｒ１，Ｃ
１と、 該レギユレータ１の入力端子に該入力電圧Ｖｉ
ｎを与える第１のトランジスタＱ１と、 該積分回路Ｒ１，Ｃ１の積分電圧Ｖ１が一定値
以上のときオンして該第１のトランジスタＱ１に
ベース電流を供給する第２のトランジスタＱ２と
、前記電源端子の電圧Ｖ２が一定値以上のときオ
ンして該積分回路Ｒ１，Ｃ１のコンデンサＣ１を
放電すると共に、前記第１のトランジスタＱ１に
ベース電流を供給する第３のトランジスタＱ３と
を備えてなることを特徴とするラツチアツプ解除
回路。[Scope of Claim for Utility Model Registration] In the latch-up release circuit of C-MOS IC2 to which stabilized power is supplied to the power supply terminal by the regulator 1, the integrating circuits R 1 and C are charged with the input voltage Vin.
1 , and the input voltage Vi is applied to the input terminal of the regulator 1.
a first transistor Q 1 that supplies n, and a second transistor that turns on when the integrated voltage V 1 of the integrating circuits R 1 and C 1 is a certain value or more and supplies a base current to the first transistor Q 1 . Q 2 and the voltage V 2 of the power supply terminal are turned on when the voltage V 2 of the power supply terminal is above a certain value, discharging the capacitor C 1 of the integrating circuit R 1 and C 1 , and supplying the base current to the first transistor Q 1 . A latch-up release circuit comprising a third transistor Q3 .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10029488U JPH0221757U (en) | 1988-07-28 | 1988-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10029488U JPH0221757U (en) | 1988-07-28 | 1988-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221757U true JPH0221757U (en) | 1990-02-14 |
Family
ID=31328248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10029488U Pending JPH0221757U (en) | 1988-07-28 | 1988-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221757U (en) |
-
1988
- 1988-07-28 JP JP10029488U patent/JPH0221757U/ja active Pending