JPH0221983U - - Google Patents
Info
- Publication number
- JPH0221983U JPH0221983U JP1988100402U JP10040288U JPH0221983U JP H0221983 U JPH0221983 U JP H0221983U JP 1988100402 U JP1988100402 U JP 1988100402U JP 10040288 U JP10040288 U JP 10040288U JP H0221983 U JPH0221983 U JP H0221983U
- Authority
- JP
- Japan
- Prior art keywords
- output
- circuit
- control pulse
- pulse input
- counter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001934 delay Effects 0.000 claims 1
- 230000001960 triggered effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例によるセレクタ回
路を示すブロツク図、第２図は同上実施例の動作
を説明するためのタイムチヤート、第３図は従来
のセレクタ回路のブロツク図、第４図は第３図の
セレクタ回路の動作を説明するためのタイムチヤ
ートである。
２……遅延回路、４……単安定マルチバイブレ
ータ、６……論理積回路、８……ｎ進リングカウ
ンタ、１０……デコーダ。なお、図中、同一符号
は、同一、又は相当部分を示す。
FIG. 1 is a block diagram showing a selector circuit according to an embodiment of this invention, FIG. 2 is a time chart for explaining the operation of the same embodiment, FIG. 3 is a block diagram of a conventional selector circuit, and FIG. 4 is a time chart for explaining the operation of the selector circuit shown in FIG. 3. 2... Delay circuit, 4... Monostable multivibrator, 6... AND circuit, 8... N-ary ring counter, 10... Decoder. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
遅延回路の出力によつて、トリガされ所定のパル
ス幅のパルスを発生する単安定マルチバイブレー
タと、この単安定マルチバイブレータの出力と上
記制御パルス入力の論理積を得る論理積回路と、
上記制御パルス入力をカウントし、かつ上記論理
積回路の出力で、リセツトされるカウンタと、こ
のカウンタのバイナリ出力をデコードし、セレク
タ出力を出力するデコーダとを備えたセレクタ回
路。 A delay circuit that delays a control pulse input, a monostable multivibrator that is triggered by the output of this delay circuit to generate a pulse with a predetermined pulse width, and the logic of the output of this monostable multivibrator and the control pulse input. an AND circuit that obtains a product;
A selector circuit comprising: a counter that counts the control pulse input and is reset by the output of the AND circuit; and a decoder that decodes the binary output of the counter and outputs a selector output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988100402U JPH0221983U (en) | 1988-07-27 | 1988-07-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988100402U JPH0221983U (en) | 1988-07-27 | 1988-07-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0221983U true JPH0221983U (en) | 1990-02-14 |
Family
ID=31328443
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988100402U Pending JPH0221983U (en) | 1988-07-27 | 1988-07-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0221983U (en) |
-
1988
- 1988-07-27 JP JP1988100402U patent/JPH0221983U/ja active Pending