JPH022199B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alarm device that transmits information from gas leak alarms, security alarms, etc. installed in various parts of a building to a monitoring device installed in a management room or the like.

Conventionally, the above-mentioned alarm device consists of, for example, a central monitoring device and a plurality of terminal devices, each of which is assigned a different address. supplies different address signals and monitoring command signals to each terminal device via the first line, and the terminal device corresponding to the transmitted address determines whether it is normal or not when the monitoring command signal is supplied. A response signal, which is a signal indicating whether there is an abnormality or a signal indicating the status of the monitored equipment, is sent to the central monitoring device via a second line that is different from the first line, and the central monitoring device There is a method that repeatedly performs processing according to the received signal (Japanese Patent Laid-Open No. 52-25993).

With such an alarm device, it is possible to know not only the status of each monitored device but also whether the terminal device is normal or not. However, it requires a first line for transmitting address signals and supervisory command signals from the central monitoring device to each terminal device, and a second line for transmitting response signals from each terminal device to the central monitoring device. However, there was a problem in that the wiring between the central monitoring device and each terminal device became complicated. Furthermore, with such alarm devices, when all terminal devices are monitored once and monitoring is restarted from the beginning, even though accurate information about the monitored device cannot be obtained from the abnormal terminal device, , and the central monitoring device processes the information from that terminal device before calling the next terminal device, so the problem is that it takes a long time to monitor all terminal devices. It was hot too.

This invention not only simplifies the wiring between the central monitoring device and each terminal device, but also allows the system to monitor all terminal devices by immediately calling the next terminal device when a terminal device with an abnormality is called. The purpose of the present invention is to provide an alarm device that reduces the time required for the alarm.

The present invention will be explained below based on one embodiment shown in the drawings. In FIG. 1, numeral 1 is a central monitoring device, which is installed, for example, in a building's management room, and 2-0 to 2-15 are terminal devices, which are installed at various locations in the building. Addresses 0 to 15 are assigned to these terminal devices 2-0 to 2-15, and furthermore, addresses 0 to 15 are assigned to the terminal devices 2-0 to 2-15, and furthermore, addresses 0 to 15 are assigned to terminal devices 2-0 to 2-15.
Type information 3 is provided. Central monitoring device 1
and each terminal device 2-0 to 2-15 are connected via a coaxial cable 4 and a series unit 5.

As shown in FIG. 2, the central monitoring device 1 has a 4-bit binary counter section 6. This 4-bit binary counter section 6 generates an output for calling each terminal device 2-0 to 2-15, and the output of each bit is initially "0000" corresponding to address 0, and these are They are supplied to the pulse width generation circuit 8 in parallel with each other. Pulse width generation circuit 8
generates four pulse signals with different widths according to the value of each supplied digital signal of each bit, and in this embodiment, the digital signal of each bit changes to "0" with reference to 1.5 msec. For
A 2ms pulse signal is generated, and four 1ms pulse signals are generated for the same "1". Therefore, if the output of the 4-bit binary counter section 6 is "0000" as described above, a total of 16 2 msec pulse signals are generated.
In the case of "1010", 1ms pulse signal, 2ms pulse signal, 1ms pulse signal,
A 2 msec pulse signal is generated by repeating it four times in sequence. Based on the serial pulse signal from the pulse width generation circuit 8, the FM-PWM transmitter 10 generates a pulse width modulation signal, which is transmitted to each terminal device 2--via the mixer 12, coaxial cable 4, and series unit 5.
0 to 2-15.

Each terminal device 2-0 to 2-15 converts the pulse width modulation signal from the central monitoring device 1 into an FM-
It is supplied to the PWM receiving section 14, received and demodulated, and then sent to the decoder section 16 to receive and demodulate the 4 bits corresponding to each bit.
is converted into parallel signals.

These four parallel signals are respectively supplied to corresponding ones of the four comparison circuits 20 to 23 provided in the pulse width comparison section 18 as shown in FIG.
It is converted into a bit digital signal. Each of the comparison circuits 20 to 23 is composed of a one-shot multi 24 and an R.S. flip-flop (hereinafter abbreviated as R.SF.F) 25, as shown in FIG. The one-shot multi 24 responds to the rising edge of the parallel pulse signal supplied to its comparator circuit, as shown in FIGS. 5a and 5b.
The value of the built-in time constant circuit 26 is selected to generate a 1.5 msec pulse signal, and this pulse signal b is supplied to the S terminal of the R, SF, F25. A parallel pulse signal is supplied to the R terminal. Therefore, as shown in Figure 5c, the output of R, SF, F25 is "1" while the parallel pulse signal is a 1 msec pulse signal, and is "0" while the parallel pulse signal is a 2 msec pulse signal. ”. Therefore, when the output of the 4-bit binary counter section 6 of the central monitoring device 1 is "0000", the outputs of the R, SF, and F 25 of each of the comparison circuits 20 to 23 are respectively "0". Each comparison circuit 20
The outputs of R, SF, and F25 of 23 to 23 are integrated circuit 2.
7, the respective time differences are adjusted and supplied to the 4-bit decoder section 29, and an output is generated on one of the 16 output lines of the 4-bit decoder section 29 corresponding to the digital signal "0000".

At this time, the control circuit 30 of the terminal device 2-0
The FM-PWM transmitter 32 is operated to transmit a pulse width modulated signal to the central monitoring device 1 via the mixer 13, the series unit 5, and the coaxial cable 4. This pulse width modulation signal is generated based on the pulse signal generated by the pulse width generation circuit 34,
This pulse signal is a set of four pulse signals with different widths depending on whether the four types of information 3 are "normal" or "abnormal" that are supplied in parallel to the control circuit 36 from a gas leak alarm, a security alarm, etc. In this example, each pulse signal of each set is 1 msec when each information is normal, and 2 msec when it is abnormal.
It is of seconds. For example, if the security alarm warning information is "normal", the security alarm alarm information is "abnormal", the gas leak alarm operation stop information is "abnormal", and the gas leak alarm alarm information is "normal", The pulse width generation circuit 34 repeats four sets, each consisting of one 1 ms pulse signal, two 2 ms pulse signals, and one 1 ms pulse signal. generate. Note that when the four types of information are supplied to the control circuit 36, the control circuit 36 operates the display device 38, the alarm device 40, and the external alarm output 42 in accordance with the information.

The pulse width modulated signal from the FM-PWM transmitter 32 of the terminal device 2-0 is sent to the FM-PWM transmitter of the central monitoring device 1.
The signal is supplied to the PWM receiving section 44 via the mixer 13, and after being received and demodulated here, the signal is sent to the decoder section 4.
6: Security alarm alert information, security alarm alarm information,
The signal is converted into four parallel pulse signals corresponding to the gas leak alarm operation stop information and the gas leak alarm information, and is supplied to the pulse width comparator 48.

The pulse width comparison unit 48 converts each of the four parallel pulse signals into digital signals, and when each parallel pulse signal is composed of a 1 msec pulse signal, it is set to "0", and when each parallel pulse signal is composed of a 1 msec pulse signal, it is set to "0"; If it is composed of , each is converted to "1". That is, the pulse width comparison section 48 includes comparison circuits 50, 51, 52, and 53 provided to correspond to four parallel pulse signals, respectively, as shown in FIG.
Each comparison circuit 50, 51, 52, 53 is a one-shot multi 54 and an AND circuit 5.
5, an integrating circuit 56, an inverter 57, a one-shot multi 58, and an AND circuit 59.
The one-shot multi 54 generates a negative output for 1.5 msec in response to the rising edge of the supplied parallel pulse signal, as shown in FIGS. 7a and 7b.
This output and the parallel pulse signal are input to an AND circuit 55. Therefore, as shown in Figure c, only when the parallel pulse signal is 2 msec, which indicates an abnormal condition,
The AND circuit 55 generates an output "1" during the time difference between the 1.5 msec output of the one-shot multi 54 and the 2 msec pulse signal, that is, 0.5 msec. This output "1" is shaped by the integrating circuit 56 and then supplied to the AND circuit 59, and is also inverted by the inverter 57 and supplied to the one-shot multi 58. As shown in d and e of the figure, in response to the rise of the trailing edge of the output of the inverter 57, the one-shot multi 58 generates an output of "1" for a predetermined time (80 msec), and as shown in f of the figure. AND circuit 59 generates an output "1" every time output "1" is supplied to AND circuit 59 during this time. Therefore, since each parallel pulse signal is composed of four 2 msec or 1 msec pulse signals, the comparator circuits 50, 5
1, 52, and 53 are one shot multi 58 when a 2 msec pulse signal is initially supplied.
operates, and generates an output "1" every time the remaining 2ms pulse signal is supplied. The outputs of these comparison circuits 50, 51, 52, 53 are sent to a synthesis circuit 60.
-0 to 60-15.

The synthesis circuits 60-0 to 60-15 are provided to correspond to each of the terminal devices 2-0 to 2-15, and the security alarm alert information digitized by the pulse width comparison unit 48 is sent to each synthesis circuit 60. -0 to 6
0-15 input terminal 61, security alarm warning information to the same input terminal 62, gas leak alarm operation stop information to the same input terminal 63, gas leak alarm alarm information to the same input terminal 64 in parallel. For example, when the security alarm warning information supplied to the input terminal 61 is "1", this is transmitted to the capacitor 6 via the resistor 65a and the diode 66a.
7a, is discharged by a resistor 68a, and "1" is input to an AND circuit 69a.
At this time, if the output of the 4-bit binary counter section 6 is "0000", an output "1" is generated at _S0 of the 4-bit decoder section 70 shown in FIG. AND circuits 69a to 69
d, the AND circuit 69a generates an output "1", and it is displayed that there is an abnormality during the security alarm of the terminal device 2-0. A similar display is made when output "1" is generated at the other input terminals 62 to 64.

As shown in FIG.
When a predetermined time of 100 msec has elapsed since the signal was supplied from the bit binary counter section 6, the decoder section 46
In response to the generation of a pulse signal, the one-shot multi 72 generates an output, updates the output of the 4-bit binary counter section 6 by one, and thereafter, the terminal devices 2-1, 2-2, . . . , 2- 15 are sequentially called, and each time they are called, information is transmitted to the central monitoring device 1 and displayed.

The failure alarm unit 74 shown in FIG.
This is to display which terminal device is out of order when any of the terminal devices 0 to 2-15 is out of order and no longer sends a signal to the central monitoring device 1, as shown in Figure 9. The failure alarm circuit 75-0 corresponds to each terminal device 2-0 to 2-15.
75-15. Failure alarm circuit 75
-0 to 75-15 each have an AND circuit 76, to which corresponding outputs _S0 to _S15 are supplied from the 4-bit decoder section 70. Now, 4
When the output of the bit binary counter section 6 is "0000", _S0 is "1" and the failure alarm circuit 75-0
"1" is supplied to the AND circuit 76. In this state, when one second elapses after there is no trace of transmission from the terminal device 2-0, the output of the retrigger one shot 77, which responds to the fact that no pulse signal is generated in the decoder section 46, becomes "1", causing a failure. Alarm circuit 75
-0's AND circuit 76 is further supplied with "1", and its output becomes "1". This output is voltage-divided by resistors 78 and 79 and applied to the gate of thyristor 80, which makes thyristor 80 conductive and lights up light emitting diode 81, indicating that the terminal device 2-0 is out of order. . In addition, capacitor 8
2 is for noise cancellation, and a reset switch 83 is for turning off the light emitting diode 81 when a failure is repaired.

If one of the terminal devices 2-0 to 2-15 is out of order, the path section 84 shown in FIG. This is for the first
As shown in Figure 0, each terminal device 2-0 to 2-15
Pass circuits 85-0 to 85-1 correspond to
5. These pass circuits 85-1 to 85-8
5-15 each have a one-shot multi 86. These one-shot multis 86 are configured to generate an output for 0.5 msec in response to the rising edge of an input pulse, and these outputs are connected to four outputs via an inverter 87 and a diode 88, respectively.
It is supplied in parallel to the input of the bit binary counter section 6. The input side of the one-shot multi 86 is connected via a coupling capacitor 86 to the collector of a transistor 90, and its base is connected via a resistor 91 to the anode of the thyristor 80 of the corresponding fault alarm circuit. The emitter and base of this transistor 90 are connected via a resistor 92, the base is further connected to the collector of a transistor 93, the emitter of this transistor 93 is connected to the emitter of the transistor 90,
The base of the transistor 93 is connected to the output of the corresponding 4-bit decoder section 70, for example, _S0 in the case of the pass circuit 85-0. transistor 90,9
Emitter 3 is connected to Vdd.

Therefore, for example, if the terminal device 2-0 is not malfunctioning and is not being called, the thyristor 80 of the failure display circuit 75-0 is non-conductive;
Transistors 90 and 93 are OFF, and no input pulse is supplied to one-shot multi 86.
In addition, if there is no failure but a call is made, the thyristor 80 of the failure display circuit 75-0 is still non-conductive, so the transistors 90 and 93 are turned OFF.
Therefore, no input pulse is supplied to the one-shot multi 86. If faulty but not called, thyristor 80 of fault indication circuit 75-0
is conductive and S ₀ is "0", so transistor 93 is turned on, and since the base and emitter of transistor 90 are short-circuited by transistor 93, transistor 90 remains off. If there is a failure and it is called, the thyristor 80 of the failure indication circuit 75-0 is conductive, but since _S0 is "1", the transistor 93 is turned off, and the voltage between the emitter and base of the transistor 90 is turned off. Since the short circuit is released, the transistor 90 turns on, and the transistor 90 turns on.
ON, the input pulse is supplied, and the one-shot multi 8 is faster than the one-shot multi 72.
6 causes the 4-bit binary counter section 6 to be updated. In this way, if the one-shot multi 86 is out of order, each call will be passed through the terminal. Note that Sw0 to Sw15 are the path circuits 85-0 to 85-0 in which they are provided.
-Terminal devices 2-0 to 2 corresponding to 15 respectively
-15 is forcibly passed through.

As described above, according to the alarm device according to the present invention, the first modulated signal sent from the central monitoring device to each terminal device and the second modulated signal sent from each terminal device to the central monitoring device are transmitted over the same coaxial cable. transmitted by. Therefore, wiring between the central monitoring device and each terminal device requires only one coaxial cable, which simplifies the wiring. In addition, since the central monitoring device is equipped with a failure alarm section and a path section, even if an address signal is generated to call a terminal device in which a failure has occurred, the failure alarm section continues to be generated since the occurrence of the failure. In response to the current failure alarm signal, the path section immediately causes the 4-bit binary counter 6 to generate the next address signal, so that the next terminal device is immediately called. Therefore, there is no need to judge whether the called terminal device is responding or not, and the time required to call all terminal devices is shortened by the amount of time required to call all terminal devices if there is a malfunctioning terminal device. It doesn't waste time. When such an operation is attempted by a microcomputer, for example, the microcomputer determines that the called terminal is not responding, and then determines whether this unresponsive terminal is the same terminal that did not respond last time. If so, an address signal for calling the next terminal device must be generated, and additional time is required to make these two determinations. However, according to this occurrence, the path section generates the next address signal in response to the failure alarm signal that has been continuously generated since the occurrence of the failure, so it takes time to determine whether there is a response or not. This eliminates the need for the terminal device that has not responded to the previous one to determine whether the terminal device has not responded, and the next terminal device can be called quickly. Moreover, since this invention does not use a microcomputer, the cost is reduced.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an alarm device according to the present invention, Fig. 2 is a block diagram of a central monitoring device used in the alarm device, Fig. 3 is a block diagram of a terminal device used in the alarm device, and Fig. 4 is a block diagram of the terminal device. A block diagram of the pulse width comparison section used in the device, FIG. 5 is its time chart, FIG. 6 is a block diagram of the pulse width comparison section used in the central monitoring device, FIG. 7 is its time chart, and FIG. 8 is the same. FIG. 9 is a block diagram of a combining circuit used in the central monitoring device. FIG. 10 is a block diagram of a path section used in the central monitoring device. 1... Central monitoring device, 2-0 to 2-15...
Terminal device, 6...4-bit binary counter section,
10, 32...FM-PWM transmitter, 14, 44
...FM-PWM receiving section, 18... Pulse width comparison section, 29... 4-bit decoder section, 60-0 to 60-15... Synthesizing circuit.

Claims (1)

[Claims] 1. Consisting of a central monitoring device and a plurality of terminal devices connected in series to the central monitoring device via coaxial cables and each having a different address assigned to the central monitoring device, , an address signal generating device that sequentially generates each of the address signals at predetermined time intervals, and a first modulated signal that modulates the address signal and transmits a first modulated signal to each of the terminal devices via the coaxial cable.
a second transmission device configured to transmit a second modulated signal obtained by modulating the alarm signal supplied from the sensor to each of the terminal devices to the central monitoring device via the coaxial cable; a first demodulator that receives a first modulated signal and demodulates it into the address signal; and a device that activates a second transmission device when the demodulated address signal is equal to the address assigned to the terminal device. and further provided in the central monitoring device, a second demodulator that receives a second modulated signal and demodulates it into the alarm signal, and an address signal from the address signal generator and the demodulated alarm. a device for activating a predetermined alarm based on the signal; and a second modulated signal transmitted from the terminal device corresponding to the address signal generated by the address signal generator, which is provided corresponding to each of the terminal devices. a failure alarm section that continuously generates a failure alarm signal when the terminal device is not received; a device for causing the address signal generating device to immediately generate the next address signal in response to the generated failure alarm signal when the address signal of the terminal device corresponding to the generated failure alarm unit is generated; Alarm device provided.