JPH02222278A - Electronic still camera equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to an electronic still camera device that converts a photographed optical image into an electrical video signal and records it on a recording medium.
In particular, the present invention relates to a device designed to effectively utilize the capacity of the recording medium.

(Prior Art) As is well known, in general cameras, the captured optical image is formed on a silver halide film, so unless the film is chemically processed and developed, the captured image cannot be viewed. is not possible.

In response, in recent years, electronic photographic systems have been developed that eliminate the need for complicated chemical processing by converting the captured optical image into an electrical video signal and displaying the image on a television receiver. , is becoming popular in the market. An example of such an electronic photographic system is a still image recording system.

In this still image recording system, a tape, disk, drum, or the like made of magnetic material is attached to a camera body as a recording medium in the form of a cassette or cartridge. After taking a picture and recording the video signal on a recording medium, the recording medium is removed from the camera body and attached to a playback device, and the still image is displayed on a television receiver connected to the playback device. be.

However, in this type of still image recording system, since the recording medium is made of a magnetic material, a magnetic head and a drive mechanism for the recording medium are required to perform recording and reproduction.
Problems arise in that the configuration becomes more complex and larger, and power consumption also increases.

Therefore, in recent years, it has been considered to use a semiconductor memory as a recording medium to eliminate the need for a magnetic head, drive mechanism, etc., thereby reducing the size, weight, and power consumption. In particular, in recent years, with the advancement of semiconductor element mounting technology,
2. Description of the Related Art Memory cards incorporating semiconductor memories have come into practical use, and development for using these memory cards as recording media is actively underway.

By the way, in the conventional electronic still camera device that uses a memory card as a recording medium as described above, the video signal is converted into digital data, and then the band is compressed and stored in the semiconductor memory, so still images cannot be captured. - The data length for each image differs depending on the content of the captured image, the compression ratio specified by the user, etc. Furthermore, still image data is sequentially written into the memory, such as the first image, second image, etc. in the order in which they were photographed.

Therefore, if the data of, for example, the n-th still image becomes unnecessary during shooting and is deleted, the deleted storage area will be
This means that a still image having a data length greater than or equal to the data length of the n-th still image cannot be recorded. Therefore, some still images taken after the nth one have a data length of n.
Unless there is something shorter than the data length of the first still image, the erased storage area will not be used at all and will be wasted.
A problem arises in that the storage capacity of the memory is not effectively utilized (challenge 8 to be solved by the invention) As described above, in the conventional electronic still camera device, the storage capacity of the semiconductor memory is not effectively utilized. The problem is that there is no.

Therefore, the present invention has been made in consideration of the above circumstances, and provides an extremely good electronic still camera device that can organically utilize the recording area of a recording medium without wasting it, and can effectively utilize the recording capacity. The purpose is to

[Structure of the Invention] (Means for Solving the Problems) An electronic still camera device according to the present invention converts a photographed optical image into an electrical video signal and records it on a recording medium having a semiconductor memory element. It is targeted. and,
A video signal is divided into a plurality of parts, distributed over a plurality of empty recording areas of a recording medium, and recorded, and information indicating the number of divisions of the recorded video signal and the recording position of each divided video signal is recorded on the recording medium. It was designed to do so.

(Function) According to the above configuration, a video signal is distributed and recorded in a plurality of empty recording areas generated on a recording medium, and the number of divisions of the recorded video signal and the number of divided video signals are determined. Since the recording position is recorded on the recording medium, the recording area of the recording medium can be used organically without waste, and the recording capacity can be used effectively.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. The electronic still camera device described in this embodiment is composed of a camera body 11 and a memory card 12 that is detachably attached to the camera body 11, as shown in FIG. The camera body 11 has a lens barrel 13, a viewfinder 14, and a shutter 1, like a normal camera.
5 and an opening 16 into which a memory card 12 is inserted.

FIG. 4 shows the internal structure of the camera body 11. That is, numeral 17 in the figure is a lens disposed within the lens barrel 13, and a subject image is projected by this lens I7 onto a solid-state imaging device 18, such as a CCD, disposed on the back surface of the lens 17.

The solid-state image sensor 18 outputs an analog electrical signal (video signal) according to the brightness of the image projected through the lens 17, and this electrical signal is
The data is converted into digital data by a D (analog/digital) conversion circuit I9, and after band compression is performed by a band compression circuit 20, it is supplied to a memory card control circuit 21.

Further, 22 in FIG. 4 is a microphone placed outside the camera body 11. The audio signal output from the microphone 22 is converted into digital data by an A/D conversion circuit 23, subjected to predetermined data processing by a digital audio processing circuit 24, and then supplied to the memory card control circuit 21.

Furthermore, 25 in FIG. 4 is a CPU, which performs overall control of the entire electronic still camera device including the memory card I2, and, for example, controls the drive of the solid-state image sensor 18 and performs band compression via the drive system 2B. It controls the compression ratio of the circuit 2o, and also controls the memory card control circuit 21 and the memory card 12.

FIG. 5 shows the configuration of the memory card control circuit 21 and its surroundings. In the figure, reference numeral 27 denotes an I10 control circuit, which performs input/output control between a memory 28 or CPU 25, which will be described later, and the memory card I2 in order to exchange data therebetween.

That is, data related to images from the band compression circuit 20 is manually inputted to the memory 28 via the data input terminal 29, and data related to audio from the digital audio processing circuit 24 is inputted via the data input terminal 3o. has been done. Then, the output data of this memory 28 and the data generated by the CPU 25 are transferred to the I10 control circuit 27.
The data is sent from the data input/output terminal 31 to the memory card 12 via the data input/output terminal 31.

Furthermore, data supplied from the memory card 12 via the data input/output terminal 31 is sent to the CPU 25 via the r10 control circuit 27.

Here, a memory 32 is interposed and connected on the data line between the CPU 25 and the I10 control circuit 27, and an interface for data transfer speed is established between them. In other words, the data input/output by the CPU 25 is serial data and low speed, while the data input/output by the I10 control circuit 27 is parallel data and high speed. Converts parallel data into parallel data or serial data respectively 〇 Also, 33 in Fig. 5 is an address generation circuit, which is connected to the CPU 2.
It generates address data corresponding to the initial address value of the memory card 2 and memory 2B specified by 5 and the address value obtained by sequentially adding "1" to this initial address value, and this address data is sent to the memory 28. At the same time, the memory card 12 is output via the address output terminal 34.
sent to.

Furthermore, 35 in FIG. 5 is a timing signal generation circuit, and C
Based on the designation from the PU 25, the I10 control circuit 27.
Memory 2B, 32. It generates a predetermined timing signal to the address generation circuit 33 and also generates a timing signal to the memory card 12 via the timing output terminal 36.

Next, FIG. 6 shows a detailed configuration of the memory card 12. As shown in FIG. That is, this memory card I2 has a large number of memories such as RAM and E2 FROM on a board 37, which can electrically rewrite data.
. . , and connection terminals 39 connected to the camera body 11 are arranged in a row at one end of the board 37.

The memory card 12 has a data input/output terminal 40 connected to the data input/output terminal 3I of the camera body 11, as shown in FIG. This data input/output terminal 40 is connected to a plurality of memories 3g, 38. through an I10 control circuit 41. It is connected to each data input/output terminal of...

The memory card 12 also has an address input terminal 42 connected to the address output terminal 34 of the camera body 11. This address input terminal 42 is connected to the memory 3B.
, 38. . . . are connected to each address input terminal and the chip select circuit 43. Note that this chip select circuit 43 selects the memory 38 .
H, . . . are selected.

Further, the memory card 12 has a timing input terminal 44 connected to the timing output terminal 3B of the camera body 11. This timing input terminal 44 is connected to the memory 38.38. It is connected to each timing input terminal of...

FIG. 2 shows a plurality of memories 3g of the memory card 12.

38, . . . shows a memory map for explaining a memory area configured by 38, . That is,
This memory area is roughly divided into four areas: a status flag area, a division area, a directory area, and an image data area.

Among these, still image data obtained by photographing a subject is stored in the image data area. As shown in FIG. 1, this image data area includes a first block, a second block,
. . . is divided into 256 blocks called the 256th block.

Each of these blocks has the same fixed recording capacity.

However, the recording capacity of one block is not set to correspond to the amount of data for one still image, but rather is set smaller than the amount of data for one still image.

Then, when photographing is performed, image data corresponding to the first still image is recorded, for example, in an area between the first and second blocks and the middle of the third block. Further, image data corresponding to the second still image is recorded in an area halfway between the fourth block and the fifth block. Furthermore, the image data corresponding to the third still image is the sixth still image. It is recorded in the area between the seventh block and the middle of the eighth block. below,
Similarly, image data corresponding to a plurality of still images is recorded.

Here, a status flag indicating whether data is recorded for each block is recorded in the status flag area. This status flag is set to '1' for a block in which even 1 byte of data is recorded.
m, and becomes "0°" for an empty block in which no data is recorded.

In addition, in the above-mentioned division area, when the image data for a still image is divided into multiple parts and recorded in the image data area, a division indicating how many parts the image data for the still image is divided into. number is recorded. In this case, the number of still images that can record the number of divisions is 2 from screen 1 to screen 256.
It is set for 56 sheets. Further, the maximum number of divisions of image data for still images is "4".

Furthermore, the directory area contains still images 1 to 256 that are divided into four at most and recorded in the image data area.
The start address and end address, which are recording positions in the image data area, of each divided image data are recorded, respectively.

Next, the photographing operation of the electronic still camera device configured as described above will be explained. First, when the memory card 12 is inserted into the camera body 11 through the opening 1B, the memory card control circuit 2 in the camera body 11
Each terminal 31, 34, 38 of memory card 12 is connected to each terminal 40, 42, 44 of memory card 12, respectively.

Then, the CPU 25 causes the timing signal generation circuit 35 to output data from the memories 38, 38 . . . . generates a signal to read data from the memory 3B, 38. Generates an address that specifies the status flag area of...

Therefore, data in the status flag area of the memory card 12 is transferred to the CPU 25 via the I10 control circuit 41.27 and the memory 32.

Here, the CPU 25 calculates the number of available programs in the image data area based on the data in the status flag area.
Memory 3B, 38. In addition to checking whether image data can be written to . . . , calculating how many parts the image data should be divided into, memory
. . . and calculates from which address in the memory 28 (start address) to which address (end address) the next image data should be written.

Then, if image data can be written, the CPU
25 sets the start address and end address of the memory 28 in the address generation circuit 33. As a result, the camera body 11 can be opened by the user using the shutter 15.
is in a state of waiting for operation.

Therefore, when the user presses the shutter 15, the CP
U25 outputs the timing signal generation circuit 35 to the memory 2.
While generating a signal to write data to 8,
The address generation circuit 33 generates the address data set as described above at a predetermined timing.

Therefore, the video signal output from the solid-state image sensor 18 is sent to the memory 28 via the A/D conversion circuit 19 and the band compression circuit 20, and at the same time, the address data generated by the address generation circuit 33 is also sent. It is sent to memory 28 and written to memory 28.

Next, the CPU 25 inputs the start address and end address of the image data written into the memory 28 and the memory 3
g, 38. The start address and end address for writing are set in the address generation circuit 33. Then, the CPU 25 causes the timing signal generation circuit 35 to generate a signal for reading data from the memory 28, and also causes the memory 3B, 3
8. Generates a signal to write data to...

At the same time, the CPU 25 causes the address generation circuit 33 to transfer the address data set as described above to the memory 28 and the memory 38.3g, . . .
. . occurs at a predetermined timing. Therefore, the previously written image data is read out from the memory 28 and transferred to the memory 38.38 via the I10 control circuit 27.41.
, . . . and written into the image data area.

When such writing is completed, the CPU 25
The status flag data updated from is stored in the memory 32.
and memory 38.3 via I10 control circuit 27.41.
8. . . . and the status flag area is updated. Thereafter, the CPU 25 sends the timing signal generation circuit 35 to the memory 38, 38, .
...Generates a signal to stop a series of write operations for.

Here, by the write operation as described above, the memory 38
．． 38. As shown in Figure 1, the image data for the first to third still images is recorded in the image data area of . Suppose you erase the data. This erasing operation can be performed by the user
This is automatically performed by the CPU 25 by specifying the number of sheets and operating an erase switch (not shown) provided in the CPU 25.

When the erase operation is performed, the contents of the status flag area are also automatically updated. In this case, the fourth and fifth blocks become empty blocks.

In FIG. 1, it is assumed that the ninth block is also an empty block.

In such a state, the CPU 25 confirms that the fourth and fifth blocks are empty blocks, that is, data can be written, based on the contents of the status flag area, and also determines how many parts the image data should be divided into. Calculation, memory 38.3B, ... and memory 28
Calculations are performed such as from which address (start address) to which address (end address) should the next image data be written.

Then, the CPU 25 causes the address generation circuit 33 to
Set the start address and end address of the memory 28. As a result, the camera body 11 is placed in a standby state for the shutter 15 to be operated by the user.

Therefore, when the user presses the button 15 to take the nth still image (for example, the fourth), the CP
U25 outputs the timing signal generation circuit 35 to the memory 2.
While generating a signal to write data to 8,
The address generation circuit 38 generates the address data set as described above at a predetermined timing.

Therefore, the video signal output from the solid-state image sensor 1B is sent to the memory 28 via the A/D conversion circuit 19 and the band compression circuit 20, and at the same time, the address data generated by the address generation circuit 33 is also sent. The data is sent to memory 2B and written to memory 28.

Next, the CPU 25 writes the start address and end address of each divided data of the image data written to the memory 28, and the start address and end address (
4th. Fifth. (corresponding to the ninth block) is set in the address generation circuit 33. Then, the CPU 25 causes the timing signal generation circuit 35 to generate a signal for reading data from the memory 28, and also causes the memory 38.
Generates a signal to write data to 3g, . . . .

At the same time, the CPU 25 causes the address generation circuit 33 to transfer the address data set as described above to the memories 28, 38, 38, .・・・・・・
...is generated at a predetermined timing. Therefore, the image data written earlier is read out from the memory 28,
Memory 38°38, via I10 control circuit 27.41;
4th of... The data is distributed and recorded in the fifth block and the ninth block.

When such writing is completed, the CPU 25
The status flag data updated from is stored in the memory 32.
and memory 38.3 via I10 control circuit 27.41.
g, .
...Generates a signal to stop a series of write operations for.

Therefore, according to the configuration of the above embodiment, the image data is distributed and recorded in a plurality of empty blocks generated in the image data area of the memories 38.3B, . The number of divided image data and the recording position of each divided image data are stored in the memory 38.38°...
・Since the data is recorded in the division area and directory area of 3g and 38. . . . can be used organically without waste, and the recording capacity can be used effectively.

It should be noted that the present invention is not limited to the above-mentioned embodiments, and can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, it is possible to organically utilize the recording area of a recording medium without waste, and to provide an extremely good electronic still camera device that can effectively utilize the recording capacity. can be provided.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining an embodiment of an electronic still camera device according to the present invention, FIG. 2 is a diagram for explaining a memory area of a memory card used in the embodiment, and FIG.
The figure is an external view of the electronic still camera device according to the same embodiment, FIG. 4 is a block configuration diagram showing the detailed configuration of the device, and FIG.
The figure is a block diagram showing the detailed structure of the memory card control circuit of the same device, FIG. 6 is a perspective view showing the internal structure of the memory card of the same device, and FIG. 7 is a block diagram showing the detailed structure of the memory card. FIG. 11...Camera body, 12...Memory card, 13
... Lens barrel, 14... Finder, 15... Shutter, 16... Opening, 17... Lens, 18...
Solid-state image sensor, 19... A/D conversion port path, 20...
Band compression circuit, 21...Memory card control circuit, 22...Microphone, 23...A/D conversion circuit, 24...Digital audio processing circuit, 25...CP
U, 2B... Drive system, 27...110 control circuit, 2
8...Memory, 29, 30...Data input terminal, 3
1...Data input/output terminal, 32...Memory, 33.
...address generation circuit, 34...address output terminal,
35... Timing signal generation circuit, 36... Timing output terminal, 37... Board, 38... Memory, 3
9... Connection terminal, 40... Data input/output terminal, 41
... I10 control circuit, 42 ... address input terminal,
43... Chip select circuit, 44... Timing input terminal. Applicant's Representative Patent Attorney Takehiko Suzue

Claims (2)

[Claims] (1) In an electronic still camera device that converts a photographed optical image into an electrical video signal and records it on a recording medium having a semiconductor storage element, the video signal is divided into a plurality of parts and a plurality of empty recording areas of the recording medium are divided. The first
and a second recording means for recording information indicating the number of divisions of the video signal recorded by the first recording means and the recording position of each divided video signal on the recording medium. An electronic still camera device characterized by: (2) The recording medium includes a video signal recording area divided into a plurality of blocks each having a fixed recording capacity, and a first recording area in which information indicating whether each block of the video signal recording area is free is recorded. a recording area, a second recording area in which the number of divisions of the video signal is recorded, and a third recording area in which the start address and end address of each video signal divided and recorded in the video signal recording area are respectively recorded. a recording area, and the first recording means records each divided video signal in a distributed manner in a plurality of empty blocks determined from the contents of the first recording area, and 2. The electronic still camera device according to claim 1, wherein the recording means updates the contents of the first to third recording areas each time the first recording means records the video signal.