JPH02228021A - Method and apparatus for manufacturing semiconductor device and reticle used therein - Google Patents

Abstract

PURPOSE:To make the processing of wafers efficient by recording information with respect to the wafer as a bit pattern which is constituted of the assembly of minute bits, and registering a large amount of informations on the wafer. CONSTITUTION:A plurality of circuit element regions 2 are arranged in a matrix pattern on the surface of a wafer 1. Control indexes 3 are formed in the remaining region other than the circuit element regions 2. The control index 3 is constituted of a target pattern 4 for positioning and a neighboring bit pattern 5. The information regarding the wafer 1 is recorded as the bit pattern 5 which is constituted of the assembly of the minute bits. Thus, the large amount of the information can be registered on the wafer 1, and the processing of the wafer 1 can be made efficient.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention makes it possible to add a large amount of information such as a management index to the wafer itself and to perform highly accurate positioning in alignment when manufacturing semiconductor devices. Regarding technology.

[Conventional technology]

JP-A-51-140482, filed by the present applicant, describes a technique for writing management indexes on wafers in the manufacturing process of semiconductor devices.

As stated in the above publication, in the so-called pre-processing process using wafers in the manufacturing process of semiconductor devices,
A marking area is provided on a portion of the wafer surface that is not used as a circuit element to identify the wafer's product number, etc. Conventionally, this marking method was done by hand using a hard material such as diamond, but there were concerns that it would have a negative impact on work efficiency and product reliability, so currently marking is done by laser beam irradiation or etching. Marking has become mainstream.

[Problem to be solved by the invention]

However, in all of the technologies listed above, markings that can be visually recognized by operators are applied to the wafer surface, which requires a large area, which reduces product yield. This was a contributing factor.

Moreover, each of the above techniques has a limit to the amount of information that can be recorded, and the content has to be limited to only the loft number or product number.

Furthermore, when reading the above markings, a technology has been proposed in which numbers are recognized using photodiodes arranged in a 7-segment pattern as optical sensors, but the markings formed by etching etc. on the lower layer gradually change as they move toward the upper layer. This has caused problems such as difficulty in recognizing steps and automatic recognition.

The present invention has been made in view of the above-mentioned problems, and its first purpose is to enable the registration of a large amount of information such as design information or production control information on a wafer, and to automatically read this information. The goal is to achieve high precision, efficient and reliable wafer processing.

The second purpose is to achieve highly accurate alignment in the exposure process.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, first, a management index consisting of at least one pair of a target pattern and a bit pattern is formed on the wafer, and a reading start position of the bit pattern is detected based on recognition position information obtained from the target pattern. , index information is acquired from the wafer by sequentially reading bit patterns from the starting position.

Second, a predetermined periodic pattern is formed on a wafer, and the pattern is recognized by Fourier transform or standard deviation transform of the signal obtained from the reflected light of the pattern. At this time, the conversion is performed in a direction perpendicular to the detection axis direction.

[Effect]

According to the first method described above, by recording information about the wafer as a bit pattern made up of a collection of minute bits, it is possible to register a large amount of information on the wafer, making wafer processing more efficient. can do.

In addition, by providing a management index that combines the target pattern and bit pattern, the bit pattern can be read accurately based on the position coordinates determined by the target pattern, and wafer information can be automatically read. This can be achieved with high precision.

According to the second means, by selectively performing Fourier transformation or standard deviation transformation on the signal level in the direction of the periodic axis orthogonal to the detection axis direction, S/ The N ratio can be significantly improved,
Detection reliability can be greatly improved.

〔Example〕

As shown in FIG. 2, the wafer 1 of this embodiment has a plurality of circuit element areas 2 (bellet areas) arranged in a matrix on its surface, and the entire area of the circuit element areas 2 is used for management purposes. Index 3 is formed.

Here, as shown in FIG. 1, the management index 3 is composed of a positioning target pattern 4 and a bit pattern 5 adjacent thereto. Although the target pattern 4 is configured in the shape of a cross in the figure, it is not limited to this shape and may have any graphic shape. The details of this target pattern 4 are as shown in FIG. 16, in which regular squares each having a side of about 6 μm are arranged in a box shape at a pitch of 12 μm, and further arranged in a cross shape inside the box. The entire target pattern 4 has a vertical and horizontal side of about 120 μm. One bit pattern 5 is vertically 1 as a whole
It is composed of a rectangle with a diameter of 40 μm and a diameter of 315 μm, and the inside thereof is composed of a plurality of single bits 6 arranged in a matrix. Each single bit 6 is formed, for example, in a pattern as shown in FIG. 3, which will be described later.

As explained above, the management index 3 consisting of the target pattern 4 and the bit pattern 5 has a small rectangular shape with a length of about 140 μm and a width of about 465 μm, and is significantly different from conventional marking-based indexes. Since it can be formed small, it can be arbitrarily placed at multiple locations on the wafer l, as shown in FIG.

Here, the contents of the information recorded in the management index 3 in this embodiment will be briefly explained.

First, the information recorded on the wafer 1 in this embodiment includes design information as fixed information determined by the photomask or reticle 7, and production control information as variable information that differs for each wafer 1 or each arrangement coordinate. Divided. The former design information includes, for example, ■product name, ■process name, ■target pattern coordinates, and ■inspection pattern coordinates.

On the other hand, the latter production management information is composed of, for example, ■wafer loft number, ■wafer number, etc. FIG. 4 conceptually explains each information item and the method of registering it in the management index 3.

Next, a method for forming the management index 3 for design information and production management information will be specifically explained.

First, since the management index 3 related to design information is fixed information for the same series of products, a pattern shape is formed in advance on a photomask or reticle 7 together with a circuit pattern 8, as shown in FIG. ,
In the initial exposure process, a circuit pattern 8 is formed on the wafer 1.
It is possible to transfer the image onto the wafer 1 at the same time as or during the same exposure process. In the figure, chromium (Cr) is placed approximately in the center of a transparent reticle substrate 10 made of quartz glass or the like.
A circuit pattern 8 is formed by the vapor-deposited film, and a management index 3 in which the above-mentioned design information is registered as a bit pattern 5 is formed on the upper right side of the circuit pattern 8, and an outline pattern 11 for alignment is formed on the left side. It is formed.

On the other hand, since the management index 3 related to production management information needs to be different for each wafer due to the difference in loft number or Uni-Hachi number, the management index 3 related to production management information must be different for each wafer. The whole cannot be formed at the same time. Therefore, the bit pattern 5 in the management index 3 for the production management information is registered for each exposure process, for example, bit by bit. That is, as shown in FIG. 5, the reticle 7 includes, in addition to the target pattern 4 for the design information described above, one bit corresponding to the exposure process in the bit pattern 5 of the management index 3 of the production management information. The single bit 6 is formed in a predetermined area of the wafer 1 during the same process as the transfer process of the circuit pattern 8 by the reticle 7.
is transferred. FIG. 6 shows the transfer state of this single bit 6, and the details will be described later.

FIG. 7 shows an exposure device 12 used to form the management index 3 on the wafer 1. As shown in FIG. In the figure, a wafer 1 fixed to a wafer chuck 15 is placed on the upper surface of an XY stage 14 installed on a base 13 and movable in the horizontal direction. A reduction projection lens 16 is disposed above the wafer 1, an exposure optical system 17 is disposed further above the wafer 1, and an alignment optical system 18 is disposed on the side. Alignment optical system 18
The alignment light from the alignment light source 20 is irradiated onto the wafer 1 through the condenser lens 21, half mirror 22, relay lens 23, reflector 24 and reduction projection lens 16, and the reflected light of the alignment light follows the above path. The light travels backwards and enters the pattern detection TV camera 25, where it is recognized as an image signal.

Further, the exposure optical system 17 includes an exposure light source 26 made of a mercury lamp or the like, and a condenser mirror 27 made of a concave mirror, and is configured such that exposure illumination reaches the reticle 7 through an integrator 28 and a condenser lens 21. In this embodiment, a masking blade 30 is disposed between the condenser lens 21 and the reticle 7, and a predetermined range of exposure illumination that is irradiated onto the reticle 7 is blocked so that it does not reach the wafer l. It has become.

FIG. 6 shows the positional relationship between the masking blade 30, the reticle 7, and the wafer 1. The figure shows the positional relationship when only the bits (single bit 6) of information corresponding to the exposure process using the reticle 7 are transferred in the management index 30-bit pattern 5 for production management information. , does not show the actual positional relationship in transferring the circuit pattern 8. It is desirable that the bits corresponding to such a predetermined exposure process be transferred immediately before or after the exposure process. Note that the masking blade 30 shown in the figure is a reticle 70.
It is formed to cover the entire surface, and as shown in Figure 6, it contains one bit of production control information and the white pattern 1.
It has a structure that allows exposure illumination to pass through only the range corresponding to 1.

Although not shown, the masking blade 30 is provided with means for fine adjustment in the X and Y directions, and can be moved in the horizontal direction.

FIG. 8(a) shows a pattern such as target pattern 4 or bit pattern 5 (hereinafter pattern 3) explained above.
(b) shows the cross-sectional structure of each wafer process step for forming a wafer (generally referred to as 1).

In FIG. 8(b) above, first, a silicon oxide film 82 is formed on the surface of a semiconductor substrate 81 made of silicon (Si).
) is grown to a thickness of about 0.05 μm, patterning for doping with impurities is performed using photoetching technology, and at the same time, a pattern 31a indicated by 3 is formed.

Next, in the second element isolation step, a silicon oxide film is further deposited at a predetermined location on the silicon oxide film 82 to form an element isolation layer, but at the same time, a pattern 31b shown in (3) is formed. Ru. Such a pattern 31b has a deposition height of about 0.35 μm.

After the above steps, a second silicon oxide film 83, a first gate film 84, a third silicon oxide film 85, a second gate film 86, and a fourth silicon oxide film are formed on the silicon oxide film. A silicon oxide film 87 is sequentially formed, and a first wiring 88 made of aluminum (AI) is formed on the silicon oxide film 87. Simultaneously with the formation of the first wiring, a pattern 31C is formed by etching in the portion indicated by .

By the way, when various layers are formed above such a pattern 31, the level difference of the pattern located in the lower layer is not reflected in the upper layer, and therefore it may be difficult to recognize the pattern from the upper layer. In such a case, for example, the pattern 31C formed when forming the first wiring 88 may be further overlapped when forming the second wiring 89 to form the pattern 31d.

As described above, in this embodiment, the recognition of the pattern 31 can be improved by forming the pattern 31 in a plurality of steps such as an impurity doping step, an element isolation step, and a wiring step.

Although the formation of the pattern 31 has been schematically explained above based on FIG. 8, it may be formed through other processes other than those described above.

Next, a method for recognizing the target pattern 4 and bit pattern 5 formed by the above steps will be specifically explained.

Unlike the exposure device 12 explained in FIG. 7, FIG.
A configuration is shown in which the alignment optical system 18 is provided independently of the exposure optical system 17.

An objective lens 32 and a half mirror 33 are arranged at a predetermined angle above the wafer 1 fixed to the upper surface of a wafer chuck (not shown in the figure). An alignment light source 35 composed of a halogen lamp or the like is arranged on the side of the half mirror 33 via a condenser lens 34. Further, in the figure, a TV left camera 6 is arranged above the half mirror 33.

In the figure, alignment light from an alignment light source 35 passes through a condenser lens 34 to a half mirror 3.
After being refracted at a predetermined angle at 3, the light passes through the objective lens 32 and is irradiated onto the wafer l. Here, the detection light reflected from the wafer l is transmitted to the objective lens 32 and the half mirror 33.
The light travels straight ahead and is incident on the TV left camera 6. The TV left camera 6 converts the incident detection light into an electrical signal, and after performing arithmetic processing to be described later in the image processing circuit 37, the position of the target pattern 4 or the code of the bit pattern 5 is recognized. Here, FIG. 10 conceptually shows a state in which a periodic pattern constituting, for example, the target pattern 4 is recognized. In the figure, the periodic pattern obtained from target pattern 4 is
It is photographed on the imaging plane of the left camera 6 and recognized as an image.

Next, the arithmetic processing performed in the image processing circuit 37 based on the image signal from the TV left camera 6 will be explained.

The image processing circuit 37 of this embodiment performs Fourier transform or standard deviation calculation based on the image signal to attenuate noise components and improve recognition accuracy.

Figure 11 shows the principle of Fourier transform, and generally any function f (x) with periodicity can be expressed as follows (1) to (
As shown in 3), it can be expanded into a Fourier series.

It turns out. Therefore, by performing Fourier transform on the detected image signal in the image processing circuit 37, the accuracy of pattern recognition can be greatly improved.

Note that the variable X in the above equations (1) to (3) is a dimensionless number and needs to be converted into a distance X'. This is shown below.

2π/X = k/X'
(4) (k = period length) Here, as n; 1, in equations (2) and (3) above, (
4) Substituting the equation, In the above equation, equations (2) and (3) are the function f (X
), its absolute value becomes large only when the period and phase match, and it becomes a minute value even under other conditions.

In other words, the values of a, , , b, that match the period of the periodic pattern in target pattern 4 result in a state in which only the signal component from target pattern 4 is amplified, and other noise components are attenuated. , x' = x, and if the variables are x and y, then the following is obtained. In the above formulas (7) and (8), X and y can be replaced with each other. It is also possible to provide an offset to the integration range.

Next, the directionality in the above Fourier transform will be explained.

First, let us consider the case where Fourier transform is performed in the same direction as the detection axis X for an image signal having a light intensity distribution as shown in FIG. 12(a). 1st
2 et al.) show a simulation program in a basic language, in which line number 60 performs Fourier Co5 transform (X direction), and line number 70 performs Fourier Sin transform (X direction). Also, line numbers 1000 to 11
In the subroutines up to 00, image signals are generated in a pseudo manner.

FIG. 12(C) shows the execution result at this time. As is clear from the figure, when Fourier transform is performed in the same direction as the detection axis X, although the S/N ratio of the image signal improves, the sharpness of the signal deteriorates significantly. This shows that Fourier transformation in the direction of the detection axis X is not preferable.

Next, a case will be described in which Fourier transform is performed on an image signal having a light intensity distribution as shown in FIG. 13(a) in a direction perpendicular to the detection axis X, that is, in the y-axis direction.

FIG. 13(b) is a simulation program written in a basic language, in which line number 60 performs Fourier Co5 transform (y direction) and line number 70 performs Fourier Sin transform (y direction).

The above simulation results are shown in Figure 13 (
C). The image signal after such Fourier transformation in the y-axis direction can be converted into S/S without deteriorating the sharpness of the signal.
The N ratio can be significantly improved.

In this way, in this embodiment, by performing Fourier transformation at the signal processing level in the image processing circuit 37, transformation only in the direction perpendicular to the detection axis X can be realized, so that the sharpness of the signal can be maintained at a high level. In contrast, conventional technology has proposed a technique to improve recognition accuracy by applying optical Fourier transform using a filter, etc. However, since Fourier transform at the optical level is performed simultaneously in the x and y directions, Even though the S/N ratio was improved, the sharpness of the signal deteriorated.

The above simulation program was written in a basic language for simplicity, but it is possible to convert variables into integers,
By creating a table of the CQS function and the sin function, it is possible to speed up the calculation process.

Next, the interval standard deviation transformation performed by the image processing circuit 37 together with the Fourier transformation will be explained.

Standard deviation is generally given by the following formula.

(However, f=average value) A case will be described in which an interval standard deviation conversion is performed in the same direction as the detection axis X in an image signal having a light intensity distribution as shown in FIG. 14(a).

In the simulation program shown in FIG. 14 et al., section standard deviation conversion in the X direction is performed by the loop of line numbers 40 to 85. In addition, line numbers 1000 to 1
Image signals are generated in a pseudo manner using 100 subroutines.

The results of the above simulation are shown in the 14th
Figure (C).

As is clear from the figure, when the interval standard deviation conversion is performed in the same direction as the detection axis X, the sharpness of the signal deteriorates significantly, making it impossible to maintain high recognition accuracy.

On the other hand, FIGS. 15(a) to 15(C) show cases in which interval standard deviation conversion is performed in a direction perpendicular to the detection axis X direction, that is, in the periodic axis y direction. As is clear from FIG. 15(C) showing the results of this simulation, the S/N ratio is improved without deterioration of signal sharpness.

However, in the interval standard deviation conversion in this case, a frequency separation function cannot be obtained due to the conversion principle.

Next, the recognition method for target pattern 4 and bit pattern 5 will be specifically explained separately.

As described above, the target pattern 4 is formed of a periodic pattern as shown in FIG. 16, and the position is recognized by calculating the center of the cross.

FIG. 17 shows a flowchart of the method for recognizing target pattern 4 as described above.

First, when the image processing circuit 37 captures an image signal from the TV camera 36 (step 1701), as explained earlier, it performs Fourier transformation in the direction perpendicular to the detection axis X, that is, in the periodic axis y direction (1702). . The sum of the squares of a (X) and b (X) thus obtained is calculated to obtain R(3) (1703).

Next, the center position of each of the plurality of combinations of periodic patterns is calculated using the threshold value (1704), and combinations of pattern intervals (L+, L2) are selected (1705).
), calculate the center of target pattern 4 (170
6).

Next, target pattern 4 obtained as above
A case will be described in which a predetermined code composed of bit pattern 5 is read based on the center coordinates of .

Here, single bit 6 constituting bit pattern 5
An example of a pattern is shown in Figure 3, in which "1" or "0" is expressed by forming the patterns shown in (a) to (C) in an area of 35 μm on each side in the vertical and horizontal directions. It shall be.

The process will be explained below with reference to the flowchart shown in FIG.

First, an image signal is captured from the TV camera 36 to the image processing circuit 37 (1801), and the center coordinates of the target pattern 4 are calculated according to the sequence described in FIG. 17 (1802). The reading start position of bit pattern 5 is calculated based on the center coordinates of target pattern 4 (1803). At this time, in this embodiment, as shown in FIG.
Since the bit pattern 5 and the bit pattern 5 are formed as a pair with a predetermined positional relationship, by using the target turn 4 as a reference, the reading start position of the bit pattern 5 can be accurately grasped.

Next, the image signal from the predetermined single bit 6 is subjected to Fourier transform in the image processing circuit 37, but the direction of the Fourier transform at this time is the periodic axis that is orthogonal to the detection axis This is done in the y direction (1804).

After obtaining the sum of squares R(X) of a (X) and b (x) calculated in this way (1805), R(X
) is calculated (1806), and the result obtained by subtracting both values is greater than the preset judgment value ε (,1
The relevant bit is “1” or “0” depending on whether
(1807). The binary code thus obtained is output to a 0 output device (not shown) as letters, numbers, or symbols in hexadecimal code (1
806). Therefore, for example, in accordance with the ASCII code, 8 bits, ie, 8 single bits 6, are required to represent one alphanumeric character.

Next, regarding a modification of bit pattern reading, the first
This will be explained using FIG.

Here, up to steps 1901-1903, the previous 18th
Since it is similar to the figure, the explanation will be omitted.

First, after starting to read bit pattern 5, data in the y direction is compressed and averaged (1904).

Next, Fourier transform in the X direction is performed (1905).

The period of the Fourier transform at this time is the same.

Next, Fourier transform is performed with twice the period in the X direction (1906). In this way, even in the case of Fourier transform in the .

The sum of squares R of all values of the thus obtained Fourier transform with one period and the Fourier transform with twice period is calculated (1907).

Next, it is determined whether the bit is "l" or "10" depending on whether the above R is greater than the determination value ε (1908). The bit string is output as a hexadecimal code (1909).

In the above description, the case where the image signals obtained in the image processing circuit 37 are all recognized by Fourier transform has been explained, but FIG. 20 is a flowchart in the case of recognition by interval standard deviation transform.

In the same figure, steps 2001 to 2003 are the same as in the case of FIG. 19, so the explanation will be omitted.

When reading of the bit pattern 5 is started, the standard deviation of the image signal obtained by scanning the single bit 6 is calculated (2004). As a result, it is determined whether the single bit 6 is “1” or “0” based on whether the obtained value S is larger than the preset determination value ε (2005), and it is determined in hexadecimal format. Output as code (2
006). In this way, recognition using standard deviation has the advantage that it is easy to detect if the amplitude is large regardless of periodicity, so it is easier to detect bit pattern 5 than recognition of target pattern 4. It is more advantageous to use it for recognition.

To summarize the above, in this example, when recognizing a periodic pattern such as target pattern 4, recognition using Fourier transform is superior to interval standard deviation without a frequency classification function, and bit When recognizing a non-periodic pattern like pattern 5, either Fourier transform or interval standard deviation transform is possible.

The hexadecimal code output in this way can be used to register, for example, a product identification number, loft number, etc., as well as, for example, process specifications. By reading the process specifications registered in this way from the management index 3, it becomes easy to determine the process conditions to be performed next.
It is also possible to improve the efficiency of the treatment process. Moreover, in this embodiment, since the information regarding the process specifications is registered in the wafer 1 itself, the wafer 1 and the information are not dispersed, and error-free and reliable process management can be realized.

As described above, according to this embodiment, by recording information regarding the wafer 1 as the bit pattern 5 made up of a collection of minute bits, it is possible to register a large amount of information on the wafer 1, and the wafer 1 processing can be made more efficient.

Furthermore, by providing a management index 3 in which the target pattern 4 and the bit pattern 5 are integrated,
The bit pattern 5 can be read accurately based on the position coordinates determined by the target pattern 4, and the wafer information can be automatically read with high accuracy.

Since the management index 3 is formed through each exposure process, a separate marking process is not required, and the wafer process can be performed efficiently.

Furthermore, by using the image processing circuit 37 to perform Fourier transform on the signal level in the direction of the periodic axis orthogonal to the detection axis direction, detection reliability can be greatly improved.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor.

For example, '1' or '0' in single bit 6
The pattern ' is not limited to the one shown in FIG. 3, but may have any stepped shape. Furthermore, the periodic target pattern 4 is not limited to the shape shown in FIG. 16.

In addition, although the management index 3 has been explained in the case where it is formed only by the target pattern 4 and the bit pattern 5, in addition to such a management index, conventional management indexes using symbols, numbers, etc. can be replaced by laser marking, etc. It may also be written in terms of technology.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, by recording information about the wafer as a bit pattern made up of a collection of tiny bits, it is possible to register a large amount of information on the wafer, which not only makes wafer processing more efficient, but also improves the reliability of reading wafer information. You can increase your sexuality.

[Brief explanation of the drawing]

Fig. 1 is a plan view showing the management index used in this embodiment, Fig. 2 is a plan view showing the entire wafer, Fig. 3 is an explanatory drawing showing the single bit pattern shape, and Fig. 4 is the top view of the wafer. Fig. 5 is a plan view showing the reticle used in this embodiment; Fig. 6 is an explanatory drawing showing the positional relationship between the reticle and the masking blade. , FIG. 7 is an explanatory diagram showing the exposure apparatus used in this example, FIGS. 8(a) and (c) are explanatory diagrams showing the steps and cross-sectional structure of the pattern formation process, and FIG. 9 is an explanatory diagram showing the exposure apparatus used in this example. Figure 1O is an explanatory diagram conceptually showing a state in which this alignment optical system forms a periodic pattern. Figures 11(a) to (C) are Fourier An explanatory diagram showing the principle of transformation. Figure 12 (a) is an explanatory diagram showing the calculation direction in the detection axis X direction in the light intensity distribution in Fourier transform. Figure 12 (b) is a simulation program. Figure 12 (C )
are diagrams showing the execution results of the program, Figure 13 (a) is an explanatory diagram showing the calculation direction in the periodic axis y direction, Figure 13 et al.) is the simulation program, and Figure 13 (C) is the execution of the program. Figure 14(a) shows the calculation direction in the detection axis X direction in the light intensity distribution in the interval standard deviation conversion.
C) is a diagram showing the execution results of the program, FIG. 15(a) is an explanatory diagram showing the calculation direction in the periodic glaze y direction, FIG.
Figure (C) is a diagram showing the execution results of the program, Figure 16 is an explanatory diagram showing a periodic target pattern, Figure 17 is a flowchart showing the target pattern recognition procedure, Figures 18 to 20 are 3 is a flowchart illustrating a bit pattern recognition procedure. DESCRIPTION OF SYMBOLS 1... Wafer 2... Circuit element area, 3... Management index, 3... Management index, 4...
・Target pattern, 5...Bit pattern, 6・
... Single bit, 7... Reticle, 8... Circuit pattern, 1O... Reticle board, 11... White pattern, 12... Exposure device, 13... Base, 14
...XY stage, 15...Wafer chuck, 16
... Reduction projection lens, 17... Exposure optical system, 18.
... Alignment optical system, 20... Alignment light source, 21... Condenser lens, 22... Half mirror 23... Relay lens, 24... Reflector, 25...
...TV camera for pattern detection, 26...exposure light source,
27... Concentrating mirror, 28... Integrator, 30...
...Masking blade, 31...Pattern, 32.
...Objective lens, 33...Half mirror 34...Condenser lens, 35.. Clear alignment light source, 36.
...TV left camera 37...image processing circuit. Agent Patent Attorney Daiwa Tsutsui 9 Figure λ7 Figure 10 Figure 20

Claims (1)

[Claims] 1. A management index including at least one pair of a target pattern and a bit pattern is provided on the wafer, and a reading start position of the bit pattern is detected based on positional information recognized by the target pattern; A method for manufacturing a semiconductor device, comprising acquiring index information from a wafer by sequentially reading bit patterns from the starting position. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the bit pattern is composed of a set of single bits representing "1" or "0". 3. A claim characterized in that the management index is transferred from the photomask or reticle at the same time or during the same exposure process when the circuit pattern on the photomask or reticle is transferred onto the wafer through an exposure device. Item 1. A method for manufacturing a semiconductor device according to item 1. 4. A claim characterized in that when transferring the bit pattern, only the bit information of the bit area corresponding to the exposure process is transferred, and the bit pattern is not transferred to the bit areas corresponding to other exposure processes. Item 3. A method for manufacturing a semiconductor device according to Item 3. 5. A semiconductor device having a pattern formed in a periodic shape on a wafer, the pattern being recognized by Fourier transforming a signal obtained from the reflected light of the pattern. Production method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein the Fourier transformation is performed in a direction perpendicular to the detection axis direction. 7. A method for manufacturing a semiconductor device, comprising a predetermined pattern on a wafer, and the pattern is recognized by calculating the standard deviation of a signal obtained from reflected light from the pattern. 8. Claim 8, wherein the pattern is a binary or multivalued bit pattern, and the value of each bit is recognized by calculating the standard deviation of the signal obtained from the reflected light of the pattern. 7. The method for manufacturing a semiconductor device according to 7. 9. The method of manufacturing a semiconductor device according to claim 7, wherein the standard deviation is performed in a direction perpendicular to the direction of the detection axis. 10. A horizontal moving means, a wafer movable by the moving means, an alignment light source that irradiates alignment light onto a predetermined portion of the wafer, and an image that uses the reflected light of the alignment light from the wafer as detection light. A manufacturing apparatus for a semiconductor device, comprising means for converting the image signal into a signal, and an image processing means capable of selectively Fourier transforming the image signal at least in a direction orthogonal to a detection axis direction in the light intensity distribution. 11. A moving means in the horizontal direction, a wafer movable by the moving means, an alignment light source that irradiates alignment light onto a predetermined part of the wafer, and an image that uses the reflected light of the alignment light from the wafer as detection light. A manufacturing apparatus for a semiconductor device, comprising means for converting an image signal into a signal, and an image processing means capable of selectively calculating a standard deviation of an image signal at least in a direction perpendicular to a detection axis direction in a light intensity distribution. 12. A semiconductor device having a management index on the wafer that records a process specification encoded in a bit pattern, and determining processing conditions for the process by reading the bit pattern of the management index during processing. manufacturing method. 13. A reticle characterized in that a management index pattern is formed together with a circuit pattern.