JPH0222904A - Phase synchronous demodulator - Google Patents

Phase synchronous demodulator

Info

Publication number
JPH0222904A
JPH0222904A JP17419788A JP17419788A JPH0222904A JP H0222904 A JPH0222904 A JP H0222904A JP 17419788 A JP17419788 A JP 17419788A JP 17419788 A JP17419788 A JP 17419788A JP H0222904 A JPH0222904 A JP H0222904A
Authority
JP
Japan
Prior art keywords
signal
phase
synchronization
oscillator
low
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17419788A
Other languages
Japanese (ja)
Other versions
JPH0724371B2 (en
Inventor
Shinji Senba
仙波 新司
Norio Komiyama
典男 小宮山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd filed Critical NEC Corp
Priority to JP17419788A priority Critical patent/JPH0724371B2/en
Publication of JPH0222904A publication Critical patent/JPH0222904A/en
Publication of JPH0724371B2 publication Critical patent/JPH0724371B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To stably discriminate synchronization or not even at the time of input of a signal of low S/N by providing a band-pass filter in the synchronization discriminating circuit of a sweep circuit in a phase synchronizing loop. CONSTITUTION:A demodulator 1 and a digital sweep circuit 2 are provided. A filter 22 which is inserted to the route between a low frequency oscillator 21 and synchronization discriminating means 23 and 24 and has a frequency band near the oscillation frequency of the oscillator 21 as the pass band is provided to eliminate noise components which penetrate synchronization discriminating means 23 and 24 of the digital sweep circuit 2. Thus, the stable leading-in operation is performed even for a phase modulated wave input signal of low S/N to stably discriminate synchronization or not.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、位相変調方式に利用する。特に、デジタル掃
引回路が付加され、位相同期ループを有する復調器に関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applied to a phase modulation method. In particular, it relates to a demodulator with an added digital sweep circuit and a phase-locked loop.

〔概要〕〔overview〕

本発明は、デジタル掃引回路が付加された位相同期ルー
プを有する位相変調復調器において、デジタル掃引回路
の同期判定手段に侵入する雑音成分を除去することによ
り、 安定した同期非同期判定が行えるようにしたものである
The present invention enables stable synchronization/asynchronous determination in a phase modulation demodulator having a phase-locked loop to which a digital sweep circuit is added by removing noise components that invade the synchronization determination means of the digital sweep circuit. It is something.

〔従来の技術〕[Conventional technology]

位相変調方式に用いられる復調器として、電圧制御発振
器の出力信号を入力信号に位相同期させる方法が従来か
ら用いられてきた。第3図にこの種の復調器の構成の一
例を示す。この回路は、第3図に示すように、位相比較
器11、搬送波再生信号処理回路12、合成器13、低
域通過フィルタ14および電圧制御発振器15からなる
位相同期ループ型の復調器1と、低周波発振器21、検
波器23、電圧比較器24、低周波発振器25、スイッ
チ26.2進カウンタよりなるカウンタ27およびデジ
タルアナログ変換器28からなるデジタル掃引回路2と
を備え、搬送波同期信号処理回路の出力が接続される端
子29と合成器13の入力が接続される端子18とが接
続さする。
Conventionally, as a demodulator used in a phase modulation method, a method has been used in which the output signal of a voltage controlled oscillator is phase-synchronized with the input signal. FIG. 3 shows an example of the configuration of this type of demodulator. As shown in FIG. 3, this circuit includes a phase-locked loop demodulator 1 consisting of a phase comparator 11, a carrier-wave regenerated signal processing circuit 12, a synthesizer 13, a low-pass filter 14, and a voltage-controlled oscillator 15; The carrier synchronized signal processing circuit includes a low frequency oscillator 21, a wave detector 23, a voltage comparator 24, a low frequency oscillator 25, a switch 26, a counter 27 consisting of a binary counter, and a digital sweep circuit 2 consisting of a digital-to-analog converter 28. The terminal 29 to which the output of the synthesizer 13 is connected is connected to the terminal 18 to which the input of the synthesizer 13 is connected.

位相変調波人力信号aは端子10を経て位相比較器11
に入力され、互いに直交した搬送波信号で位相比較され
て生成された同相分信号すおよび直交分信号Cは搬送波
再生信号処理回路12に入力される。この回路内で変調
信号の影響が取り除かれ、位相変調波入力信号aと電圧
制御発振器15の出力する再生搬送波信号dとの位相差
に相当した直流電圧が生成される。この信号は合成器1
3を経て低域通過フィルタ14に接続され、ここで高域
成分を除去された後に電圧制御発振器15に接続され、
電圧制御発振器15の位相が位相変調波入力信号aの位
相と同期するように制御される。また、搬送波再生信号
処理回路12の出力は端子17および20を経て低周波
発振器21の発振のための帰還ループに接続され、位相
同期ループが同期している場合には発振を停止し、同期
ループが外れている場合には発振するように動作する。
The phase modulated wave human input signal a passes through the terminal 10 to the phase comparator 11.
The in-phase signal C and the orthogonal signal C, which are generated by phase comparison using mutually orthogonal carrier signals, are input to the carrier reproduction signal processing circuit 12 . In this circuit, the influence of the modulation signal is removed, and a DC voltage corresponding to the phase difference between the phase modulated wave input signal a and the reproduced carrier wave signal d output from the voltage controlled oscillator 15 is generated. This signal is synthesizer 1
3 and is connected to a low-pass filter 14, where high-frequency components are removed, and then connected to a voltage controlled oscillator 15.
The phase of the voltage controlled oscillator 15 is controlled to be synchronized with the phase of the phase modulated wave input signal a. Further, the output of the carrier wave regenerating signal processing circuit 12 is connected to the feedback loop for oscillating the low frequency oscillator 21 via terminals 17 and 20, and when the phase locked loop is synchronized, the oscillation is stopped and the locked loop is If it is out of place, it will oscillate.

この低周波発振器21の出力は検波器23で検波され、
電圧比較器24で同期状態の判別が行われる。電圧比較
器24の出力を制御信号として低周波発振器25の出力
する信号が開閉される。このスイッチ26は非同期状態
ではスイッチが閉じ、同期状態ではスイッチが開くよう
に制御される。低周波発振器25の開閉出力は、2進カ
ウンタを縦続接続したカウンタ27でカウントされ、数
ビットのパラレル出力に変換された後にデジタルアナロ
グ変換器28でアナログ電圧に変換される。デジタルア
ナログ変換器28の出力は端子29および18を経て復
調器1の同期ループに入力され、合成器13で加算され
、電圧制御発振器15の出力する再生搬送波信号dと位
相変調入力信号aとが同期するまで掃引される。
The output of this low frequency oscillator 21 is detected by a detector 23,
The voltage comparator 24 determines the synchronization state. The signal output from the low frequency oscillator 25 is switched on and off using the output of the voltage comparator 24 as a control signal. This switch 26 is controlled so that it is closed in an asynchronous state and opened in a synchronous state. The switching output of the low frequency oscillator 25 is counted by a counter 27 having binary counters connected in cascade, converted into a several-bit parallel output, and then converted into an analog voltage by a digital-to-analog converter 28. The output of the digital-to-analog converter 28 is input to the synchronous loop of the demodulator 1 via terminals 29 and 18, and is added in the synthesizer 13, so that the recovered carrier signal d output from the voltage controlled oscillator 15 and the phase modulation input signal a are combined. Sweeps until synchronized.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、このような従来のデジタル掃引型復調器では、
位相変調波人力信号のSN比が高い場合には十分な掃引
、引込特性を示すが、SN比が低い場合には低周波発振
器21の出力に雑音が重畳され、検波器23の出力も雑
音で影響を受けるので、正確な同期判定ができなくなり
、安定な引込動作ができない欠点がある。
However, in such conventional digital sweep demodulators,
When the S/N ratio of the phase modulated wave human input signal is high, sufficient sweeping and pulling characteristics are exhibited, but when the S/N ratio is low, noise is superimposed on the output of the low frequency oscillator 21, and the output of the detector 23 is also noisy. As a result, accurate synchronization judgment cannot be made and stable retracting operation cannot be performed.

本発明はこのような欠点を除去するもので、SN比の低
い位相変調波入力信号でも安定な引込動作が行える位相
同期復調器を提供することを目的とする。
The present invention aims to eliminate such drawbacks, and aims to provide a phase synchronization demodulator that can perform a stable pull-in operation even with a phase modulated wave input signal having a low S/N ratio.

〔問題点を解決するための手段〕[Means for solving problems]

本発明は、位相変調波信号が到来する位相比較器と、こ
の位相比較器に再生搬送波信号を与える電圧制御発振器
と、上記位相比較器で生成された信号に基づき位相変調
波信号と再生搬送波信号との位相差に相当の位相差信号
を生成する搬送波再生信号処理回路と、この位相差信号
に応じて発振する発振器と、この発振器の出力レベルに
基づき位相変調波信号と再生搬送波信号との同期状態を
判定する同期判定手段と、この同期判定手段の判定結果
に基づき同期制御信号を生成する同期制御信号生成手段
と、この同期制御信号と位相差信号にかかわる信号とを
合成した信号にかかわる信号を上記電圧制御発振器に与
える合成器とを備えた位相同期復調器において、上記発
振器と上記同期判定手段との間の経路に挿入され、この
発振器の発振周波数近傍の周波数帯域を通過帯域とする
フィルタを備えたことを特徴とする。
The present invention provides a phase comparator to which a phase modulated wave signal arrives, a voltage controlled oscillator that provides a regenerated carrier wave signal to the phase comparator, and a phase modulated wave signal and a regenerated carrier wave signal based on the signal generated by the phase comparator. a carrier wave regenerating signal processing circuit that generates a phase difference signal equivalent to the phase difference between the two, an oscillator that oscillates in response to this phase difference signal, and synchronization of the phase modulated wave signal and the regenerated carrier signal based on the output level of this oscillator. A synchronization determination means for determining a state, a synchronization control signal generation means for generating a synchronization control signal based on the determination result of the synchronization determination means, and a signal related to a signal obtained by combining the synchronization control signal and a signal related to a phase difference signal. a phase synchronization demodulator, the filter being inserted in a path between the oscillator and the synchronization determining means, and having a pass band in a frequency band near the oscillation frequency of the oscillator. It is characterized by having the following.

〔作用〕[Effect]

搬送波再生信号処理回路を経由して発振器に雑音が侵入
する。この雑音により同期判定手段での判定が不安定に
なり、特に、位相変調波入力信号のSN比が低いと同期
の引込動作ができなくなる。
Noise enters the oscillator via the carrier wave recovery signal processing circuit. This noise makes the judgment by the synchronization judgment means unstable, and in particular, when the S/N ratio of the phase modulated wave input signal is low, the synchronization pull-in operation becomes impossible.

同期判定手段の前段にこの雑音を除去するフィルタを設
けて安定した掃引、引込特性を確保する。
A filter for removing this noise is provided before the synchronization determining means to ensure stable sweep and pull-in characteristics.

〔実施例〕〔Example〕

以下、本発明の一実施例を図面に基づき説明する。 Hereinafter, one embodiment of the present invention will be described based on the drawings.

第1図は第一実施例の構成を示すブロック構成図である
。この実施例は、第1図に示すように、復調器1とデジ
タル掃引回路2とを備え、ここで、復調器1は、位相比
較器11と、搬送波再生信号処理回路12と、合成器1
3と、低域通過フィルタ14と、電圧制御発振器15と
を備え、またデジタル掃引回路2は、低周波発振器21
と、帯域通過フィルタ22と、検波器13と、電圧比較
器24と、低周波発振器25と、スイッチ26と、バイ
ナリカウンタをカスケード接続したカウンタ27と、デ
ジタルアナログ変換器28とを備える。すなわち、この
実施例は、位相変調波信号が到来する位相比較器11と
、この位相比較器11に再生搬送波信号を与える電圧制
御発振器15と、位相比較器11で生成された信号に基
づき位相変調波信号と再生搬送波信号との位相差に相当
の位相差信号を生成する搬送波再生信号処理回路12と
、この位相差信号に応じて発振する発振器である低周波
発振器21と、この発振器の出力レベルに基づき位相変
調波信号と再生搬送波信号との同期状態を判定する同期
判定手段である検波器23および電圧比較器24と、こ
の同期判定手段の判定結果に基づき同期制御信号を生成
する同期制御信号生成手段である低周波発振器25、ス
イッチ26、カウンタ27およびデジタルアナログ変換
器28と、この同期制御信号と位相差信号にかかわる信
号とを合成した信号にかかわる信号を上記電圧制御発振
器に与える合成器13と、上記発振器と上記同期判定手
段との間の経路に挿入され、この発振器の発振周波数近
傍の周波数帯域を通過帯域とするフィルタである帯域通
過フィルタ22とを備える。
FIG. 1 is a block configuration diagram showing the configuration of the first embodiment. This embodiment includes a demodulator 1 and a digital sweep circuit 2, as shown in FIG.
3, a low-pass filter 14, and a voltage-controlled oscillator 15, and the digital sweep circuit 2 includes a low-frequency oscillator 21.
, a bandpass filter 22 , a wave detector 13 , a voltage comparator 24 , a low frequency oscillator 25 , a switch 26 , a counter 27 in which binary counters are connected in cascade, and a digital-to-analog converter 28 . That is, this embodiment includes a phase comparator 11 to which a phase modulated wave signal arrives, a voltage controlled oscillator 15 that supplies a recovered carrier wave signal to this phase comparator 11, and a phase modulated wave signal based on the signal generated by the phase comparator 11. A carrier wave reproduction signal processing circuit 12 that generates a phase difference signal corresponding to the phase difference between the wave signal and the reproduction carrier wave signal, a low frequency oscillator 21 that is an oscillator that oscillates in response to this phase difference signal, and an output level of this oscillator. A detector 23 and a voltage comparator 24 are synchronization determining means for determining the synchronization state of the phase modulated wave signal and the reproduced carrier signal based on the synchronization determination means, and a synchronization control signal for generating a synchronization control signal based on the determination result of the synchronization determination means. A synthesizer that provides the voltage-controlled oscillator with a signal related to a signal obtained by combining the low-frequency oscillator 25, switch 26, counter 27, and digital-to-analog converter 28, which are generation means, and the synchronous control signal and a signal related to the phase difference signal. 13, and a band-pass filter 22 which is inserted in a path between the oscillator and the synchronization determination means and whose passband is a frequency band near the oscillation frequency of the oscillator.

次に、この実施例の動作を説明する。位相変調入力信号
aは端子10を経て位相比較器11に人力され、互いに
直交する搬送波信号で位相比較され生成された同相分信
号すおよび直交分信号Cが搬送波再生信号処理回路12
に出力され、ここで、変調波の影響が除かれて位相変調
入力信号aと再生搬送波信号dとの位相差に比例した直
流制御信号が生成され、この信号は合成器13を経由し
て低域通過フィルタ14に与えられ、ここで高域の雑音
が除かれた後に電圧制御発振器150周波数および位相
を制御する。このようにして電圧制御発振器15の出力
である再生搬送波信号dは位相変調入力信号aと同期す
ることができる。また、搬送波再生信号処理回路12の
出力は低周波発振器21の帰還ループに接続され、位相
同期ループが非同期のときにはこの発振器21は発振し
、同期しているときには発振が停止するように調整され
る。低周波発振器25の出力は帯域通過フィルタ22に
接続される。端子17および20を介して低周波発振器
21に漏れこんだ雑音を含む低周波発振器21の出力す
る信号から低周波発振器21の発振周波数近傍のみの信
号を帯域通過フィルタ22でとり出した後に検波器23
で電圧検出を行い、電圧比較器24で同期非同期判定を
行う。低周波発振器25の出力はスイッチ26で同期判
定出力に応じて開閉された後にカウンタ27でカウント
され、デジタルパラレル信号に変換された後にデジタル
アナログ変換器28に入力され、ここでアナログ信号に
変換される。スイッチ11は同期時には閉じ、非同期時
には開くように制御されるので、カウンタ27は同期時
には状態を保持し、非同期時にはカウントアツプする。
Next, the operation of this embodiment will be explained. The phase modulated input signal a is input to the phase comparator 11 via the terminal 10, and the phases are compared using mutually orthogonal carrier signals, and the generated in-phase signal and orthogonal signal C are sent to the carrier-wave regenerated signal processing circuit 12.
Here, the influence of the modulated wave is removed and a DC control signal proportional to the phase difference between the phase modulated input signal a and the recovered carrier signal d is generated. The signal is applied to a pass-pass filter 14, where high-frequency noise is removed, and then the frequency and phase of a voltage controlled oscillator 150 are controlled. In this way, the regenerated carrier signal d, which is the output of the voltage controlled oscillator 15, can be synchronized with the phase modulated input signal a. Further, the output of the carrier wave regenerating signal processing circuit 12 is connected to the feedback loop of a low frequency oscillator 21, and the oscillator 21 is adjusted so that it oscillates when the phase-locked loop is asynchronous, and stops oscillating when it is synchronized. . The output of low frequency oscillator 25 is connected to bandpass filter 22 . After extracting only the signal near the oscillation frequency of the low frequency oscillator 21 from the signal output from the low frequency oscillator 21 containing the noise leaked into the low frequency oscillator 21 through the terminals 17 and 20 using the band pass filter 22, the detector 23
The voltage is detected by the voltage comparator 24, and the synchronous/asynchronous determination is made by the voltage comparator 24. The output of the low frequency oscillator 25 is opened and closed by a switch 26 according to the synchronization judgment output, and then counted by a counter 27, converted into a digital parallel signal, and then inputted to a digital-to-analog converter 28, where it is converted into an analog signal. Ru. Since the switch 11 is controlled to be closed during synchronization and open during non-synchronization, the counter 27 maintains its state during synchronization and counts up during non-synchronization.

これによってデジタルアナログ変換器28の出力は同期
時には状態を保持し、非同期時には微視的に階段状で巨
視的に鋸状の電圧を発生する。この電圧は端子29から
出力され、合成器13の人力に接続された端子18を経
て位相同期ループに入力され、ループの制御信号に重畳
され、低域フィルタ14を経由して電圧制御発振器15
を掃引制御する。
As a result, the output of the digital-to-analog converter 28 maintains its state during synchronization, and generates a voltage that is microscopically step-like and macroscopically sawtooth during non-synchronization. This voltage is output from the terminal 29, inputted into the phase-locked loop via the terminal 18 connected to the human power of the synthesizer 13, superimposed on the control signal of the loop, passed through the low-pass filter 14, and is input to the voltage-controlled oscillator 15.
to control the sweep.

第2図は本発明の第二実施例の構成を示すブロック構成
図である。第一実施例と比較して低域通過フィルタ14
と合成器13との接続順序が入れかわっているほかは同
様の構成である。また、デジタル掃引回路2は第1図の
構成と同様である。また、この実施例の動作は第一実施
例の動作の場合と同様である。
FIG. 2 is a block configuration diagram showing the configuration of a second embodiment of the present invention. Low pass filter 14 compared to the first embodiment
The configuration is the same except that the connection order between the two and the synthesizer 13 is reversed. Further, the digital sweep circuit 2 has the same configuration as that shown in FIG. Further, the operation of this embodiment is similar to that of the first embodiment.

〔発明の効果〕〔Effect of the invention〕

本発明は、以上説明したように、位相同期ループの掃引
回路の同期判定回路内に帯域通過フィルタを設けるので
、低いSN比の信号入力時でも安定した同期非同期判定
が行え、広い同期範囲を確保することができる効果があ
る。
As explained above, the present invention provides a bandpass filter in the synchronization determination circuit of the sweep circuit of the phase-locked loop, so that stable synchronization and asynchronous determination can be performed even when a signal with a low S/N ratio is input, and a wide synchronization range is ensured. There is an effect that can be done.

23・・・検波器、24・・・電圧比較器、26・・・
スイッチ、27・・・カウンタ、28・・・デジタルア
ナログ変換器。
23...Detector, 24...Voltage comparator, 26...
Switch, 27...Counter, 28...Digital-analog converter.

Claims (1)

【特許請求の範囲】 1、位相変調波信号が到来する位相比較器(11)と、 この位相比較器に再生搬送波信号を与える電圧制御発振
器(15)と、 上記位相比較器で生成された信号に基づき位相変調波信
号と再生搬送波信号との位相差に相当の位相差信号を生
成する搬送波再生信号処理回路(12)と、 この位相差信号に応じて発振する発振器(21)と、こ
の発振器の出力レベルに基づき位相変調波信号と再生搬
送波信号との同期状態を判定する同期判定手段(23、
24)と、 この同期判定手段の判定結果に基づき同期制御信号を生
成する同期制御信号生成手段(25〜28)と、 この同期制御信号と位相差信号にかかわる信号とを合成
した信号にかかわる信号を上記電圧制御発振器に与える
合成器(13)と を備えた位相同期復調器において、 上記発振器と上記同期判定手段との間の経路に挿入され
、この発振器の発振周波数近傍の周波数帯域を通過帯域
とするフィルタ(22) を備えたことを特徴とする位相同期復調器。
[Claims] 1. A phase comparator (11) into which a phase modulated wave signal arrives; a voltage controlled oscillator (15) that supplies a recovered carrier signal to this phase comparator; and a signal generated by the phase comparator. a carrier wave reproduction signal processing circuit (12) that generates a phase difference signal corresponding to the phase difference between the phase modulated wave signal and the reproduced carrier wave signal based on the phase difference signal; an oscillator (21) that oscillates in response to this phase difference signal; synchronization determination means (23,
24), synchronization control signal generation means (25 to 28) that generates a synchronization control signal based on the determination result of the synchronization determination means, and a signal related to a signal obtained by combining the synchronization control signal and a signal related to the phase difference signal. A phase synchronization demodulator is provided with a synthesizer (13) that provides a synthesizer (13) to the voltage controlled oscillator. A phase-locked demodulator comprising: a filter (22).
JP17419788A 1988-07-12 1988-07-12 Phase locked demodulator Expired - Lifetime JPH0724371B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17419788A JPH0724371B2 (en) 1988-07-12 1988-07-12 Phase locked demodulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17419788A JPH0724371B2 (en) 1988-07-12 1988-07-12 Phase locked demodulator

Publications (2)

Publication Number Publication Date
JPH0222904A true JPH0222904A (en) 1990-01-25
JPH0724371B2 JPH0724371B2 (en) 1995-03-15

Family

ID=15974422

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17419788A Expired - Lifetime JPH0724371B2 (en) 1988-07-12 1988-07-12 Phase locked demodulator

Country Status (1)

Country Link
JP (1) JPH0724371B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7201105B2 (en) 2003-05-01 2007-04-10 Daifuku Co., Ltd. Conveyance apparatus using movable bodies

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7201105B2 (en) 2003-05-01 2007-04-10 Daifuku Co., Ltd. Conveyance apparatus using movable bodies

Also Published As

Publication number Publication date
JPH0724371B2 (en) 1995-03-15

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