JPH0222982A - Still picture transmission equipment - Google Patents

Abstract

PURPOSE:To shorten a time from the start of transmission to the display of picture data by dividing index data with arbitrary bit size, transmitting them from a high-order bit for several number of times, and performing encoding on each division index at a reception side. CONSTITUTION:An index division transmission circuit 10 consists of an index division circuit 11 to generate three division indexes (Ij.d1-Ij.d3) by dividing the index Ij, three index memories (12a-12c) to store the division index at every division stage, and a transmission control circuit 13 to control a transmission buffer 3 and the index memories (12a-12c), respectively. Therefore, the transmission of the index data can be performed separately in three stages, and picture display at the reception side can be performed by stages. In such a way, it is possible to shorten the time until the picture at a first stage is displayed after starting the transmission of the picture to around 1/3 of an on-going time.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a still image transmission device, particularly to an improvement of a still image transmission device applying a vector quantization method in image communication such as a video conference or a video telephone. .

[Prior Art] In general, image transmission used for image communication such as video conferencing or video telephone calls involves a huge amount of image information, but due to line speed and transmission cost, etc. Compression encoding devices that reduce (compress) the amount of image information have been put into practical use.

Among these methods, the vector quantization method is known as a method for compressing the amount of information with a high degree of compression.

Hereinafter, a conventional still image transmission device will be explained based on the drawings.

FIG. 4 shows a basic block configuration of a still image transmission apparatus to which the tree search vector quantization method is applied, and FIG. 5 shows a detailed block configuration of a conventional search vector quantization section.

In FIGS. 4 and 5, the blocking unit (1) converts an image input signal (100) into A/D conversion, blocks adjacent pixels on the image one by one, and generates a dimensional vector signal for each block. This is a circuit that creates (101).

On the other hand, when vector signal patterns are arranged in this structure as shown in FIG. It consists of (21), (22), (23), and (24).゛Then, the main search circuit (21) in the −th stage is a codebook (21) that stores the vectors in the first stage of the segmentation stage.
10), (211), the vector signal (101), and the pattern vectors output one by one from the codebooks (210), (211), a distortion calculation unit (212) that performs distortion calculations as shown in the following equation. , (213) and a comparator (21) that selects a pattern vector with a small distortion value.
4) and the address signal (2100) of the next stage (second stage) codebook based on the output signal of the comparator <214).
The codebook address register (215) generates the vector signal (101) and outputs the vector signal (101) to the next (second stage) tree search circuit (220) as the codebook address signal
A latch circuit (216) that latches between the generation of
It consists of.

Vectors are stored in the food books (210) and (211), respectively, as shown in FIG. 7(a). Tree search circuit at each stage (22), (23), (24)
has the same configuration as the negative stage main search circuit (21).

Therefore, it is possible to select the vector that most closely approximates the vector signal (101) from the pattern vector group (yoooG""yfill) at the final stage shown in FIG. 6 by performing a four-stage comparison operation. The final codebook address is index data (102)
Output as .

For example, considering only brightness information, when encoding normal image information on a pixel basis, 8 bits are required per pixel. However, when one block is composed of 4×4 pixels, the 4-bit information of the address of the pattern number becomes the information of one block when the vector doji conversion as described above is performed. Therefore, 1 block (4X4
-16 pixels), it is possible to reduce information by 8x16-4-124 bits, which is a very significant effect.

The index data (102) is sent to the transmission buffer (3), stored frame by frame in the transmission buffer (3), and sent out to the communication line frame by frame.

Next, the signal flow will be explained.

First, the image input signal (100) is input to the blocking unit (1
), the signal is converted into blocks, and converted into a vector signal (101).

Then, the vector signal (101) is quantized in the main search vector quantization section (2) as follows.

First, the vector signal (
101) and the vectors yo and y stored in the codebooks (210) and (211). ,dl
is determined by the distortion calculation unit (212) as shown in the following equation.

However, Xi: the i-th component of the human vector signal X, Yl: the first component of the pattern vector Y, and the distortion value d at the comparator (214). , d, and select a vector that gives a small distortion value, and send the selection signal (103) to the codebook address register (215).
Output to. For example d.

is small, the codebook address register (21
5) Sends “Oo.

Then, the codebook address register (216) outputs "0000" as the codebook address for the next stage.

Next, in the two-stage tree search circuit (22), the codebook (2
20) and (221) respectively address “o o o
o” vector, yoo and yol are the distortion calculation unit (2
22) and (223).

Then, the distortion calculation units (222) and (223) calculate the distortion value with respect to the vector signal (101), and a vector register for the third stage is generated.

Similarly, the three-stage main search circuit (23) and the four-stage tree search circuit (24) perform distortion calculation comparisons, and the vector that most closely approximates the vector signal (101) is selected from the vector group of the fourth segmentation stage. The address of is selected and the index data (
102), it is sent to the transmission buffer (5) and temporarily stored for each frame.

Next, reception will be explained.

The decoding unit (6) receives the index data (102) from the communication line, and decodes the codebook (6) using the received index data (102) as address information.
From a), the pattern vector signal is converted into a decoded signal (106
).

At this time, the codebook (6a) of the receiving section includes the pattern vector group of the final stage (fourth stage in this example).

The decoded signal (106) is then D/A converted to generate a reproduced signal (107), which is displayed on the image display section.

[Problems to be Solved by the Invention] As explained above, in the conventional still image transmission device, the transmitter stores index data for one frame in a transmission buffer, and transmits the index data to the communication line for each frame. The receiving unit has the final stage pattern vector in its codebook, and decodes and displays the index data received via the communication line after receiving all the data for one frame. Therefore, there was a complaint from the department that it took a long time from the start of image transmission until it was displayed.

The still image transmission device according to the present invention has been made to solve the above problems, and aims to shorten the time from the start of image data transmission to display.

[Means for Solving the Problems] In a still image transmission device including a vector quantization circuit having a codebook in which pattern vector signals are arranged in a main structure, each of the index data output from the quantization circuit is transmitted to a transmitting section. Divide I into m pieces by a predetermined number of bits starting from the most significant bit, and use the dividing index (1, 1,...
・、■、 、J、dlゝ こ、d2ゝ
J, dl..., Ij, dll), and an index data division circuit that generates each division index (1, I
.

m divided index memories each storing 1 frame (n pieces) of ko・dl'j・ , 2, . . . , Ij, di, . . . , Ij, di); is provided, and the transmission control circuit sequentially transmits data from the divided index memory, that is, I
I... ■, ..., ■! 1, d
lゝ 2. di' J, dlゝ n, dl'
1°!・・・■ ・・・、■ ・
..., Id2ゝ 2. d2ゝ j, d2'
n, d2ゝ j.

dl...! . , dm, and sends the divided indexes to the communication line, and the reception unit receives the divided indexes from the communication line, displays a decoded image for each received divided index, and performs m-stage decoding. It is characterized by decoding and displaying one still image.

[Operation] As explained above, the still image transmission device according to the present invention divides index data into arbitrary bit sizes,
The configuration is such that the data is transmitted in several batches starting from the upper bit, and the receiving side performs encoding for each divided index, so the time from the start of image transmission until the first stage picture is displayed is Time can be displayed in the conventional 1/(number of division stages) time, and thereafter updated and decoded and displayed in units of 1/(number of division stages) time.

Therefore, display can be performed in stages without changing the time required until the final still image is displayed.

[Embodiment] Hereinafter, a preferred embodiment of the still image transmission device of the present invention will be described based on the drawings.

FIG. 1(A) shows the block configuration of the transmitting side according to a preferred embodiment of the still image transmission device according to the present invention, and FIG. 1(B) shows the block configuration of the receiving side. There is.

In the figures, the same parts as those of the conventional device are given the same reference numerals, and the explanation thereof will be omitted.

The features of this embodiment are an index division transmitting circuit (10) on the transmitting side and an index combining receiving circuit (20) on the receiving side.

The index division transmitting circuit (10) transmits the index! , is divided into three parts and a divided incodex (I 1. 1.) is generated.
dl', d2', d3 index division circuit (11), three index memories (12a) for storing the division index for each division stage, (
12b), (12c), the transmission buffer (3) and the index memory (12a), (12b), (12c).
), respectively.

Therefore, on the transmitting side, the index data is divided and divided indexes ("j, dl, 1.1...
) can be sent.

J・d2ゝJ,d3 Furthermore, the index synthesis receiving circuit (20) stores index memories (21a), (2l b), (21
c) and the division stages (4 stages, 8 stages,
decoding circuits (22a) and (22b) each having a codebook that stores pattern vectors corresponding to
), (22C), the reception buffer (5) and the index memory (21a), (2l b), (21c)
and a control circuit (23) that controls the decoding circuits (22a), (22b), and (22C), respectively.

Therefore, according to the index synthesis receiving circuit (20), image data can be easily decoded and displayed according to the number of division stages.

Next, the operation will be explained.

An example of regular search vector quantization in which pattern vectors are arranged in a 12-stage binary regular structure shown in FIG. 2 will be described.

The process up to the generation of index data Ij (102) is the same as the conventional one, so the explanation will be omitted.

Here, each index data Ij (102) is 12-bit information as shown in FIG. 3(A),
Each bit information is a history of the pattern vector shown in FIG. 2 of the division stage.

Next, the index data 1. (102) is input to the index division transmitting circuit (10), and is divided into 4 bits each starting from the upper bit.
1,1,I) ko, d1ゝ ko, d2ゝ
j, d3(lla), (lllb), and (111c) are generated.

Here, as shown in FIG. 3(B), the division index (Ij, d,) (111a) is bit information of up to 4 bits from the upper bit of the index data (102), and the fourth This is the address of the row pattern vector.

Also, the division index (I,, 2) (11l b
) is similarly 5 of index data Ij (102)
This is 8-bit information, and when used together with the division index (Ij, dl) (111a), it becomes the address of the eighth stage pattern vector.

Then, the division index (Ij, da) (111
C) is similarly index data 1. (102) is information from the 9th bit to the 12th bit of the division index (I I ) (111j, di
'j, d2 a), (11l b) used in combination, final stage (12th stage)
This is the address of the pattern vector.

The divided indexes are stored in the corresponding index memories (12a) and (12b) for each divided stage.
), (12c).

That is, the division index (112a) stored in the index memory (12a) is I!, where n is the total number of blocks per frame. t, dt, 22,1,... ■j, dl,...
In, dl.

Similarly, the divided index (112b) stored in the index memory (12b) is 1, d2' 2
．． d2'``'' j, d2'''' In, d2, and the divided index (112c) stored in the index memory (12c) is I SI l' Ij, ds,...! .

, da.

1, da 2. d3ゝThen, the control circuit (13) sends the data to the transmission buffer (3),
1. Separate indexes from the index memory (12a). dl" 2.dl,...■,...
III...,I.

J, di, n, dl' 1. d2ゝ 2
．． d2ゝJ.

... III ... Id2ゝ
n, d2ゝ 1. d3ゝ 2. d3ゝ
The data is read out in the order of j, d3ゝ, . . . , In, da, and a header indicating the beginning of the division stage of each division index is added.

Therefore, from the transmission buffer (3) to the communication line (4a), as shown in FIG. 3(E), 111I.
... Summer, ... ■ 2.1, dlゝ 2.
dl' J, diゝ n, diゝ■■J, d
2' n, d2' 1, d2, 2. d2,...1. ...! 3
, 1, d3' 2. d3' ”” Ij, d3'
Data “” In, da is sent.

Next, the operation at the time of reception will be explained.

First, through the communication line (4b), the division index I
I z, dl゛2. dl゛”” j, dl゛”°ゝIn, d
1 is received and temporarily stored in the reception buffer.

Then, the control circuit (23) of the index synthesis receiving circuit (2o) controls the division index I received in the index memory (21a) based on the header information.
,I...1. ...1, dl
2. I remember dlゝko, dlゝIn, dl.

Then, a fourth stage decoding of the pattern vector is performed in a decoding circuit (22a) including a codebook having the fourth stage pattern vector, and a post-processing unit (7) performs D
After /A conversion, it will be played back and displayed.

Next, divide index '1. d2.12. d2,・
...Ij, d2, ... ■. , d2 are received by the reception buffer (5), and as described above, the division index ■
1. d2, ■2. d2'"" j, d2'"" n
, d2 are stored in one index memory (2lb).

Then, the division index 11. 1, d2ゝ 2
．． d2...! , . . . , In, d2 are the division indexes II . . . , 1 . ...1, dlゝ
2. It is combined with d1ゝJ, dlゝ■□, , 1, the eighth stage pattern vector is decoded in a decoding circuit (22b), and displayed after being D/A converted.

Similarly, the division index Il, da"2.d3'・
・・■、 、・・・、■. 1 and 3 are combined with the previously received divided parakeet and d3 index, and decoding is performed in the final stage (12th stage), and a precise still image is displayed on the display unit (not shown). will be held.

As described above, according to this embodiment, index data (102) is transmitted in three stages, and images are displayed in stages on the receiving side.
It takes 1/3 of the time to display the picture of the first stage compared to the conventional method, and after that, detailed images can be updated and displayed in 1/3 hour units.

Therefore, display can be performed in stages without changing the time required until the final still image is displayed.

In the above embodiment, the index data is divided into 3 bits each with 4 bits.
Although an example of division into stages has been shown, if the index synthesis receiving circuit has a codebook from the first stage to the final stage,
The number of division bits and the number of division stages can be set arbitrarily.

Further, in the above embodiment, an example was shown in which a header indicating the beginning of the division index is added and transmitted, but if the number of block divisions is agreed upon in advance on the transmitting and receiving sides, the same effect can be achieved even without the header.

In addition, in the above embodiment, an example was shown in which binary water main search vector quantization was used, but even if the address on the codebook is index data of a pattern vector arranged in a multi-ary tree structure, the above The same effects as in the embodiment are achieved.

[Effects of the Invention] As explained above, according to the present invention, it is possible to greatly reduce the time required to reproduce the first-stage image data from the start of still image transmission, and to provide the user with an overview of the image in a short time. It has the effect of being able to convey information.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a transmitting section and a receiving section of a preferred embodiment of a still image transmission device according to the present invention, FIG. 2 is an explanatory diagram of the binary book structure of a food book, and FIG. 3 is a block diagram of a divided index. 4 is a block diagram of a conventional still image transmission device, FIG. 5 is an explanatory diagram of a conventional search vector quantization unit, and FIGS. 6 and 7 are explanatory diagrams of a codebook. In the figure, (2) is the main search vector quantization unit, (3)
is the transmission buffer, (4g), (4b) is the communication line,
(5) is a reception buffer, (6) is a decoding unit, (10) is an index division transmission circuit, (11) is an index division circuit, (12a), (12b), (12c)
is an index memory, (13) is a control circuit, (20)
is an index data synthesis receiving circuit, (21a),
(2l b), (21C) are index memories, (
22a), (22b), and (22c) are decoding circuits. In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] Read a still image signal, perform A/D conversion to generate a pixel signal, combine the pixel signals into a plurality of blocks according to a predetermined rule, and generate n blocks, one corresponding to each block j. A blocking circuit that generates a vector signal V_j; a codebook that stores a plurality of pattern vector signals arranged in a tree structure in advance; and a pattern vector that most closely approximates the vector signal V_j from the codebook for each block j. a vector quantization circuit that selects a signal and outputs index data I_j on a codebook of the selected pattern vector; and a vector quantization circuit that stores each index data I_j for one frame (n pieces), and a transmission control circuit that sends out each index data I_j to a communication line; a transmitting unit that receives each of the index data I_j from the communication line and reads a pattern vector signal corresponding to the received index data I_j from a codebook; , a decoding circuit that outputs the decoded vector signal ■_j of block j as a decoding circuit; Divide into m pieces by a predetermined number of bits starting from the upper bit, and divide into m pieces by dividing index (I_j_, _d_1, I_j
＿, _d_2, ..., I_j_, _d_i, ..., I_j_
,_d_m);
＿, _d_2, ..., I_j_, _d_i, ..., I_j_
,_d_m) for one frame (n pieces) for each division stage; ___d
_1, ..., I_j_, _d_1, ..., I_n_, _d_
1, I_1_, _d_2..., I_j, _d_2,..., I
_n_, _d_2, ..., I_j_, _d_i, ..., I_
The division indexes are read out and sent to the communication line in the order of n_, __d_m, and the reception unit receives the division indexes from the communication line, displays the decoded image while decoding each received division index, and A still image transmission device characterized by decoding and displaying one still image in stages of decoding.