JPH0222995A - Video signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a video signal processing device such as a VTR.

(Prior Art) As a recording method for VTRs currently used for broadcasting, a composite video signal is separated into a luminance signal and two color difference signals, and the luminance signal is modulated as it is and recorded on one track. There is a 1 time axis compression time division multiplexing method in which the two color difference signals are time axis compressed within one horizontal scanning line, modulated as one time axis compressed color signal, and recorded on one track in order to ensure sufficient bandwidth. . An example of this signal processing method is shown in the fourth section.
As shown in the figure.

FIG. 4(a) is a tan signal, FIG. 4(b) is a (RY) signal which is one of the color difference signals, and FIG. 4(d) is another color difference signal (B- Y) It is a signal. Figure 4(c) is 1
This is a time-axis compressed color signal, and the (RY) signal is time-axis compressed in the first half of the horizontal period that is delayed by one horizontal scanning period with respect to the luminance signal, and the (B-Y) signal is in the second half. This allows time division multiplexing. In order to restore the signal recorded and reproduced using this method into a composite video signal, it is necessary to time-axis expand the time-axis compressed color signal into two color difference signals.

As one method of time axis expansion operation, the time axis compressed color signal is converted into a digital signal by an A/D converter, the two time-divided color difference signals are written separately into two memories, and when read out, the two color difference signals at the time of writing are The time axis is expanded by reading from each memory with a clock of twice the period, and D
There is a method of performing /A conversion to obtain two color difference signals. A conventional example of this time axis expansion circuit is shown in FIG. 5, and a timing chart thereof is shown in FIG. 6 and will be described.

In FIG. 5, 1 is a time axis compressed color signal input terminal, 6 is an A/D converter, 7 and 8 are memories, 10 and 11 are counters that generate a write address to the memory, and 9 is a read address to the memory. 12 and 13 are D/A converters, 2 is a write clock input terminal, and 22 is a read clock input terminal.

The time-base compressed color signal 5 inputted from the terminal 1 is converted into a digital signal 21 by the write clock 19 in the A/D converter 6 . Of the digital signals 21 (R-
The Y) part is stored sequentially (in the input order according to the clock) in the memory 7 from address O at intervals of the write clock 19 by the write address counter 10 reset by the RY reset pulse 17, and is stored in the memory 7 sequentially (in the input order according to the clock).
The write address counter 11 reset by the B-Y reset pulse 18 also writes the memory 8 sequentially from address O at intervals of the write clock 19.
is memorized.

Next, when reading, a read reset pulse 1 is generated based on a read clock 20 with a cycle twice that of the write clock 19.
The read address counter 9 reset in step 6 sends the (RY) signal from the memory 7 and the (B -Y) signal from the memory 8.
) signals are simultaneously read out sequentially (in the order they were stored) from address O.

The timing of writing to and reading from memory will be explained with reference to FIG. A is a digitized time-base compressed color signal 5. B represents the write timing of the R-Y portion, and E
represents the writing timing to the (B-Y) portion. (
If both (RY) and (B-Y) are written sequentially between address 0 and address a, (R-Y), (
To double the B-Y) signal and read it at the same time, set the read address from O to a at the timing shown in E to read the expanded (R-Y)t (
The digital signal of B-y) can be read out at the timings of (2) and (J).

Furthermore, when recording and reproducing are performed with a VTR device, missing portions may occur in the reproduced video signal due to peeling of the magnetic layer of the video tape, impurities on the tape, and the like. Generally, the method of interpolating this missing part of the video signal is to take advantage of the fact that the video signal has a strong correlation between horizontal scanning lines, store the video signal immediately before the missing part in memory, and then store the missing part. There is a method of interpolating using a video signal. An example of this conventional circuit is shown in FIG. 7 and will be explained.

In FIG. 7, 32 is a video signal input terminal, 33 is a dropout detection circuit, 34 is an A/D converter, 35 is a digital signal switch, 36 is a memory, 37 is a D/A converter, and 38 is a video signal output It is a terminal. Video signal input terminal 3
The video signal input from 2 is sent to the dropout detection circuit 3.
3, it is detected whether or not there is a dropout, and if there is a dropout, a dropout detection signal 39 is output. On the other hand, the reproduced video signal digitized by the A/D converter 34 is input to the digital signal switch 35, and if there is no dropout detection signal, it is converted into an analog signal again by the D/A converter 37 as an output signal. In addition, the output of the digital signal switch 35 is stored in the memory 36 for each horizontal scanning period, and when a dropout occurs, the signal from the previous horizontal scanning line is outputted from the digital signal switch 35 by the dropout detection signal 39 and is lost. Interpolate parts.

(Problems to be Solved by the Invention) (1) When recording and reproducing with a VTR device, the reproduced signal contains fluctuation components in the time axis direction due to unevenness in the running speed of the tape, unevenness in the running speed of the recording and playback heads, etc. In general, as a method of correcting the time axis fluctuation, a clock synchronized with the time axis fluctuation is used for writing to the memory, and a fixed clock without time axis fluctuation is used for reading from the memory. (timebase collector).

In order to provide a time base collector function to the conventional example, a clock synchronized with the time axis fluctuation of the reproduced time axis compressed color signal is used as the write clock 19, and a clock synchronized with the time axis fluctuation of the reproduced time axis compressed color signal is used as the read clock 20. A fixed clock is used, which has one cycle twice as long but does not include time axis fluctuations. However, if the write clock and read clock are asynchronous, and the write clock lags behind the read clock, the (B-Y) signal will write near address 0, the read address will be reversed, and the part where the address was reversed will be output as 1. A signal one horizontal scanning line before the signal that is output is output. Conversely, when the write clock is faster than the read clock, the write address and read address are reversed near the end of the write address of the (RY) signal, and the data of the next horizontal period is written before reading, and the B-Y signal is written. There is a portion where data is read after one horizontal scanning line.

(2) When performing the dropout compensation shown in the conventional example, it is necessary to prepare a memory separate from the two sequential memories used in the circuit that expands the time-domain compressed color signal, which reduces the circuit size, cost, etc. disadvantageous in terms of

The present invention expands the reproduced time axis compressed color signal by one time axis using two sequential memories.

This provides a means for making time base correction and dropout compensation possible.

(Means for solving the problem) A composite video signal is separated into a luminance signal and two color difference signals, and each of the two color difference signals is divided into 17 pixels for one horizontal scanning period.
In a VTR device that compresses the time axis to 2 and stores both signals within one horizontal scanning line and records and reproduces them as a 1 time axis compressed color signal, when reproducing the time axis compressed color signal, the writing address to the memory is The period of the read address is doubled, the write address to the memory is synchronized with the time axis fluctuation of the reproduced signal, the read address is a fixed address without time axis fluctuation, and the period of two horizontal scanning periods of the reproduced signal is Furthermore, if it is necessary to interpolate the missing part of the reproduced signal due to dropout, etc., write to the memory is prohibited by the dropout detection signal, but the write address is made consecutive. This system uses two sequential memories to enable time-axis expansion, time-axis correction, and dropout compensation of the reproduced time-axis compressed color signal.

(Function) According to the above-described configuration, the present invention enables time axis expansion, time axis correction, and dropout compensation of a reproduced time axis compressed color signal with a simple configuration including two sequential memories, and provides a good reproduced signal. can be obtained.

(Embodiment) Fig. 1 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in Fig. 5 indicate the same elements, and 23 and 24 indicate data output. Forbid buffer,
25 is a dropout detection signal input terminal, 27 is a sync signal separation circuit that separates the sync signal from the reproduced signal, and 28 is a PLL circuit that generates a write clock 29 synchronized with the time axis compressed color signal 5 based on the sync signal. .

The flow of the time-base compressed color signal in this embodiment is the same as that in the conventional example shown in FIG. 5, but this embodiment is unique in how addresses are given to the memories 7 and 8. A synchronizing signal separation circuit 27 separates a synchronizing signal from the reproduced time-base compressed color signal 5, and a PLL circuit 28 generates a write clock 29 synchronized with the time-base fluctuation of the reproduced time-base compressed color signal. By sending a write clock 29 to the A/D converter 6 and the write address counters 10 and 11, writing to the memory is synchronized with the time axis fluctuations of the reproduced time axis compressed color signal 5.

On the other hand, read address counter 9 and D/A converter 12
．． 13, a read clock 20 is used, which is a fixed clock having a period twice that of the write clock 29 but does not fluctuate by one time axis. At this time, as shown in the time chart of Fig. 2, the address is given to the (RY) signal by a write reset pulse (17 in Fig. 1 and B in Fig. 2) and a write enable pulse (17 in Fig. 2). 30.2nd in Figure 1
Figure C) by (RY). O”a, (RY
) Addresses such as a+1 to 2a are given to the part □□ every two horizontal periods. Similarly, the write reset pulse for the (B-Y) signal (18 in Figure 1, E in Figure 2)
and write enable pulse (31 in Figure 1.F in Figure 2)
), the part of (B-Y) is O~a, (B-Y),
- Addresses are given to the 1 part every two horizontal periods, such as a+1 to 2a. Furthermore, by simultaneously applying (RY) and (B-Y) to the read address continuously from addresses 0 to a by read reset pulses (16 in Figure 1 and H in Figure 2), .

The (RY) and (B-Y) signals are read out at the timing shown in J. By giving an address every two horizontal periods in this way, even if writing and reading to the memory are asynchronous, if the difference between the two addresses is within 1/2 horizontal period, the writing and reading addresses will be reversed. Normal TBC operation is possible.

Furthermore, when a dropout is detected in the playback time axis compressed color signal 5, the data is written to the memory 7.8 in the buffers 23 and 24 by the dropout detection signal 26 input from the dropout detection signal input terminal 25. In addition, addresses to the memory continue to be given every two horizontal periods as shown in FIG. In this way, the signal from two horizontal periods ago remains in the portion where data writing is prohibited by the dropout detection signal, and the missing portion can be interpolated using this signal. The third figure shows how the extension occurs when dropout occurs.
As shown in the figure.

If there is a dropout in the shaded area in FIG. 3A, writing is prohibited by the dropout detection signal K, and (R-Y
). , 2, the part (RY) remains.

If we expand this signal, we get (RY)a+x, and the missing part becomes (RY)a+x.
interpolated with the signal RY).

(Effects of the Invention) According to the present invention, with a simple configuration equipped with two sequential memories, it is possible to perform time axis expansion, nine time axis corrections, and dropout compensation of reproduced time axis compressed color signals, and in terms of cost, it is possible to perform time axis correction and dropout compensation. It is advantageous in this respect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a circuit of an embodiment of the present invention;
2 and 3 are operation timing charts of an embodiment of the present invention, FIG. 4 is a diagram showing a time-base compressed color signal used in the present invention, and FIG. 5 is a diagram showing a conventional circuit. FIG. 6 is a block diagram showing an operation timing chart of the conventional example, and FIG. 7 is a block diagram showing a dropout compensation circuit of the conventional example. 6...A/D converter, 7, 8...memory, 9...
- Read address counter, to, tt...Write address counter, 12.13...D/'A converter, 27...Synchronization signal separation circuit, 28...PLL circuit, 23.24... buffer. Patent applicant: Matsushita Electric Industrial Co., Ltd. ■Kuchikuku■ From Kuchidashikutsuzuzuzuku■

Claims (1)

[Scope of Claims] A composite video signal is separated into a luminance signal and two color difference signals, and each of the two color difference signals is time-axis compressed to 1/2 for one horizontal scanning period, and both signals are compressed by one horizontal scanning period. In a VTR device that records and reproduces a time-axis compressed color signal within a scanning line, the reproduction signal processing device for the time-axis compressed color signal includes two color difference signal components obtained by A/D converting the reproduced signal. means for generating a write address synchronized with the time axis fluctuation of the reproduction signal as a write address to the sequential memory, and a means for generating a write address synchronized with the time axis fluctuation of the reproduction signal as a read address from the sequential memory; means for generating a fixed read address having a cycle twice as long as the address and having no time axis fluctuation; and a means for generating a fixed read address having a cycle twice as long as the address and having no time axis fluctuation; and further comprising means for continuously providing the address when interpolation of a missing portion of the reproduced signal due to dropout or the like, but inhibiting writing to the memory by a dropout detection signal during that time, A video signal processing device characterized by performing time-base expansion, time-base correction, and dropout compensation of a reproduced time-base compressed color signal.