JPH02230772A - Structure of MIS type semiconductor device - Google Patents
Structure of MIS type semiconductor deviceInfo
- Publication number
- JPH02230772A JPH02230772A JP1049903A JP4990389A JPH02230772A JP H02230772 A JPH02230772 A JP H02230772A JP 1049903 A JP1049903 A JP 1049903A JP 4990389 A JP4990389 A JP 4990389A JP H02230772 A JPH02230772 A JP H02230772A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor
- heat treatment
- insulating film
- semiconductor device
- impurity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
Description
【発明の詳細な説明】
[産業上の利用分野]
本発明はMIS型半導体装置の構造に関し、更に詳しく
は絶縁体と半導体の界面に誘起されたキャリアの伝導を
利用するMIS型半導体装置の構造に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of an MIS type semiconductor device, and more particularly to the structure of a MIS type semiconductor device that utilizes conduction of carriers induced at the interface between an insulator and a semiconductor. Regarding.
[従来の技術]
絶縁体と半導体の界面に誘起されたキャリアの伝導によ
って動作するMIS型半導体装置は、半導体の伝導型と
して輸送キャリアと逆か、または半絶縁性のものを用い
てノーマリオフ型とする。[Prior Art] MIS type semiconductor devices, which operate by conduction of carriers induced at the interface between an insulator and a semiconductor, have a conduction type of the semiconductor that is the opposite to that of transport carriers, or a semi-insulating type that is normally off type. do.
このため、半導体層の作製法もしくは作製条件には制限
が必要であり、例えば半導体層としてヒ化ガリウム(以
下GaAsと記V)を用いてn型MIs電界トランジス
タを製造する場合には、残留キャリア補償用の深い準位
を導入したバルク結晶や、弱いp型のエビタキシャル結
晶を使用している。このうちキャリア移動度を決める結
晶性や均一性の観点からすれば、エビタキシャル結晶の
方が望ましい。For this reason, it is necessary to limit the manufacturing method or manufacturing conditions of the semiconductor layer. For example, when manufacturing an n-type MIs field transistor using gallium arsenide (hereinafter referred to as GaAs) as the semiconductor layer, residual carriers A bulk crystal with a deep compensation level introduced or a weak p-type epitaxial crystal is used. Of these, from the viewpoint of crystallinity and uniformity that determine carrier mobility, the epitaxial crystal is more desirable.
実際のMIS型半導体装置の製造過程では、ソースおよ
びドレインのオーミツク接触をとるために上記のような
半導体基板中に高濃度ドープ領域を形成することが必要
であり、プレーナ型素子では通常イオン注入が用いられ
る。MIS系の耐熱性が充分大きい場合には前記のプロ
セスをゲート部形成後に行うことが可能でおるが、イオ
ン注入後の活性化熱処理によってMIS系の電気特性が
劣化してしまう場合には、絶縁体膜堆積前に予め高濃度
領域を形成することが必要である。後者の場合には、高
濃度領域形成工程によって半導体表面に形成ざれた劣化
層を絶縁膜堆積前に除去する必要があった。In the actual manufacturing process of MIS type semiconductor devices, it is necessary to form highly doped regions in the semiconductor substrate as described above in order to establish ohmic contact between the source and drain, and planar type devices usually require ion implantation. used. If the heat resistance of the MIS system is sufficiently high, the above process can be performed after forming the gate part, but if the electrical characteristics of the MIS system deteriorate due to activation heat treatment after ion implantation, insulation It is necessary to form a high concentration region in advance before body film deposition. In the latter case, it is necessary to remove the degraded layer formed on the semiconductor surface by the high concentration region forming process before depositing the insulating film.
[発明が解決しようとする課題]
絶縁体一半導体界面の蓄積キャリアの伝導を利用する型
のMIS型半導体装置にあいて、半導体としてGaAs
等の化合物半導体を用いた場合には、絶縁膜一半導体界
面に高濃度の欠陥準位が存在するため、表面電位の移動
範囲が制限ざれることや界面でのキャリア移動度が小さ
いことが問題となっている。[Problem to be solved by the invention] In a MIS type semiconductor device that utilizes conduction of accumulated carriers at an insulator-semiconductor interface, GaAs is used as a semiconductor.
When using compound semiconductors such as, there are problems such as a high concentration of defect levels at the insulating film-semiconductor interface, which limits the movement range of the surface potential and low carrier mobility at the interface. It becomes.
更に、この型のM I S型半導体装置では上記のよう
に半導体中の残留不純物濃度に制限があるが、一方で有
機金属気相エビタキシャル結晶を用いる場合には無添加
状態で残留キャリア濃度を低く抑えようとするとV族原
料対■族原料供給比を小さくする必要かおり、良好な表
面モホロシを{qにくいという問題点かあった。Furthermore, in this type of MIS type semiconductor device, there is a limit to the concentration of residual impurities in the semiconductor as described above, but on the other hand, when using an organometallic vapor phase epitaxial crystal, it is possible to reduce the concentration of residual carriers without adding any additives. In order to keep it low, it is necessary to reduce the supply ratio of group V raw materials to group (2) raw materials, which poses the problem of making it difficult to achieve good surface morphology.
しかも結晶性を改善しようとすると、成長温度をより高
く設定する必要があり、この場合、残留キャリア濃度が
増加する傾向にあるという問題もめった。これに対して
補償不純物を導入する方法では、残留キャリア濃度の低
減が図れるものの、キャリアの散乱中心が増え、移動度
が低下するという問題がおった。Moreover, in order to improve the crystallinity, it is necessary to set the growth temperature higher, and in this case, there is also the problem that the residual carrier concentration tends to increase. On the other hand, although the method of introducing compensation impurities can reduce the residual carrier concentration, there is a problem in that the number of carrier scattering centers increases and the mobility decreases.
また従来技術で述べた事情によってプロセス中に生じた
劣化層を化学エッチングによって除去する場合には、除
去可能な半導体層厚さに元々制限がある上に、エッチン
グ後の半導体表面の処理状態を制御しきれないという問
題があった。Furthermore, when removing a deteriorated layer generated during the process by chemical etching due to the circumstances described in the conventional technology, there is an inherent limit to the thickness of the semiconductor layer that can be removed, and the processing state of the semiconductor surface after etching is controlled. There was a problem that I couldn't do it.
本発明は、以上述べたような従来の問題点を解決するた
めになされたもので、実効移動度が高く、特性の向上し
た半導体装置の構造を提供することを目的とする。The present invention has been made to solve the conventional problems as described above, and an object of the present invention is to provide a structure of a semiconductor device with high effective mobility and improved characteristics.
[課題を解決するための手段]
本発明は、半導体上に絶縁膜が形成ざれたMIS型半導
体装置の構造において、絶縁膜下の半導体表面近傍の不
純物原子および欠陥単位が原子状水素の導入により電気
的に不活性化されてなることを特徴とするMIS型半導
体装置の構造である。[Means for Solving the Problems] The present invention provides an MIS type semiconductor device structure in which an insulating film is formed on a semiconductor, in which impurity atoms and defect units near the semiconductor surface under the insulating film are reduced by the introduction of atomic hydrogen. This is a structure of a MIS type semiconductor device characterized by being electrically inactivated.
本発明にあいて、絶縁膜を表面に形成ざれた半導体層は
、無添加の液体封止引き上げ法等によって成長したバル
ク結晶でもよいし、あるいは無添加の気相エビタキシャ
ル成長法によってハルク結晶上に成長したエビタキシャ
ル成長結晶であってもよい。In the present invention, the semiconductor layer on which the insulating film is formed may be a bulk crystal grown by an additive-free liquid confinement pulling method, or a hulk crystal grown by an additive-free vapor phase epitaxial growth method. It may also be an epitaxially grown crystal grown.
特に、エビタキシャル成長結晶を用いた場合には、残留
不純物をチャネル領域で不活性化することが可能となる
ため、従来のように故意の補償不純物添加や成長温度お
よびV族原料対■族原料供給比に対する制限が不用とな
り、結晶性の観点のみで最適化した成長条件を選ぶこと
かできる。In particular, when an epitaxially grown crystal is used, it is possible to inactivate residual impurities in the channel region, so it is possible to inactivate residual impurities in the channel region. There is no need to limit the supply ratio, and growth conditions optimized only from the viewpoint of crystallinity can be selected.
[作用1
本発明は、半導体中に導入された原子状水素が欠陥や不
純物を電気的に不活性化する現象を利用したものである
。欠陥や不純物が電気的に不活性化されると、絶縁体一
半導体界面の実質上の残留欠陥濃度や残留不純物濃度が
減少し、良好な界面特性が得られるようになる。そのた
め、例えばGaAS系のMIS型装置においても、表面
電位のピンニングやキャリア移動度の点で装置特性の改
善を行うことができる。[Operation 1] The present invention utilizes the phenomenon that atomic hydrogen introduced into a semiconductor electrically inactivates defects and impurities. When defects and impurities are electrically inactivated, the substantial residual defect concentration and residual impurity concentration at the insulator-semiconductor interface are reduced, and good interface characteristics can be obtained. Therefore, even in a GaAS-based MIS type device, for example, device characteristics can be improved in terms of surface potential pinning and carrier mobility.
[実施例1 以下、本発明の実施例について説明する。[Example 1 Examples of the present invention will be described below.
第1の実施例ではGaAS基板を用い、絶縁膜として窒
化アルミニウムく△IN)をトリメチルアルミニウムー
ヒドラジン系原料により堆積してMIS型電界効果トラ
ンジスタ(MISFET>を作製する例について述べる
。In the first embodiment, an example will be described in which a GaAS substrate is used and an MIS type field effect transistor (MISFET) is manufactured by depositing aluminum nitride (ΔIN) as an insulating film using a trimethylaluminum-hydrazine-based raw material.
液体封止引き上げ法によって成長したバルクの無添加半
絶縁性GaASに、まずソースおよびトレインとなる領
域をフォトレジストによってパタニングし、n型不純物
となるシリコン(S i )イオンをエネルギー100
keV、ドーズ置2X1014cm−2の条件で注入
した後、フォトレジストを剥離した。熱処理保護膜とし
てAI!Nを1000人堆積し、活性化熱処理を950
゜C,20分の条件で行った後、保護膜を剥離した。次
にゲート絶縁膜用△NNを80OA堆積し、Pdを背圧
1×1叶7Torrの真空下で抵抗加熱法により500
0 A蒸着した後、パターニングを行ってゲート部とし
た。First, regions that will become sources and trains are patterned using photoresist on bulk doped-free semi-insulating GaAS grown by the liquid-sealed pulling method, and silicon (S i ) ions, which will become n-type impurities, are exposed to energy 100.
After implantation under the conditions of keV and dose setting of 2×10 14 cm −2 , the photoresist was peeled off. AI as a heat treatment protective film! Deposit N for 1000 hours and perform activation heat treatment for 950 hours.
After the test was carried out at ℃ for 20 minutes, the protective film was peeled off. Next, 80 OA of ΔNN for the gate insulating film was deposited, and 500 OA of Pd was deposited using the resistance heating method under a vacuum with a back pressure of 1×1 and 7 Torr.
After 0 A vapor deposition, patterning was performed to form a gate portion.
次いで、水素原子を導入するために水素気流中で270
゜C、3時間熱処理した。最後にソースとトレイン領域
の電極として金ゲルマニウムニッケル(AuGeN i
)をリフトオフ法を用いて形成し、MISFETとし
た。Then, in order to introduce hydrogen atoms, 270
Heat treatment was performed at °C for 3 hours. Finally, gold germanium nickel (AuGeNi) is used as the source and train region electrodes.
) was formed using a lift-off method to form a MISFET.
本実施例で作製したMISFETは電子蓄積型の動作を
示し、得られた素子の電流飽和領域における実効移動度
は室温で2400 cm2 V−1 sec−1であり
、水素原子による不活性化を行わない場合に比べて20
%の移動度改善がみられた。The MISFET fabricated in this example exhibited electron storage type operation, and the effective mobility of the obtained device in the current saturation region was 2400 cm2 V-1 sec-1 at room temperature, and the device was inactivated by hydrogen atoms. 20 compared to without
% mobility improvement was observed.
第2の実施例では、第1の実施例の半導体をバルク半絶
縁性GaASに代えて、その上に有機金属を原料とした
気相成長法(MOCVD法)で成長したエビタキシャル
GaAsに置き換えた。この際、成長温度は750’C
, V/III比を150として2000人の結晶成長
を行ったJこの後、第1の実施例と同一の工程によりM
ISFETを作製した。In the second example, the semiconductor of the first example was replaced with bulk semi-insulating GaAS, and was replaced with epitaxial GaAs grown on it by a chemical vapor deposition method (MOCVD method) using an organic metal as a raw material. . At this time, the growth temperature was 750'C.
, 2000 crystals were grown with a V/III ratio of 150. After this, M was grown using the same process as in the first example.
An ISFET was fabricated.
水素原子の導入を行わなかった場合には、チャネル領域
の半導体層がn型の導電性を持つためノマリーオン型と
なってしまい、空乏層変調型の素子となった。これに対
して、水素原子の導入を行った場合には、第1の実施例
と同様の電子蓄積動作を示し、しかもチャネル部分の半
導体層をエビタキシャル成長層としたことによって、第
1の実施例と比較して実効移動度が増加し、2500c
m2 V−1 sec−1が得られた。この結果は従
来法で作製した最も実効移動度の高いMISFETに比
べて10%以上高い値でおる。If hydrogen atoms were not introduced, the semiconductor layer in the channel region had n-type conductivity, resulting in a normally-on type device, resulting in a depletion layer modulation type device. On the other hand, when hydrogen atoms are introduced, the electron accumulation operation is similar to that of the first embodiment, and by using the semiconductor layer in the channel portion as an epitaxial growth layer, the first embodiment The effective mobility increases compared to the example, 2500c
m2 V-1 sec-1 was obtained. This result is more than 10% higher than the MISFET with the highest effective mobility produced by the conventional method.
なお、以上の実施例では半導体としてGaASを用いた
が、真性キャリア濃度が実用上許容ざれる程度に低く、
しかも水素原子による不純物不活性化の生じる半導体で
あれば、これ以外の材料を用いてもよい。またゲート絶
縁体としては、ここで使用したA2N以外の材料を用い
てもよい。Note that although GaAS was used as the semiconductor in the above embodiments, the intrinsic carrier concentration was low to a practically unacceptable level;
Moreover, other materials may be used as long as they are semiconductors in which impurity inactivation by hydrogen atoms occurs. Further, as the gate insulator, a material other than A2N used here may be used.
[発明の効果]
以上説明したように、本発明によれば実効移動度が高く
、特性の改善ざれたMIS型半導体装置の構造が得られ
る。[Effects of the Invention] As described above, according to the present invention, a structure of a MIS type semiconductor device with high effective mobility and improved characteristics can be obtained.
Claims (1)
置の構造において、絶縁膜下の半導体表面近傍の不純物
原子および欠陥準位が原子状水素の導入により電気的に
不活性化されてなることを特徴とするMIS型半導体装
置の構造。(1) In the structure of a MIS type semiconductor device in which an insulating film is formed on a semiconductor, impurity atoms and defect levels near the semiconductor surface under the insulating film are electrically inactivated by the introduction of atomic hydrogen. A structure of a MIS type semiconductor device characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1049903A JPH02230772A (en) | 1989-03-03 | 1989-03-03 | Structure of MIS type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1049903A JPH02230772A (en) | 1989-03-03 | 1989-03-03 | Structure of MIS type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02230772A true JPH02230772A (en) | 1990-09-13 |
Family
ID=12843975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1049903A Pending JPH02230772A (en) | 1989-03-03 | 1989-03-03 | Structure of MIS type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02230772A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2723981C1 (en) * | 2019-08-06 | 2020-06-18 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Semiconductor device manufacturing method |
-
1989
- 1989-03-03 JP JP1049903A patent/JPH02230772A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2723981C1 (en) * | 2019-08-06 | 2020-06-18 | Федеральное государственное бюджетное образовательное учреждение высшего образования "Кабардино-Балкарский государственный университет им. Х.М. Бербекова" (КБГУ) | Semiconductor device manufacturing method |
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