JPH02230779A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to ultra-high performance electronic devices that combine superconducting electrodes and semiconductors, and particularly to high-performance transistors that have both the advantages of bipolar transistors and superconducting field effect transistors.

[Conventional technology 1] Conventionally, high-performance transistors combining superconductors and semiconductors have been developed by T.D.C. Clark et al. in Journal of Applied Physics 5.
Volume 1, page 2736 (Journal of Applied
Physics, vol. 51, p. 2736,
1980) is known. In this transistor, a superconducting electrode is formed in contact with the source and drain regions of an insulated gate or Schottky junction field effect transistor, and the current flowing between the source and drain is controlled by gate voltage. . Regarding the operating principle of this field-effect superconducting transistor, see, for example, ``Quantum Mechanics and New Technology'' (Baifukan,
1987), as described in detail in Chapter 3, a pair of Coopers intrudes from the superconducting electrodes of the source and drain into the channel region via the source/train region of the semiconductor due to the "superconducting proximity effect". If the carrier density in the channel region is changed by a gate voltage that allows a current to flow with a resistor O between them, this superconducting current also changes, making it possible to operate as a transistor. It has the ability to flow drain current without applying voltage between the source and drain, a feature not found in conventional semiconductor field-effect transistors, making it possible to create high-speed, low-power digital circuits. It is extremely suitable for Problem 1 to be Solved by the Invention The conventional field effect superconducting transistor described above has a problem in that when it is attempted to be used in actual circuit operation, the threshold voltage variation is too large to allow normal operation. In field effect transistors with a gate length of 1 μm or less, the threshold voltage strongly depends on the gate length due to a two-dimensional effect called the short channel effect. This is discussed, for example, in the Physics of Semiconductor Devices 2nd Edition by S.M.Sze.
cs of Se + ai conductor Devi
ces, SECONDEDITION, 1981)
It is discussed in detail on pages 474 to 477. Therefore,
Due to slight variations in gate processing dimensions, the threshold voltage of a transistor can easily vary by about 100 mV. This threshold variation remains the same even in superconducting transistors. Since a typical semiconductor digital circuit operates with a logic amplitude of several volts, the influence of the above-mentioned threshold variation on circuit operation is relatively small. On the other hand, in a circuit using superconducting transistors, the logic amplitude needs to be on the order of mV to several tens of mV, and this threshold fluctuation makes it impossible for the circuit to operate normally. The reason why the logic amplitude in a superconducting transistor must be on the order of mV to several tens of mV will be explained below. In order for a superconducting transistor to have a significant difference from a transistor that uses a normal conduction mechanism using semiconductors (hereinafter referred to as normal conduction), a superconducting current mechanism is required. must be larger than the normal conduction current IN. Let's find the conditions for this below. The normal conduction current IN is expressed by the following equation according to Ohm's law. IN ” Vsn/RH (1) Here. VS
O is the voltage between the source and drain, and RN is the resistance between the source and drain when there is no superconducting electrode. Superconducting current I, as used in Clark's article above. and RN
The following relational expression roughly holds true between them. IaRN-47CΔ/ (2q) (2) Here, Δ is the gap energy of the superconducting electrode, and 9 is the amount of charge of the electron. By eliminating RN from (1) and (2), we obtain the following equation. I, /IN- 2πΔ/ (qVsn) I, /IN-
6.3Δ/ (qvmo) From now on, in order to make the superconducting current sufficiently larger than the normal current, that is, ■. >> It can be seen that for , it is necessary that VSO ~ Δ/q. Therefore, it is necessary to set the voltage between the drain and source to about the gap voltage Δ/9 of the superconducting electrode. From this, it is necessary to make the logic amplitude in the digital circuit approximately equal to the gap voltage Δ/q. Since the gap voltage Δ/9 of a superconductor is on the order of mV to several tens of mV (for example, 1.2 mV for lead PB, 1.2 mV for niobium N
The logic amplitude is required to be on the order of mV to several tens of mV. Therefore, it is clear that the circuit cannot operate normally due to the above-mentioned variations in threshold voltage. Another problem with conventional field-effect superconducting transistors is that their amplification factors are extremely small. As described above, in a circuit using a field effect type superconducting transistor, the logic amplitude needs to be on the order of mV to several tens of mV. However, in field effect transistors,
Even when such a small signal is applied as an input to the gate electrode, the number of carriers in the channel changes very little. Therefore, the change in drain current becomes extremely small.An object of the present invention is to provide a superconducting transistor that has small variations in threshold value and a large amplification factor, so that it can operate at high performance. . [Means for Solving the Problems 1] In order to achieve the above object, the present invention provides an active method in which carriers of the opposite conductivity type exist at the same location on the path of the main current, the density of which is higher than that of the carriers carrying the main current. contacting superconducting electrodes to the emitter and collector regions of a transistor having regions, i.e., a bipolar transistor;
It consists of a superconducting transistor. Furthermore, since the superconducting transistor can conduct current with a resistance of O, the distance between the superconducting electrodes is set to be less than or equal to the coherence length of the superconductor. Furthermore, the forbidden band width of the emitter semiconductor is made larger than that of the base semiconductor so that the piebola transistor can operate normally with a high current gain even at low temperatures where a superconducting state occurs. Furthermore, the recombination current is small even at low temperatures, and in order to use a homojunction as a semiconductor material, the impurity concentration in the base is made higher than that in the emitter. Furthermore, in order to reduce the base resistance to O, the superconducting electrode that controls the potential of the base semiconductor region is structured to be in direct contact with the base semiconductor region. Furthermore, in order to simplify the manufacturing process and create a structure suitable for high integration, the direction in which current flows is parallel to the semiconductor substrate. Furthermore, since the proximity effect from the superconducting electrode to the semiconductor works effectively even at low temperatures, the semiconductor region in the current path of the bibolar superconducting transistor is made of a degenerate semiconductor. Furthermore, in order to ensure that the current path of the bipolar superconducting transistor passes over a short distance between the emitter and collector, a lightly doped base region is provided in the other region. In order to realize high-speed logic circuits with even lower power consumption, np
An n bipolar superconducting transistor and a pnp bipolar superconducting transistor are fabricated on the same substrate. In addition, in order to enable operation at relatively high temperatures and realize a vertical bipolar transistor using epitaxial growth, we used an oxide superconductor containing Cu as the superconductor, and oxidized the oxide superconductor. Alternatively, the bipolar transistor of the present invention is formed in a reduced semiconductor region. [Effect 1] In a bipolar transistor, when a superconducting electrode is connected to the emitter and collector semiconductor regions, a pair of Coopers invades the base region via the emitter and collector regions. It's coming. By changing the voltage between the base and emitter, the number of minority carriers (the number of electrons in the case of an npn bipolar transistor) in the base can be changed, and therefore transistor operation using superconducting current becomes possible. Since a superconducting current flows between the emitter and collector due to the pair of Coopers, current can flow even if the voltage between the emitter and collector is zero. The variation in the threshold voltage at which the collector current begins to flow in bipolar transistors is extremely small compared to field effect transistors, and becomes even smaller especially when operated at low temperatures. This is because, in a bipolar transistor, a high density of holes exists in the base region, which is the active region, so that the potential of the base is hardly affected by the collector voltage due to the shielding effect. The threshold voltage variation of a bipolar transistor is expressed by the following equation, as described in "Ultra High Speed Bibolar Device" (Baifukan, 1985), p. 54. ΔVsg = - (kT/q) (ΔAg/Ag) (
2) Here, Δvag is the change in threshold, k is Boltzmann's constant, T is the absolute temperature, q is the amount of electron charge, Δtrans is the change in emitter area, and 80 is the emitter area. If the temperature is 4.2K and the emitter area variation ΔAg/Ag is 10%, ΔVBE is 0.036mV.
becomes. This is three orders of magnitude smaller than the threshold voltage variation of field effect transistors, which is 100+nV. Furthermore, since it is sufficiently small compared to the gap voltage of a superconducting electrode (mV to several tens of mV), normal circuit operation is possible even with a minute logic amplitude on the order of mV. Furthermore, as is well known, the voltage amplification factor of a bipolar transistor is much larger than that of a field effect transistor, so that the collector current can be changed significantly even with a minute voltage on the order of mV. especially,
When operated at low temperatures, this voltage amplification factor becomes extremely large. This is because transconductance g0, which is a measure of voltage amplification, is expressed by the following equation and is inversely proportional to absolute temperature. g yoni 9 ■. /(kT) Here■. is the collector current. Therefore, the temperature is 4
．． At 2K, the transconductance when 100 μA flows as a collector current is 3.63 (Siemens). This value is more than two orders of magnitude larger considering that the transconductance of a field effect transistor is about 10 mS at a gate width of 10 μm (even at the highest value announced so far). Therefore,
A large change in output current can be obtained even with input of a minute voltage on the order of mV. In this way, the problems of conventional field-effect superconducting transistors can be solved by connecting superconducting electrodes to the emitter and collector of bipolar transistors, but it is possible to solve the problems of conventional field-effect superconducting transistors by connecting superconducting electrodes to the emitter and collector of bipolar transistors. The inventor's studies have revealed that, when the present invention is applied to bipolar transistors, there is a problem in that the current gain becomes extremely small at low temperatures. The current gain hPE of the bipolar transistor is expressed by the following equation if the recombination current is sufficiently small. h FE tie- exp {(Eag-Ec+a)/
(kT)) (3) Here, EQE is the forbidden band width of the emitter semiconductor region, and EQg is the forbidden band width of the base semiconductor region. In a normal bipolar transistor using a homojunction, the emitter region is formed with a higher concentration than the base region. S.M.S z e
Physics of Semiconductor Devices, 2nd edition, written by )
ductorDevices, SECOND EDI
TION (1981), pages 143 to 144, in highly concentrated semiconductors, the forbidden band becomes slightly smaller due to the forbidden band reduction effect. In a homojunction bipolar transistor, the forbidden band width at the emitter is smaller than that at the base, and therefore, according to equation (3), the current gain becomes smaller at low temperatures. Even if a superconducting electrode is connected to the emitter/collector, the current gain similarly decreases, so in order to obtain a large current gain at low temperatures, the forbidden band width of the emitter semiconductor region must be equal to the forbidden band width of the base semiconductor region. It needs to be relatively large. To this end, a beta junction may be used in which the emitter and base are made of different semiconductor materials that satisfy this condition. Alternatively, Extended Abstracts of the Twenties. Conference on Solid State Devices and Materials, 1988 (Extended Abstra
ctsof the 20th Conference
nce on Solid StateDevi
ces and Materials, 1988) 61
As discussed by the inventors on page 7,
By making the impurity concentration in the base active region higher than the impurity concentration in the emitter region, and making the concentration in the base active region high enough to produce a band gap reduction effect, it is possible to use a homojunction (junction made of the same material). , a large current gain can be obtained at low temperatures. If this structure is applied to a bipolar superconducting transistor, the manufacturing process can be simplified, and since it is a homojunction, the recombination current between the emitter and base can be reduced. Further, by directly connecting a superconducting electrode to the base semiconductor region, a pair of Coopers penetrates from the base superconducting electrode into the base semiconductor region. As a result, the majority carriers (holes in the case of an npn bipolar transistor) in the base also become a pair of Coopers, making it possible to extremely reduce the base resistance. The manufacturing process is simplified by making the structure described above horizontal, that is, a structure in which the direction of current flow is parallel to the substrate surface. In this case, a lateral bipolar transistor may be formed on the semiconductor surface, and superconducting electrodes may be formed on the surface of its emitter and collector regions. Furthermore, in order for the proximity effect from the superconducting electrode to the semiconductor region to work effectively, the semiconductor region must contain a sufficient number of carriers even when operated at low temperatures. For this purpose, it is desirable to use a degenerate semiconductor in which the Fermi level falls into the valence band or conduction band. Furthermore, in a lateral bipolar transistor, high-speed performance deteriorates due to a current component flowing inside the substrate from the bottom of the emitter and reaching the collector. This is because the current component due to such a current path has a longer distance than the current flowing over a shorter distance, so it effectively acts as if the base width has become longer. In order to prevent this, a barrier layer may be provided on the bottom surface of the emitter. In the case of an npn bipolar superconducting transistor, the bottom of the emitter has a lower concentration of p than the intrinsic base.
By providing a mold layer, it can be used as a barrier layer. This is because the forbidden band is small in a region with high impurity concentration. Therefore, a region with a low impurity concentration has a relatively large forbidden band, which makes it difficult for electron injection to occur. If you create an npn bipolar superconducting transistor and a pnp bipolar superconducting transistor on the same substrate,
A circuit configuration similar to a CMOS circuit using insulated gate FETs is possible, and a high-speed logic circuit with low power consumption can be realized. Furthermore, if an oxide superconductor containing Cu is used as a superconductor and a semiconductor region obtained by oxidizing or reducing the oxide superconductor is used in the bipolar transistor of the present invention, the critical temperature of this superconductor is high. It has the advantage of being able to operate at relatively high temperatures, and because the lattice constants are almost the same, it is easy to form vertical bipolar transistors using epitaxial growth. [Embodiment] An embodiment of the present invention will be described below with reference to FIG. 1st
The figure shows a high-performance superconducting transformer according to the present invention? 1 shows a cross-sectional view of a complementary device using a star. 1 is a p-type silicon substrate, 2 is an SiO2 region for isolation between elements, and 3 is an n-type well region. NPN bibolar superconducting transistor 1 in the surface area of the substrate
3 and a pnp bipolar type superconducting transistor 23 are formed. npn bibolar superconducting transistor 1
3 is a p-type low impurity concentration base region 4, a low impurity concentration n
type emitter region 5, high impurity concentration n-type emitter region 6,
Emitter superconducting electrode 7, high impurity concentration p-type base region 8
, a low impurity concentration n-type collector region 9, a high impurity concentration n-type collector region 10. It consists of a collector superconducting electrode 11 and a highly impurity-concentrated p-type polycrystalline silicon external base region 12. The pnp bipolar superconducting transistor 23 includes an n-type low impurity concentration base region 14 , a low impurity concentration p-type emitter region 15 , a high impurity concentration p-type emitter region 16 , an emitter superconducting electrode 17 , and a high impurity concentration n-type base region 18 ,
It consists of a low impurity concentration n-type collector region 19, a high impurity concentration n-type collector region 20, a collector superconducting electrode 21, and a high impurity concentration p-type polycrystalline silicon external base region 22. N-type and p-type impurities include B, As, P, Sb, a
Known impurities such as a can be used. It is particularly suitable to use sb as the n-type impurity because it has a shallow impurity level (approximately 39 meV) and is less susceptible to the effects of carrier freezing. As specific concentration values, in the case of this embodiment using silicon as the semiconductor, the low impurity concentration base regions 4, 1
4 has a concentration of about IX1017/m3, low impurity concentration emitter regions 5 and 15 have a concentration of about 1XIQLs/-3, and high impurity concentration emitter regions 6 and 16 have a concentration of IX1017/m3.
High impurity concentration base region 8 with a concentration of about 0”/cs3
, 18 have a concentration of about 5×1019/an3, and the high impurity concentration polycrystalline silicon external base regions 12 and 22 have I
The concentration of the low impurity concentration collector regions 9 and 19 is about 1 x 1 019/13, and the high impurity concentration collector region 10.20 is I x 1.
The concentration should be approximately 0"/aa'. However, depending on the purpose of use and conditions of use, the concentration may be optimized within the range of 1/10 to 10 times this concentration value. Superconducting electrode As for 7, 11, 17, and 21, any superconducting material can be used in principle, and it goes without saying that materials should be selected depending on the purpose of use.For example, Nb is used here. Nb has a high melting point and is easily compatible with the silicon process.The manufacturing process can be simplified.Other superconductors such as pb and p
alloys of b and intermetallic compounds of Nb, such as NbN, Nb,
It goes without saying that an oxide superconductor such as Ge*N b3A 1 + N b3 S 1 or further containing Cu may be used. Next, we will explain the operation of this bibolar superconducting transistor in np
This will be explained using the n-bibolar type superconducting transistor 13 as an example. First, a case where the voltage between the collector and emitter is 0 will be explained. A pair of Coopers enters the high impurity concentration emitter region 6 and the low impurity concentration emitter region 5 from the emitter superconducting electrode 7 due to the superconducting proximity effect. The proximity effect is described in detail in Chapter 3 of ``Quantum Mechanics and New Technology'' (Baifukan, 1987). Similarly, high impurity concentration collector region 10 and low impurity concentration collector region 9
A pair of Coopers enters from the collector superconducting electrode 11 due to the superconducting proximity effect. However, when the base-emitter voltage VBE is O. A potential pariah in the base region 8 prevents the emitter pair of coopers from reaching the collector. This can be easily understood from the band diagram shown in FIG. 4(A). When a voltage is applied between the emitter and base, as shown in Figure 4(B). The potential barrier of the base region 8 is lowered, and electrons, which are minority carriers, are induced in the base, and these also form a pair of Coopers due to the proximity effect. Therefore, a pair of Cooper current paths is formed between the emitter and the collector, allowing a superconducting current with a resistance of O to flow. Since this superconducting current can be controlled by the potential of the base electrode, transistor operation using superconducting current becomes possible. At this time, it goes without saying that a large number of holes, which are majority carriers, exist in the base. Next, the case where a voltage is applied between the collector and emitter will be explained using Fig. 5. When the base-emitter voltage is 0, no current flows between the collector and emitter due to the barrier effect of the base region 8, as shown in FIG. 5(A). The case where a base-emitter voltage is applied will be explained using FIGS. 5(B) and 5(C). The number of electrons at the collector end 44 of the base is expressed by the following equation. nac=A'eXP((lVBc/kT)=A-exp
[:q(Vsg-Vcg)/kT]=^・exp(qV
gg/kT) ・exp(-qVcg/kT) where A
is a proportionality constant, 9 is an electron charge amount, VBC is a base-collector voltage, VCfE is a collector-emitter voltage, VBE is a base-emitter voltage, k is a Boltzmann constant, and T is an absolute temperature. When VCE is gradually increased from 0, +nBc suddenly decreases exponentially until it reaches volK)kT/9. This becomes extremely small compared to the case where Vo8=O. At this time, the concentration of the Cooper pair at the collector end of the base also decreases rapidly, and the superconducting current becomes extremely small. In this case, since a current due to normal conduction carriers flows, this current due to normal conduction becomes dominant. The current due to normal conduction shows the voltage-current characteristics of a normal bipolar transistor. Based on the above, the current-voltage characteristics of an npn superconducting bipolar transistor are shown in FIG. Superconducting current component 45
(A), (
There are three cases shown in B) (C:). The same figure (A) is
This is the case when the superconducting current is larger than the superconducting current, and (
B) is (C
) is the case where the superconducting current is larger than the normal current. In either case, the transistor has a feature not found in conventional bipolar transistors in that a collector current can flow even if the emitter-collector voltage (1) is O. especially,
The characteristics shown in FIG. 3B show ideal characteristics as a three-terminal switch element, with an extremely large output impedance and an on-resistance of 0. Which of these cases applies to the actual device depends on the type of superconducting electrodes 7 and 11,
Emitter-base-collector semiconductors 6, 5, 8, 9.
It is determined by the type and concentration of 10, the distance between the emitter and collector superconducting electrodes, the operating temperature, etc., and can be designed according to the purpose of use. Further, by directly connecting a superconducting electrode to the base semiconductor region, a pair of Coopers penetrates from the base superconducting electrode into the base semiconductor region. As a result, the majority carriers (holes in the case of an npn bipolar transistor) in the base also form a pair of Coopers, making it possible to extremely reduce the base resistance. The manufacturing process is simplified by making the structure described above horizontal, that is, a structure in which the direction in which the current flows is parallel to the substrate surface. In this case, a lateral bipolar transistor may be formed on the semiconductor surface, and superconducting electrodes may be formed on the surface of its emitter and collector regions. Furthermore, in order for the proximity effect from the superconducting electrode to the semiconductor region to work effectively, the semiconductor region must contain a sufficient number of carriers even when operated at low temperatures. For this purpose, it is desirable to use a degenerate semiconductor in which the Fermi level enters the valence band or conduction band. Note that in this example, the current gain, that is, the current gain, even at low temperatures. /IB (I. is the collector current, TB is the base current), the concentration of the base 8 is set high enough to produce the forbidden band reduction effect, and the concentration of the emitter 5 is set higher than the concentration of the base 8. The concentration is low. Such a concentration profile has been published as a "pseudo-hetero bipolar transistor" in Extended Abstracts of the Twenty-Three Conference on Solid State Devices and Materials, 1
988 (Extended Abstracts o
f the 20th Conference on
Solid State Devices and M
Materials, 1988), page 617, discussed by the inventors. The current gain h2 of a bipolar transistor is expressed by the following equation if the recombination current is sufficiently small. hFg cx< eXP((Eag-Eaa)/(kT
)) (3) Here, [EaE is the forbidden band width of the emitter semiconductor region, and Eaa is the forbidden band width of the base semiconductor region. In a normal bipolar transistor using a homojunction, the emitter region is formed with a higher concentration than the base region. Physics of Semiconductor Devices by S.M.S.
2nd edition (Physics of Semiconductor
ctorDevices, SECOND EDITI
ON, 1981), pages 143 to 144, in highly concentrated semiconductors, the forbidden band becomes slightly smaller due to the forbidden band reduction effect. In a homojunction bipolar transistor, the forbidden band width at the emitter is smaller than that at the base, and therefore, according to equation (3), the current gain becomes smaller at low temperatures. In a superconducting transistor, the current gain similarly decreases. In order to obtain a large current gain at low temperatures, the forbidden band width of the emitter semiconductor region must be larger than that of the base semiconductor region. In the structure of this embodiment, since the forbidden band of the low concentration emitter 5 is larger than the forbidden band of the high concentration base 8, electrons are easily injected from the emitter to the base, and holes are difficult to be injected back from the base to the emitter. In other words, the injection efficiency is high. The inventors have discovered that this structure can provide a sufficiently large current gain even in bipolar superconducting transistors. Specifically, when silicon is used as the semiconductor, the high concentration emitter 6 is 5×10”/■
3 or higher concentration, low concentration emitter 5 is I x 1 0''/
Concentration of cxa', high concentration base 8 is 5 x 1 0
The concentration may be approximately ``/C!I1'. With this structure, the manufacturing process can be simplified, and since it is a homojunction, the recombination current between the emitter and base can be reduced. In a lateral bipolar transistor such as
It is necessary to prevent electrons from being injected downward from the bottom of the low concentration emitter 5. This is because, as shown in Figure 7, electrons injected downward have a long distance to reach the collector, so their operating speed is slower than when they flow over a short distance on the semiconductor surface. . In this example, in order to prevent injection at this bottom part, the temperature is low. A degree base area 4 is provided. The effect of this low concentration p-type region is due to the following effect newly discovered by the inventors. As shown in FIG. 8, consider the case where an n-type semiconductor forms a junction with p-type semiconductor regions P1+P2 having two different concentrations. When a forward voltage is applied to this junction, electrons are injected from the n-type region to the p-type region. The current due to these electrons is expressed by the following equation. I1:A1"(kT/q)" (μe ntn"
/Pat We1)・exp(ΔEgb■/kT)・
exp(qV/kT) Iz=A*{kT/q){μe nto”/PB2WB
x)・exp(ΔEgb2/kT)・exp(qV/
kT). Here, I,,I, is the current of electrons injected into P1+92, A1 and A2 are the areas of P1+p2, respectively, k is Boltzmann's constant, T is the absolute temperature, and 9 is the amount of electron charge, μ. is the electron mobility in the p-type region, nia is the intrinsic carrier density in the absence of the forbidden band reduction effect, and pi. P
z is the hole density in the region pi, P2, W1, W, is the depth of the P1+P2 region, ΔEll tΔE is P1t
The forbidden band reduction amount at P2, ■ is the applied voltage. Therefore, the following formula holds. I, /I, = (A, /A.)・(pWt/P2wz
)・eXp{(ΔEl!.−ΔEg1)/kT }
(4) One way to make the current of p2 smaller than that of 21 is to reduce the area ratio, but it is also important to reduce the second and third factors on the right side. At room temperature, the factor of the exponential function is small, so the second
factor becomes dominant. Therefore, in order to make the current of p1 smaller than that of p2, it is necessary to set fh Wx < P2 Wz. That is, the impurity concentration of p2 should be made sufficiently higher than 21. On the other hand, at low temperatures such as liquid nitrogen temperature, the exponential function factor on the right side of equation (4) becomes dominant. In order to reduce the current of p2, it is necessary to set ΔEgz < 8Egt, and considering that the forbidden band reduction is a monotonically increasing function of impurity concentration, it is necessary to set P2 < 21. That is, it is necessary to keep the concentration of p2 lower than p1, which is exactly the opposite of room temperature. Moreover, since this effect has an exponential dependence according to equation (4), this method allows the I. /I. It is possible to make this ratio extremely small. This was not previously known and was revealed by the inventor. This n-type semiconductor region is made to correspond to the emitter region 5, and p1
If P2 corresponds to the high-concentration base region 8 and P2 corresponds to the low-concentration base region 4, almost all the electron current will flow to the high-concentration base region 8.
It is clear that it is injected into That is, by covering the bottom surface of the emitter with a low concentration base, the amount of injection into the bottom surface of the emitter can be made extremely small. In the bipolar superconducting transistor of this example, an example of a structure in which the flow direction of the pair of coopers is horizontal to the substrate surface is shown, but a structure in which the flow direction is perpendicular or diagonal to the substrate surface also works in the same way. It can be manufactured based on the principle. A bibolar superconducting transistor must operate normally even under the condition that the voltage between the collector and emitter is 0, as shown in FIG. When the collector-emitter voltage is O, a forward voltage is simultaneously applied to the base-emitter pn junction and the base-collector pn junction, so the injection efficiency of the base-collector junction is also sufficiently high. This is necessary. In other words, electron current is easily injected from the collector to the base. It is necessary that it is difficult to inject hole current from the base to the collector. For this reason, in this embodiment, a structure is adopted in which the base-collector junction has a low concentration collector region 9, similar to the base-emitter junction. This makes it possible to suppress hole injection from the base to the collector, similar to the case between the base and emitter described above. Specifically, the low concentration collector region 9 is 1
The concentration is set to approximately ×10”/13. Also, since this bipolar superconducting transistor operates at a low temperature where superconductivity occurs, the high concentration emitter 6, low concentration emitter 5, high concentration base 8, low concentration collector 9,
It is better to keep the concentration of the high concentration collector 10 high enough to prevent freezing of carriers. When silicon is used as the semiconductor, freezing of carriers can be avoided by setting the concentration to 3×101″/!3 or more, so it is desirable to set the concentration higher or lower than this.This implementation The variation in the threshold voltage at which the collector current begins to flow in the bipolar superconducting transistor in this example is extremely small compared to field-effect superconducting transistors, and becomes even smaller when operated at low temperatures. Because there are many holes, which are majority carriers, inside the base, it becomes neutral due to the shielding effect.Therefore, even if the collector voltage fluctuates, the threshold value hardly changes.Threshold dispersion is caused by [ "Ultra-high-speed pipolar device" (
As described on page 54 (Baifukan, 1985), it is expressed by the following formula. ΔVaie ;- (kT/q) (ΔAg/Ag) where ΔVBEC is the change in threshold, k is the Borckmann constant, T is the absolute temperature, 9 is the amount of electron charge, ΔAR is the change in emitter area, and AE is is the emitter area. The temperature is 4.
In the case of 2K, the variation in emitter area ∆/sieve is 10
%, ΔVB is 0.036 mV. This is the threshold variation of field effect transistors1
This is more than three orders of magnitude smaller than 00mV. Furthermore, since it is sufficiently small compared to the gap voltage of the superconducting electrode (+!lv to several tens of mV), normal circuit operation is possible even with a minute logic amplitude on the order of IIlv. In addition, as is well known, the voltage amplification factor of the superconducting bipolar transistor of this example is much larger than that of a field effect transistor, so the collector current can be greatly increased even for a minute voltage on the order of mV. can be changed to In particular, when operated at low temperatures, this voltage amplification factor becomes extremely large. This is because transconductance g. is expressed by the following formula and is inversely proportional to absolute temperature. g rn = qIc/ (kT) here. is the collector current. Therefore, the temperature is 4
．． At 2K, the transconductance when 100 μA flows as a collector current is 3.65 (Siemens). This is a threshold value of more than two orders of magnitude, considering that the 1-Herance conductance of a field effect transistor is about 10 mS (even at the highest value announced so far) at a gate width of 10 μm. Therefore,
A large change in output current can be obtained even with input of a minute voltage on the order of mV. The p'np bipolar superconducting transistor 23 also operates in the same way as the npn bipolar superconducting transistor by simply reversing the polarity of the voltage applied to the electrodes. If you create an npn bipolar superconducting transistor and a pnp bipolar superconducting transistor on the same substrate,
Similar to CMOS circuits using insulated gate FETs, high-speed logic circuits with low power consumption can be realized. Embodiment 2 FIG. 2 shows a second embodiment of the present invention. A bipolar superconducting transistor is formed on the surface of the intrinsic InP substrate 24. 28 is an emitter superconducting electrode, 27 is an emitter high impurity concentration n-type region made of InGaAs with a high impurity concentration, and 5×1
The concentration is about 0"/cxn3, and 26 is the emitter low impurity concentration n-type region made of InP, 5X l O"/CI
The concentration is about 113, and 29 is a base high impurity concentration p-type region made of InGaAs.
30 is a low impurity concentration n-type collector region made of InP and has a concentration of about 5 x 10"/an3,
31 is a highly impurity-concentrated n-type collector region made of InGaAs with a concentration of about 5 x 10''/ex', 32 is a collector superconducting electrode, and 25 is an SiO film for isolation between elements. InP The forbidden band width of the base region 29 is 1.27 eV, and the forbidden band width of InGaAs is 0.75. Therefore, in the bibolar type superconducting transistor of this embodiment, the forbidden band width of the base region 29 is equal to that of the emitter 26 as in the first embodiment. This is smaller than the forbidden band width of the collector 30, and a large current gain can be obtained according to equation (3), allowing normal operation.I
Since the effective mass of electrons is small for both nP and InGaAs,
Can operate at high speed (InP is 0.067mo+I
nGaAs is 0.03m. It is. Here m. is the mass of an electron in vacuum). Furthermore, it is known that the penetration of a pair of Coopers into a semiconductor due to the superconducting proximity effect is deeper when the effective mass is smaller, and therefore the superconducting current becomes larger. In this respect as well, materials with a small effective mass are suitable for the operation of superconducting transistors. The bibolar superconducting transistor of this embodiment also has the same characteristics as the first embodiment. That is, a collector current of resistance O can be caused to flow without applying a voltage between the collector and emitter. In addition, the variation in threshold voltage is small and the transconductance is large, making it suitable for low amplitude operation. Embodiment 3 FIG. 3 shows a third embodiment of a bipolar type superconducting bipolar transistor according to the present invention. A collector superconducting electrode 35 is formed on the MgO substrate 34 by N et2-, c eXc u O, which are n-type oxide superconductors. The collector semiconductor region 36 uses an n-type semiconductor obtained by oxidizing Nd, , xCexcuOy. Nd, which is an n-conductivity type oxide superconductor)
CezcuOy becomes an n-type semiconductor by being oxidized. Since this collector semiconductor region has almost the same lattice constant as the collector superconducting electrode, it can be easily grown epitaxially. The base semiconductor region 37 is made of p-type oxide superconductor such as TIBa3Ca, Cu. p by reducing oy in nitrogen atmosphere
type semiconductor is used. A p-conductivity type oxide superconductor becomes a p-type semiconductor by being reduced. Emitter semiconductor region 38
The collector uses N d, -xce) (CuOy oxidized n-type semiconductor. Also, the emitter superconducting electrode uses N d, -xc exc Oy. The operation of this bipolar superconducting transistor is as follows. It is basically the same as the first and second embodiments, except that the current flows in the direction perpendicular to the substrate surface, and has the same characteristics.In this embodiment, a superconductor made of Cu oxide and Since the oxidized or reduced semiconductor is used, the lattice constants are almost the same, and both the superconducting electrode and the semiconductor active region can be grown epitaxially.Furthermore, these oxidized or reduced semiconductor regions The thickness of the oxide superconductor can be precisely controlled by changing the oxidation/reduction time and atmosphere, making it possible to create bipolar transistors with extremely thin base widths, which are suitable for high-speed operation. Another feature of this example is that it can operate at higher temperatures than superconductors.In this example, Ndx-
Xc e) (Cu
u, Gd, Er replaced by at least one element selected from the group, or Ce part replaced by Th,
It may be replaced with at least one element selected from the group of Tl, Pb, and Bi. Furthermore, in place of Ndi-xCexcuOy as an n-conducting type superconductor,
The composition is Ax − x Cu O y, where A is at least one selected from Sr and Ca, and N is an element that maintains the basic crystal structure and can have an oxidation number higher than 20. For example, Lay Ce, Pry Nd
, Sm+ Gd, T d + T 1 t P b r
The object of the present invention can also be achieved using an oxide superconductor characterized by at least one element selected from the group consisting of B i + Y + I n. Furthermore, the composition is A1-)(C u Oy, where A is S
At least one selected from r and Ca, N may be an element that maintains the basic crystal structure and can have an oxidation number greater than 2+, such as La, Ce, Pr, Nd, Sm.
The object of the present invention can also be achieved using an oxide superconductor characterized by at least one selected from the group consisting of , Gd, Td, TI, Pb, Bi, Y, and In. Examples of the p-conductivity type Cu oxide superconductor include La-based La1Ba. Cu. O, etc., Y-based Y, Ba, Cu
, 07, etc., Bi-based B i,S r. T1-based T such as Ca, Cu, Oy, etc.
I B a 3 C a 2 C u 4 0 y, etc. can be used. This embodiment was explained using an npn bibolar superconducting transistor as an example. A pnp bibolar superconducting transistor can also be constructed in a similar manner. Since the p-type oxide superconducting band currently has a higher superconducting critical temperature, the pnp bipolar superconducting transistor has the characteristic that it can be operated at a higher temperature.

【Effect of the invention】

In the bipolar superconducting transistor of the present invention, a superconducting current flows between the emitter and collector due to the pair of Coopers, so even if the voltage between the emitter and collector is O, a current can flow. Transistor operation using such superconducting current becomes possible only by making the distance between the collector and emitter smaller than the coherence length of the superconducting electrode. Furthermore, the variation in the threshold voltage at which the collector current begins to flow in this bipolar transistor is extremely small compared to that of a field-effect superconducting transistor, and becomes even smaller especially when operated at low temperatures. This is because the base region is electrically neutral due to the presence of majority carriers in the base region. Field effect transistor threshold variation 100mV
It is possible to achieve a variation value that is more than three orders of magnitude smaller than that of the conventional method. Also, the gap voltage of the superconducting electrode (from mV to several tens+++V
), so normal circuit operation is possible even with minute logic amplitudes on the order of mV. Further, the voltage amplification factor of the bipolar superconducting transistor of the present invention is two or more orders of magnitude larger than that of a field effect transistor, so that the collector current can be changed significantly even with a minute voltage on the order of mV. If the present invention is applied to a bipolar transistor using a normal homojunction (junction using the same material), there is a problem that the current gain becomes extremely small at low temperatures.
If a material is used in which the forbidden band width of the emitter semiconductor region is larger than that of the base semiconductor region, a large current gain can be achieved even at low temperatures. For this purpose, a heterojunction may be used in which the emitter and base are made of different semiconductor materials that satisfy this condition. Since the current gain increases exponentially as the temperature decreases according to equation (3), the current gain at low temperatures can achieve an extremely large value of 1000 to 10', which is impossible at room temperature. For this. A beta junction using different semiconductor materials that satisfies this condition for the emitter and base may be used. In addition, by making the impurity concentration in the base active region higher than the impurity concentration in the emitter region and making the concentration in the base active region high enough to produce a band gap reduction effect, a homojunction (junction made of the same material) can be used. Even though
A large current gain can be obtained at low temperatures. If this structure is applied to a bibolar superconducting transistor, the manufacturing process can be simplified, and since it is a homojunction, the emitter
Recombination current between the bases can be reduced. Further, by directly connecting a superconducting electrode to the base semiconductor region, a pair of coopers enters the base semiconductor region from the base superconducting electrode. As a result, the majority carriers (holes in the case of an nρn bipolar transistor) in the base also become a pair of Coopers, and the base resistance can be made extremely small. Furthermore, by adopting a horizontal structure, that is, a structure in which the direction in which current flows is parallel to the substrate surface, the manufacturing process is simplified. Furthermore, in order for the proximity effect from the superconducting electrode to the semiconductor region to work effectively, the semiconductor region must contain a sufficient number of carriers even when operated at low temperatures. For this purpose, it is desirable to have a degenerate semiconductor in which the Fermi level falls into the valence band or conduction band. This allows normal operation. In addition, in horizontal bipolar transistors, high-speed performance deteriorates due to the current component flowing from the bottom of the emitter inside the substrate and reaching the collector, but this can be prevented by providing a barrier layer with a low impurity concentration on the bottom of the emitter. . Furthermore, by forming the npn bibolar superconducting transistor and the pnp bibolar superconducting transistor of the present invention on the same substrate, a complementary circuit similar to a CMOS circuit can be realized, resulting in low power consumption and high-speed integration. The circuit can be realized. In addition, by using an oxide superconductor containing Cu as a superconductor and using a semiconductor region obtained by oxidizing or reducing the oxide superconductor in a bipolar transistor, operation at relatively high temperatures is possible, and in addition, it is possible to operate at relatively high temperatures. Use growth. It has the advantage that it is easy to form an octahedral vertical bipolar transistor. Therefore, there is a great effect on speeding up integrated circuits, computers, measuring instruments, communication systems, etc. using the present invention.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view of a complementary bibolar superconducting transistor according to a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of an npn bibolar superconducting transistor of a second embodiment. figure,
Figure 3 is a cross-sectional view of the npn bipolar superconducting transistor of the third embodiment, and Figure 4 is a band diagram of the npn bipolar superconducting transistor when no voltage is applied between the collector and emitter. Figure 5 is a band diagram of the npn bipolar superconducting transistor of the present invention when a voltage is applied between the collector and emitter, and Figure 6 is a diagram showing the current-voltage characteristics of the bipolar superconducting transistor of the present invention. FIG. 7 is a diagram showing two types of current paths in a lateral bipolar superconducting transistor, and FIG. 8 is a cross-sectional view showing a junction between an n-type semiconductor and two types of p-type semiconductors having different concentrations. Explanation of symbols■...p-type silicon substrate, 2...Sin region for isolation between elements, 3...n-type well region, 4...p-type low impurity concentration base region, 5...・Low impurity concentration n-type emitter region, 6... High impurity concentration n-type emitter region,
7...Emitter superconducting electrode, 8...High impurity concentration p-type base region, 9...Low impurity concentration n-type collector region,
10... High impurity concentration n-type collector region, 11...
Collector superconducting electrode, 12...high impurity concentration p-type polycrystalline silicon external base region, 13...npn pipo?
R-type superconducting transistor, 14... n-type low impurity concentration base region, 15... low impurity concentration p-type emitter region, 16... high impurity concentration p-type emitter region, 17...
- Emitter superconducting electrode, 18... High impurity concentration n-type base region, 19... Low impurity concentration n-type collector region,
20...High impurity concentration n-type collector region, 21...
Collector superconducting electrode, 22... High impurity concentration p-type polycrystalline silicon external base region, 23... pnp bibolar superconducting transistor, 24... InP substrate, 25
...SiO■ region for isolation between elements, 26...In
Emitter low impurity concentration n-type region formed by P, 27... Emitter high impurity concentration n-type region formed by InGaAs with high impurity concentration, 28... Emitter superconducting electrode,
29...Base high impurity concentration p-type region made of InGaS, 30...Low impurity concentration n-type collector region made of InP, 31...InGaAs
High impurity concentration n-type collector region, 32... Collector superconducting electrode, 33... Base superconducting electrode, 34...
・MgO substrate, 35... N d. which is an n-conductivity type oxide superconductor. ). Collector superconducting electrode by C eXC u O, 3 6 ''' N d 2-xC e x
Collector semiconductor region made of an n-type semiconductor obtained by oxidizing C u O, 37...TI which is a p-conductivity type oxide superconductor
Ba. Base semiconductor region made of p-type semiconductor reduced Ca2Cu40y, 3 8 ・= N d 2 − X
Emitter semiconductor region made of n-type semiconductor obtained by oxidizing CexCuOy, 39...Nd,) (CexC
uOy emitter superconducting electrode. 40...hole, 41...electron, 42...conduction band, 4
3...Valence band, 44...Collector end of base, 45
...Superconducting current component. jQ'- (2?) ll 4ρ 1st otsu dark rikore 7ku ekofuta r: Ia anti

Claims (1)

[Claims] 1. A superconducting transistor in which a superconducting current reaching a second superconducting electrode from a first superconducting electrode via a semiconductor region is controlled by changing the potential of a third electrode, A semiconductor device characterized in that carriers of the opposite conductivity type exist at a higher density than the carrier density of the superconducting current in at least a part of the path of the superconducting current. 2. A bipolar device including a collector region made of a first conductivity type semiconductor, a base region made of a second conductivity type semiconductor connected to the collector region, and an emitter region made of a first conductivity type semiconductor connected to the base region. A semiconductor device characterized in that, in a transistor, a superconducting electrode is connected to an emitter region and a collector region, and a superconducting current between the collector and emitter is controlled by changing the number of minority carriers in the base. . 3. The distance between these superconducting electrodes is the sum of the coherent length that penetrates into the semiconductor region from the superconducting electrode connected to the emitter and the coherent length that penetrates into the semiconductor region from the superconducting electrode connected to the collector. 3. The semiconductor device according to claim 2, wherein the semiconductor device is relatively long. 4. The semiconductor device according to claim 2, wherein the forbidden band width of at least a part of the emitter semiconductor region is larger than the forbidden band width of at least a part of the base semiconductor region. 5. The semiconductor device according to claim 2, wherein the forbidden band width of the base semiconductor region is smaller than the forbidden band width of the emitter semiconductor region and smaller than the forbidden band width of the collector semiconductor region. 6. The first part of at least a part of the emitter region
3. The semiconductor device according to claim 2, wherein the conductivity type impurity concentration is set to a value lower than the maximum value of the second conductivity type impurity concentration in the active base. 7. The semiconductor device according to claim 6, wherein the emitter region and the base region are formed of substantially the same semiconductor material except for impurities of the first and second conductivity types. 8. The semiconductor device according to claim 2, further comprising a base electrode made of a superconductor that is in direct contact with the base semiconductor. 9. The semiconductor device according to claim 1, wherein the current flowing from the first semiconductor region to the third semiconductor region is parallel to or close to the surface of the semiconductor substrate. 10. In the semiconductor device according to claim 1, on the path of current flowing from the first semiconductor region to the third semiconductor region,
A semiconductor device characterized in that the impurity concentration is higher than the Mott transition concentration determined by the semiconductor material and the impurity species. 11. In a semiconductor device in which carriers are at least injected from a semiconductor region of a first conductivity type to a semiconductor region of a second conductivity type, the second conductivity type semiconductor region has at least a first region with a low impurity concentration and a first region with a high impurity concentration. A semiconductor device that has a second region and utilizes the fact that at low temperatures, the amount of carriers injected into the second region is larger than that of the first region. 12. In the bipolar transistor according to claim 2, at least a portion of the periphery of the emitter of the first conductivity type is provided with a second
1. A semiconductor device comprising an intrinsic base layer of a conductivity type with a high impurity concentration and a carrier injection barrier layer of a second conductivity type with a low impurity concentration. 13. A semiconductor device comprising the npn bipolar transistor according to claim 2 and the pnp bipolar transistor according to claim 2 on the same substrate. 14. In the bipolar transistor according to claim 2, the superconducting electrode is made of an oxide superconductor containing Cu, and at least a part of the semiconductor region is made of a region obtained by oxidizing or reducing the oxide superconductor containing Cu. A semiconductor device characterized by: 15. A semiconductor device in the bipolar transistor according to claim 2, wherein at least a part of the semiconductor region is formed by oxidizing an n-conductivity type oxide superconductor.