JPH0223101B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a signal transmission system using PCM (Pulse Code Modulation), and in particular to differential PCM and quasi-instantaneous companding.
This paper relates to a signal transmission method using PCM with excellent transmission efficiency.

[Technical background of the invention]

Differential PCM as an efficient PCM encoding method
(hereinafter referred to as DPCM) is known. normal
While PCM encoding transmits the values obtained by sampling an analog original signal such as an audio signal every moment as digital data, that is, PCM code, DPCM transmits only the difference from the previous value, that is, the difference between two samples, as digital data. Because it is differential data, it can be digitally expressed with a small number of bits, and the data can be compressed.

Figure 1 shows an example of a transmission system using DPCM encoding.

The analog signal is converted into, for example, a 15-bit digital signal by an A/D converter 1, and is input to a delay circuit 2 using a register or the like. A/D in delay circuit 2
One sample of the digital signal input from the converter 1 is delayed and input to the difference circuit 3. Also A/
The next one-sample digital signal output from the D converter 1 is also input to the difference circuit 3.
Now, calculate the difference between both input signals, for example, 16 bits.
It is sent to the transmission system as a DPCM code.

Here, the transmission system includes transmission lines such as simple connection lines and communication lines with modulation/demodulation systems (sometimes the medium is radio waves, light, etc.), as well as recording systems for compact disks such as records and magnetic tapes. Refers to a transmission system in a broad sense, including

The differential data, in this case 16 bits, transmitted through the transmission system is first input to the adder circuit 4 on the receiving side. Here, the cumulative total (integral) data of the 16-bit difference data input to the adder circuit 4 up to the previous time is also created in the delay circuit 5, and is output from there and input to the adder circuit 4. The adder circuit 4 adds the cumulative data input from the delay circuit 5 and the difference data input from the transmission system, and can obtain the original analog signal via the D/A converter 6.

A feature of this DPCM code transmission is that by transmitting only the difference data between two temporally adjacent samples, the value of the digital data to be transmitted can be reduced on average.

Furthermore, as a method for effectively transmitting data with a small average level and a low probability of occurrence of high-level signals, normal transmission is performed using a predetermined number of bits that is smaller than the original data, and the range that can be expressed with this predetermined number of bits is So-called quasi-instantaneous companding has been considered, in which a predetermined number of upper effective bits are transmitted as data, and the lower bits are discarded. In this case, for the lower bits that were truncated, if only the encoded shift amount corresponding to the number of truncated bits is transmitted to the receiving side (the contents of the truncated bits are not sent), the correct number of digits can be restored on the receiving side. , and almost correct playback can be performed. In reality, for each data block consisting of a plurality of samples, the maximum level value of the absolute value of the samples in the block is detected, and the data in the block is digit-shifted accordingly to obtain data of a predetermined number of upper bits. An effective method is to transmit the main transmission data and scale information by using the digit shift information as the main transmission data and also using the digit shift information as scale information corresponding to the number of truncated bits. In this way, almost sufficient information can be transmitted by transmitting one piece of scale information for each data block consisting of a large number of sample data.

An example of such a method will be explained. The example described here is for reducing the number of bits of transmitted data using the above method in normal PCM transmission, and its configuration is shown in FIG.

Analog signal input such as audio signals is A/D.
After the converter 7 converts the digital signal into a digital signal with a sufficient number of bits, for example 15 bits, at fixed time intervals, the digital level detection circuit 8 digitally detects the maximum level of the absolute value within a predetermined period or a level approximately equivalent to it. , for example, obtains a 3-bit shift amount, that is, scale information data. Next, the digital variable circuit 9 adjusts the A/
The 15-bit digital signal from the D converter 7 is digitally level controlled and data compressed.
For example, when 15 bits are compressed into 8-bit data, the upper 8 bits of the 15-bit digital signal are used as main data. The 8-bit main data and 3-bit scale information data are input to the synthesis circuit 10,
The synthesis circuit 10 compresses the information so that one piece of 4-bit scale information data corresponds to a large number of 8-bit main data, and sends it to the transmission system using time division or the like.

On the other hand, on the receiving side, a separation circuit 11 separates 8-bit main data and 4-bit scale information data from the transmission signal received from the transmission system, and a digital level variable circuit 12 converts the 8-bit main data into 4-bit scale information data. Based on this, digital control is performed in the opposite direction to that on the transmitting side, and the signal is returned to a 15-bit digital signal. Further, a D/A converter 13 converts the digital signal into an analog signal to obtain a signal that approximates the original audio signal.

By compressing the transmission data in this way, that is, from 16 bits to 8 bits in this example, and further compressing the data into one piece of scale information per block, transmission efficiency can be improved.

By the way, this type of quasi-instantaneous companding is
When PCM, that is, PCM encoded data, is transmitted as is, it includes truncation errors, but there is no accumulation of errors, so it can be used almost effectively, but it was considered difficult and undesirable to apply it as is to DPCM.

The main reason is as shown in Figure 1.
This is because receiving DPCM requires decoding by cumulative and integral operations on the receiving side, and errors caused by truncation on the transmitting side are added up on the receiving side, resulting in a large error.

For this reason, even if DPCM can compress data by lowering the average level of transmitted data, it has not been possible to reduce the number of bits of actual DPCM transmitted data using quasi-instantaneous companding.

It is also possible to consider lowering the number of transmission bits by setting a certain rule in advance between transmission and reception, such as ADPCM (adaptive DPCM - adaptive differential PCM), and performing non-linear transmission and reception while lowering the level resolution on the receiving side. However, such ADPCM etc. cannot be said to be very accurate and has many problems such as not only being unable to perform good reproduction on the receiving side but also making the device complicated.

[Conventional technology and problems]

In response, the following transmission method takes advantage of the effect of reducing the average level of transmitted data by DPCM and also makes effective use of quasi-instantaneous companding to enable high-precision transmission with a smaller number of bits and no accumulation of errors. Conventionally, methods such as the following have been considered.

In other words, when performing quasi-instantaneous companding of a DPCM signal,
On the transmitting side, the missing bits (lower bits below the transmitted bits) are added at each sample time (for each data item), and if a carry occurs as a result of the addition, a carry is added to the lowest bit of the main data to be transmitted at that point. This method is to add it as input.

By using this method to correct the transmitted data, send it to the transmission system, and regenerate this transmission, the quantization noise that occurs when digitizing analog signals is whitened, and the quantization noise is concentrated only in the high frequency range. It is an ideal signal transmission method with low noise because it has a de-emphasis effect and the integrating circuit on the receiving side becomes an ideal noise reduction circuit for DPCM data.

However, even with the signal transmission method having the above-mentioned excellent characteristics, if the 8-bit main data happens to be a pattern of "01111111" and the sum of the missing bits up to that point outputs a carry, the transmitted data will be "01111111". Since 1 is added to the least significant bit of , it becomes "10000000". This means that in the case of the so-called two's complement display system in which the most significant bit of 8-bit main data represents a positive or negative sign, the sign of the main data is reversed. In other words, the transmitted data overflows (in the case of two's complement representation,
A problem arises in that the carry from the sign bit and the carry from the most significant numerical bit are exclusive, and when this is 1, the sign bit is inverted.

[Purpose of the invention]

In view of the above-mentioned drawbacks of the conventional technology, the present invention has been developed to solve the problem of overflowing the transmitted data by adding 1 from the cumulative total of lost bits to the transmitted data as a carry input when there is a carry input. The purpose is to provide a signal transmission device that prevents this from occurring.

[Key points of the invention]

According to the present invention, when performing quasi-instantaneous companding of a PCM signal or DPCM signal, a predetermined scale value is transmitted as transmission data together with the main data, and the missing bits of the lower bits are added and a carry is added to the addition result. In a digital signal transmission device that adds the carry portion to the least significant bit of the transmission data and transmits the data, if the most significant bit of the transmission main data is 0 and the other bits are 1, overflow prevention is performed. The main data for 001…
This can be achieved by providing a digital signal transmission system in which a value obtained by adding 1 to the scale value is used as the scale value.

[Embodiments of the invention]

Embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

FIG. 3 is a block diagram of an embodiment of the signal transmission system of the present invention.

For analog signals such as audio, A/D converter 1
4, and the analog signal is converted into a digital signal by an A/D converter 14.

This digital signal is input to a difference calculation circuit 15 and a one sample delay circuit 16. The one-sample delay circuit 16 latches one sample of input data, and outputs the previous latched data to the difference calculation circuit 15 when the next one-sample digital signal is input. The difference calculation circuit 15 calculates the difference between the next digital signal input from the A/D converter 14 and the previous digital signal from the one sample delay circuit 16.

A differential digital signal, ie, a DPCM signal, output from the differential calculation circuit 15 is input to a one-block delay circuit 17 and a scale value detection circuit 18. The one-block delay circuit 17 delays the sample group of the input DPCM signal by one block. The scale value detection circuit 18 detects the scale value (coded signal of the shift amount) of the DPCM signal data with the largest absolute value among the samples of one block, and transfers the scale value to the one block delay circuit 17.
is the scale value of the entire block delayed by . 1
Data from the block delay circuit 17 and scale value data from the scale value detection circuit 18 are input to a pattern detection circuit 19. The pattern detection circuit 19 checks whether a pattern "01111111" exists among the effective bit patterns for transmission created when the sample data in one block inputted from the one block delay circuit 17 is shifted according to the scale value. If that pattern exists, the output is activated, for example to a high level. The scale value data of the scale value detection circuit 18 and the detection data of the pattern detection circuit 19 are transferred to the scale value increase circuit 2.
0, this circuit adds 1 to the scale value data input from the scale value detection circuit 18 when the output signal of the pattern detection circuit 19 is activated, and when the output signal is inactive, for example, low. At level, the scale value data is controlled to remain as it is.

Scale value data modified by the scale value increase circuit 20 (original scale value or 1
(scale value added) is input to the compression circuit 21 and the synthesis circuit 22. The compression circuit 21 executes a pattern check between 1 blocks on the DPCM signal delayed by 1 block, so the DPCM signal is further delayed by 1 block in the 1-block delay circuit 23, and the DPCM signal is delayed by 1 block.
The signal is compressed according to the scale value data corrected by the scale value increasing circuit 20. When compressing this DPCM signal, the missing bits are added at each sample time using an accumulator, etc., and if a carry occurs, it is added to the least significant bit of the transmitted main data, and the output is synthesized. input to circuit 22; At this time, since the scale value of the pattern in which the effective bit of the DPCM is "01111111" is increased by 1, the main data becomes "00111111", so there is no overflow. The synthesis circuit 22 transmits the scale value data inputted from the scale value increase circuit 20 together with the compressed data for one block to the receiving side.

The PCM signal transmission device having the above configuration and operation has a one-block delay circuit 23 installed after the conventional one-block delay circuit 17 for detecting a scale value from differential signal data, and the one-block delay circuit 23 performs DPCM. While the signal is delayed by one block, the pattern detection circuit 19 checks whether the pattern "01111111" exists in the differential signal data in the block in the DPCM signal. If the pattern "01111111" exists in the DPCM signal data in the block, the scale value increasing circuit 20 detects the scale value detecting circuit 18 regardless of whether a carry has occurred from the accumulated missing bits to the main transmission data. Input a signal that adds 1 to the scale value detected in .

Therefore, when the effective bits of the DPCM signal data are in a pattern of "01111111", it is possible to completely prevent overflow caused by the cumulative total of missing bits being carried to the lowest position of the DPCM signal data.

Of course, it is not possible to increase the scale value in the case of the maximum scale value, and if necessary, a logic circuit corresponding to this can be installed, and in order to eliminate the occurrence of overflow in this case, such a logic circuit can be installed. Of course, in some cases, addition of the transmitted data and the accumulator may be stopped.

In the above explanation, the case where 16-bit data is transmitted in 8 bits has been explained, but it goes without saying that any number of bits may be used.

Also, in the above explanation, a 1 block delay is performed, but since the detection of the scale value or the detection of the bit pattern of "01111111" can normally be performed at high speed, the delay is 1 block.
There is no need to delay data until the time of the block.

Note that the present invention is applicable not only when there is a carry in the transmitted data as a result of cumulative addition of missing bits, but also when the scale value changes (decreases) even if the cumulative addition result does not result in a carry. , even when an overflow occurs when the upper digits of the cumulative addition contents are carried up into the transmitted data due to the position of the transmitted data being shifted down,
It can be applied to prevent overflow.

In addition, in the above explanation, the cause of the overflow is whether it is due to the accumulation of missing bits or
Although we have assumed either one of the following cases: or the position of the transmitted data is due to a downturn, both cases may occur at the same time.

In this case, “01111111” is of course “01111110”
must also be detected. Actually 2
It is not necessary to detect two patterns; it is sufficient to detect "0111111X". Here, X indicates that it may be either 0 or 1. In other words, you can simply ignore the lowest order and check the 7 bits "01111111".

Furthermore, since overflow caused by a digit increment in the position of transmitted data occurs only in the first data of a block, overflow in this relationship can be prevented by setting only this data length to 9 bits.

Therefore, if the system is designed in this way, overflows will not occur simultaneously due to two things, and as explained from the beginning, 8 bits of "01111111" will be detected.

In addition, in the above, the downshifting of the transmission data position, that is, the change in the scale value, was set to be 1 or less at maximum per block, but in a design that allows two downshifts, the detection of 6 bits "011111" and Become. However, as the amount of detection bits is reduced in this way, the probability that the value will not fall to a predetermined scale value increases, and it goes without saying that the system will have a poor S/N ratio.

As described above, in order to prevent the occurrence of overflow, the present invention detects a pattern in which "011~" and a required number of "1"s below "0" continue.

Next, in order to embody the present invention, an accumulation operation of lower missing bits will be described when transmitting 8 bits as main data from a 16-bit DPCM signal.

FIG. 4 is a circuit block diagram for performing an accumulation operation on the lower missing bits.

The lower 8 bits of the DPCM signal data are input to the mask logic 24, and the mask logic 24 passes some of the least significant bits among the lower 8 bits according to the scale value. For example, if the scale value is 4 and the lower 8 bits are "01101101", the bits that actually lose digits are the lower 4 bits, and the upper 4 bits do not lose digits and are forcibly masked to 0, so the output of the mask logic 24 is “00001101”
becomes. The missing bits that have passed through the mask logic 24 are input to an 8-bit full adder 25, and the 8-bit full adder 25 adds them to the accumulated missing data input from the accumulator hold circuit 26 to the 8-bit full adder 25.

The missing cumulative data added by the 8-bit full adder 25 is input to the carry detection position selection circuit 27,
Select the carry detection position according to the current scale value. This carry detection position signal is input to the correctable check logic circuit 28, and the correctable check logic circuit 28 inputs the data of the compression encoder (not shown) when detecting the carry when the correction prohibition signal inputted from the outside is not input. 01111111”, the correction signal from the control sequencer (not shown) is inhibited. Therefore, the correctable check logic circuit 28 outputs a compressed data correction signal necessary to prevent overflow at the time when the carry signal is output.

Furthermore, according to the scale information, the mask logic circuit 29 does not store data corresponding to a carry in the cumulative missing data when detecting a carry, so it masks the carry position to 0 and does not input bit information of the carry position to the accumulator hold circuit 26. This is a circuit for The accumulator hold circuit 26 is a circuit for latching the accumulated missing data up to that point in response to an accumulator latch signal inputted from the control sequencer.

With the above configuration, the missing bits that are not transmitted among the lower 0 to 8 bits in the 16-bit DPCM signal data are accumulated. For example, if the scale value is up to 8, the missing bits are 16 bits.
The missing bits are the lower 8 bits of the DPCM signal data, and if the scale value is 3, the missing bits are 16 bits.
These are the lower 3 bits of the DPCM signal data. When the scale value is 3, if the lower 4 bits or more of the input to the mask logic 24, in which the lower 8 bits are input, are masked to 0, the addition operation is performed correctly by the 8-bit full adder 25 and the like.

Therefore, only the true missing bits are subject to addition by the mask logic circuit 24, and when the fourth bit from the bottom changes from 0 to 1 after addition, this 1 is added.
Correction is performed by adding it as a carry input to the 8-bit transmission main data of the DPCM signal data. The 4th digit 1 has now been transmitted,
Since it has to be erased from the accumulator 26, this is performed by the mask circuit 29.

〔Effect of the invention〕

As explained in detail above, according to the present invention,
When the effective upper bits of DPCM are in a pattern of "01111111", the scale value always changes, so it is 100% possible to prevent transmission data from overflowing even if the accumulated number of missing bits increases.

Furthermore, the present invention can be implemented by simply detecting a pattern in which the transmitted data is "01111111", and there is no need to consider carry over from the cumulative total of missing bits, so it can be implemented with an extremely simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram explaining a DPCM signal, FIG. 2 is a circuit block diagram explaining quasi-instantaneous companding, FIG. 3 is a circuit block diagram of a signal transmission device of the present invention, and FIG. 4 is a circuit block diagram of a signal transmission device of the present invention. It is a circuit diagram of an application example.
19...Pattern detection circuit, 20...Scale value increase circuit, 23...1 block delay circuit, 24...
. . . mask logic circuit, 25 . . . 8-bit full adder, 28 . . . correctable check logic circuit.

Claims (1)

[Scope of Claims] 1. In a system including means for cumulatively adding missing bits when DPCM data is quasi-instantaneous companding, and means for adding a carry portion of the cumulative addition to transmission data and transmitting the data. A detection circuit is connected to the detection circuit for detecting a state in which the most significant bit of the effective bits for transmission obtained by shifting the bits according to the scale value is 0 and the other bits are 1; A digital signal transmission system that transmits transmission data without overflow, the method comprising means for changing the scale value in the direction of increasing the scale value when the scale value is detected. 2. When there is at least one piece of data that starts with 0 and continues with 1 in one block of the effective bits for transmission, the value obtained by adding 1 to the scale value is set as the new scale value. Range 1
Digital signal transmission method described in Section 2.