JPH0223445A - Bus supervisory and controlling system - Google Patents

Abstract

PURPOSE:To shorten a processing time at an abnormal time and to prevent bus performance from decreasing by individually supervising the bus by means of an optimum time-out period set at every device and at every access classification according to an access request to be sent to a bus. CONSTITUTION:The time-out period fetched from a time setting register 2 corresponding to the access request to be sent to the bus is loaded on a counter 3, and counting is started. When a response signal is detected before a time-out is sent from the counter 3, it is decided to be normal. On the other hand, when the response signal is not sent to the bus even if the time-out is sent from the counter 3, a bus error signal is sent to a microprocessor 4. Thus, by supervising the bus with the use of the time-out supervisory time set at every device and at every access classification, the processing time at the time of the bus abnormality is shortened, and the bus performance is prevented from decreasing.

Description

[Detailed Description of the Invention] [Summary] The present invention provides a bus monitoring and control method for monitoring an asynchronous bus, in which the bus monitoring time is long due to differences in access times of various devices coupled to the bus and bus hierarchization. In order to solve the problem of deterioration in bus performance due to
The bus monitoring time is optimized to shorten the processing time and prevent deterioration of bus performance in the event of a bus abnormality.

[Industrial application field]

The present invention relates to a bus monitoring control method for monitoring an asynchronous bus.

[Problems to be solved by conventional technology and invention] Conventionally, M
In a system where a PU accesses multiple devices via a bus, a bus monitoring device that monitors this bus is
A timer is started when a specific signal is sent to the bus, and a bus error signal is sent to the MPU when a response is not sent to the bus after a predetermined fixed period of time has elapsed.
We are trying to notify the following. MP who received this notification
U interrupts the access request and makes the next access request.

However, as systems become more multi-functional, when the same bus is shared, if the bus monitoring time is made longer in association with the access request with the longest access time, problems will occur with respect to other short access requests. Detection of such failures inevitably requires waiting for a long time, resulting in a problem that the performance of the bus deteriorates.

The present invention optimizes bus monitoring time by setting monitoring time in association with each device connected to the bus and each access type, thereby shortening processing time and preventing deterioration of bus performance in the event of a bus abnormality. The purpose is to

(Means for solving problems) Means for solving the problem will be explained with reference to FIG.

In FIG. 1, a bus monitoring device 1 monitors whether or not an access request sent to the bus has timed out, and is comprised of a time setting register 2, a counter 3, and the like.

The time setting register 2 is used to set a timeout time in advance in association with the device connected to the bus and the type of access.

The counter 3 is triggered by an access request sent to the bus, loads the contents of the corresponding time setting register 2, starts counting, and sends out a timeout.

[Effect]

As shown in FIG. 1, the present invention sets a timeout time corresponding to the device connected to the bus and the type of access in advance in the time setting register 2, and when an access request is sent to the bus. , loads the contents of the corresponding time setting register 2 into the counter 3 and starts counting, and if a response is not sent to the bus even after a timeout is sent from the counter 3, a bus error signal is sent to M.
We are trying to notify PU4 etc.

Therefore, it is possible to monitor the bus with an optimal timeout time for each device and each type of access (DMA data transfer, etc.) in response to access requests sent to the bus.

(Embodiment) Next, the configuration and operation of an embodiment of the present invention will be explained in detail using FIGS. 1 to 3.

In FIG. 1, a bus monitoring device 1 monitors the usage status of the bus.

The time setting register 2 is connected to the slave device (1) 8, slave device (2) 9, and I connected to the hierarchical bus shown in the figure.
The timeout period corresponding to devices such as the 10 control circuit 6 and the type of access request sent to the bus (DMA data transfer, read/write, etc.) is set in advance.

When the counter 3 counts the timeout time taken out and loaded from the corresponding time setting register 2 in response to the access request being sent to the bus,
This is to send a time-over signal.

The MPU (microprocessor) 4 connects the I
10 control circuit 6, slave device (1) 8, and slave device (2) 9 to perform various processes.

The arbitration circuit 5 manages the hierarchical buses so that conflicts do not occur.

The I10 control circuit 6 controls data transfer between the I107 and other devices (slave device (2) 9, etc.).

The slave device (118) and slave device (2) 9 transfer data via the bus and perform various processes.

FIG. 2 shows an example of the main part configuration of the bus monitoring device 1 shown in FIG. 1.

In FIG. 2, a time setting register (1) and a time setting register (2) are used to set timeout times in advance in association with access types from devices connected to the bus. The timeout time preset in this time setting register (11, (2)) corresponds to the input of either the selection signal of the time setting register 11 shown or the selection signal of the time setting register (2). The 0 selection signal selected by the multiplexer 3-1 and input to the counter 3 is, for example, a DMA instruction signal and an I1
It may be generated by performing an AND operation with the selection signal for the 0 column circuit 6.

The counter 3 starts counting by loading the timeout time inputted from the multiplexer 3-1 by the illustrated load & enable signal, and if no response has been sent to the bus yet when the time corresponding to the timeout has elapsed, The illustrated bus timeout signal is sent.

Next, the operations of the configurations in FIGS. 1 and 2 will be described in detail in accordance with the order shown in FIG. 3.

In FIG. 3, ■ indicates that the MPU 4 uses the time setting register 2.
Timeout times T1 to T are set in advance for each device and each access type. This timeout period T (
l=1 to n) is set to a large value in the case of DMA data transfer, and is set to a small value in the case of a read/write request. Further, a thicker value is set for a device that transfers a large amount of data by DMA data, and a smaller value is set for a device that does not.

■ is T compatible with CS (Chip 5 select)
, through 'r1 are loaded into the counter 3.

This means that when the access request C8 is sent to the bus, the timeout time taken out from the corresponding time setting register 2 preset in step 3 is loaded into the counter 3 and counting is started.

In (2), it is determined whether the count value is T+<DTACK. This is YES (
On the other hand, if DTACK is sent to the bus before the timeout is sent from the counter 3, it is judged as No (normal). If YES, it is an abnormality, and the timeout sent from the counter 3 is notified as a bus error signal to the MPU 4, etc., and the device to be accessed is judged to be abnormal, the access request is interrupted, and the next Make access requests. If NO, it is normal, so clear the counter 3 with ■ and repeat the steps below @.

As described above, the timeout time taken out from the corresponding time setting register 2 in response to C3 (access request) is loaded into the counter 3 and starts counting, and DTACK <
If the response signal (response signal) is detected before the timeout is sent from the counter 3, it is considered normal. On the other hand, if the DTACK is not sent to the bus even after the timeout is sent from the counter 3, a bus error signal is sent to the MPU 4 etc. By making the notification, it becomes possible to individually monitor the bus using the optimal timeout monitoring time set in advance for each device and each access type.

〔Effect of the invention〕

As explained above, according to the present invention, the bus is individually monitored according to the optimal timeout time set in advance for each device and each access type in response to access requests sent to the bus. This eliminates unnecessary time for bus monitoring and minimizes bus waiting time. This makes it possible to avoid deterioration in bus performance, especially when the bus is hierarchized and various devices are connected as computer systems become more multifunctional.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an embodiment of the present invention, FIG. 2 is an example of the configuration of a main part of a bus monitoring device, and FIG. 3 is an explanatory diagram of the operation of the present invention. In the figure, 1 is a bus monitoring device, 2 is a time setting register, 3 is a counter, and 4 is an MPU. Book 4 colors Sun Moon's 1 ability color fl, Y China, 10,000! Figure￥J]
Diagram of the bus jaw-mouth viewing device's light? Senmoto Komei's operation explanation horse diagram 3

Claims (1)

[Claims] In a bus monitoring control method for monitoring a bus, a plurality of time setting registers (2
), and a counter that is set by extracting from one of the above time setting registers (2) the timeout time corresponding to the access request source/access request destination device and access type, triggered by sending an access request to the bus. (
3), and is configured so that if a timeout is sent from this counter (3) before a response corresponding to the access request is sent to the bus, the timeout is sent as a bus error signal. Characteristic bus monitoring control system.