JPH0223475A - Logarithm converting circuit - Google Patents

Logarithm converting circuit

Info

Publication number
JPH0223475A
JPH0223475A JP63174563A JP17456388A JPH0223475A JP H0223475 A JPH0223475 A JP H0223475A JP 63174563 A JP63174563 A JP 63174563A JP 17456388 A JP17456388 A JP 17456388A JP H0223475 A JPH0223475 A JP H0223475A
Authority
JP
Japan
Prior art keywords
conversion
converter
gain
input
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63174563A
Other languages
Japanese (ja)
Inventor
Teruo Fumoto
麓 照夫
Yukifumi Tsuda
津田 幸文
Hiroaki Kodera
宏曄 小寺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63174563A priority Critical patent/JPH0223475A/en
Publication of JPH0223475A publication Critical patent/JPH0223475A/en
Pending legal-status Critical Current

Links

Landscapes

  • Image Processing (AREA)
  • Facsimile Image Signal Circuits (AREA)

Abstract

PURPOSE:To make concentration conversion highly accurate by providing an A/D converting means to change a conversion gain with the level of an analog input signal and a logarithm converting table to switch reference data according to the switching of the conversion gain. CONSTITUTION:When an analog input inserted to an input terminal A of a comparator 106 is smaller than a direct current voltage divided by voltage- divided resistances 109 and 110 inserted to an input terminal B, the output of the comparator 106 becomes low, a selector 103 selects the input A, an A/D converter 104 A/D-converts the high gain, the output selects a high gain converting LUT by a logarithm converting LUT 105, and executes the logarithm conversion. On the other hand, when the input terminal A of the comparator 106 becomes higher than the input terminal B, the output becomes high, and the selector 103 selects the input B. Consequently, the A/D converter 104 A/D- converts the standard gain, and the output selects a LUT for the standard gain by the logarithm converting LUT 105, and executes the logarithm conversion.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、原稿読取装置の信号処理、とりわけ輝度−濃
度変換、すなわち対数変換を行なう対数変換回路に関す
るものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to signal processing of a document reading device, and particularly to a logarithmic conversion circuit that performs brightness-density conversion, that is, logarithmic conversion.

従来の技術 従来より、画像読取装置では、原稿を白色光もしくは単
色光で照射し、それより反射もしくは透過する光の強さ
を光ダイオードもしくは光電管によυ検出して原稿点の
読取出力を得て、しかる後に対数変換を行ないC,M、
Yの濃度信号を得ている。第7図に従来の方法での対数
変換の構成を示す。この例では、まず入力アナログ信号
を基準信号に基づきA/D変換器701でA/D変換し
た後、対数変換テーブル(LUT)702に入力し、透
過率リニアのデータに対し、出力を対数変換した濃度情
報を得ている。LUT702の特性を第8図に示す。第
8図のLUT変換特性は通常、入力をY1出力をDとす
ればD = −1ogxo Y (但しYは、0〜1Ω
規格化値)の特性をもつ。この様な従来例の場合、出力
信号(2)の濃度分解能を例えば8ビツトとした場合、
対数曲線の非直線性のため入力データYは8ビツト以上
の濃度分解能を必要とし、例えば、濃度データで6ビツ
ト(64階調)を確保するには、入力反射率データは1
0ビア)強、濃度で8ピントの場合は、12ビツトの入
力反射率データが必要になる事が知られている(日本印
刷学会誌、第25巻第3号1988年175ページに記
載)。
Conventional technology Conventionally, in image reading devices, a document is irradiated with white light or monochromatic light, and the intensity of the reflected or transmitted light is detected by a photodiode or phototube to obtain a reading output of the document point. After that, logarithmic transformation is performed to obtain C, M,
A Y density signal is obtained. FIG. 7 shows the configuration of logarithmic transformation using the conventional method. In this example, first, an input analog signal is A/D converted by an A/D converter 701 based on a reference signal, and then input to a logarithmic conversion table (LUT) 702, and the output is converted to a logarithm for transmittance linear data. Concentration information is obtained. The characteristics of LUT 702 are shown in FIG. The LUT conversion characteristics in Figure 8 are normally as follows: If the input is Y1 and the output is D, then D = -1ogxo Y (However, Y is 0 to 1Ω
normalized value). In the case of such a conventional example, if the concentration resolution of the output signal (2) is set to 8 bits, for example,
Due to the non-linearity of the logarithmic curve, the input data Y requires a density resolution of 8 bits or more. For example, to ensure 6 bits (64 gradations) in the density data, the input reflectance data must be 1
It is known that 12-bit input reflectance data is required in the case of 0 via) strong and 8-focus density (as described in Journal of the Japan Printing Society, Vol. 25, No. 3, 1988, p. 175).

従って、第7図のA/D変換器701は、10ビット以
上の高分解能のものを使用し所望の濃度信号に変換して
いるものが多い。
Therefore, the A/D converter 701 shown in FIG. 7 often has a high resolution of 10 bits or more and converts it into a desired concentration signal.

発明が解決しようとする課題 しかし、従来の方法では、画像読み取りの高速・高精度
化を図る場合、高速高精度のA/D変換器が必要になり
、装置が高価になるか、もしくは目的に合致するA/D
変換器が実現出来ないという課題があった。
Problems to be Solved by the Invention However, with conventional methods, when attempting to achieve high-speed and high-precision image reading, a high-speed and high-precision A/D converter is required, which makes the device expensive or does not meet the purpose. Matching A/D
The problem was that a converter could not be realized.

本発明は以上の様な濃度変換時の高速・高精度A/D変
換器の必要性に鑑み、従来方法を改良し、第1の目的は
、低分解能のA/D変換器を用いても高精度の濃度変換
が出来る事である。また、第2の目的は、複数の低分解
能のA/D変換器を用いて高精度の濃度変換を行なう事
である。
In view of the need for a high-speed, high-precision A/D converter during concentration conversion, the present invention improves the conventional method. It is possible to perform highly accurate concentration conversion. A second purpose is to perform highly accurate concentration conversion using a plurality of low resolution A/D converters.

課題を解決するための手段 上記目的を達成するため、本発明の技術的解決手段は、
第1に、反射率もしくは透過率リニアのアナログ信号レ
ベルに応じて、A/D変換器の変換利得と濃度変換用テ
ーブルを切り換え、特に変換曲線の傾きが急激な低入力
レベル時のA/D変換器の変換利得を高くして等測的に
A/D変換器の変換ビット数の上昇を図るものである。
Means for Solving the Problems In order to achieve the above object, the technical solution of the present invention is as follows:
First, the conversion gain and concentration conversion table of the A/D converter are switched according to the reflectance or transmittance linear analog signal level. This is intended to increase the number of conversion bits of the A/D converter isometrically by increasing the conversion gain of the converter.

また第2には、変換利得の異なるA/D変換器を複数個
と、それぞれに対応した濃度変換用テーブルを設け、上
記アナログ信号レベルに応じて切り換えて上記第1の手
段と同じ効果を得るものである。
The second method is to provide a plurality of A/D converters with different conversion gains and density conversion tables corresponding to each one, and to switch according to the analog signal level to obtain the same effect as the first method. It is something.

作用 本発明は第1にA/D変換器への入力レベルが小さい時
は、A/D変換器の変換利得を上げる事により、飽和が
発生する事なく高い変換利得が得られる。この事は、見
かけ上、A/D変換器のビット数が多くなって変換され
たのと等価である。
Effects of the present invention Firstly, when the input level to the A/D converter is small, by increasing the conversion gain of the A/D converter, a high conversion gain can be obtained without saturation. This is apparently equivalent to conversion with an increased number of bits in the A/D converter.

入力レベルが高くなり、A/D変換器の飽和が発生する
以上のレベルでは、A/D変換器の変換利得をもどす(
低下する)事により、通常のA/D変換器のビット数で
変換される。高い変換利得で変換されたデータには、高
い変換利得用テーブルを通す事によシ、実質上使用した
A/D変換器のビット数より多いビット数を用いて濃度
変換された事になる。対数変換で細かくデータを必要と
するのは、入力値の小さい時であり、入力データの大き
い時は入力データの細かさは、変換後のデータより粗く
て良い。従って以上の様な低入力時のみA/D変換器の
ビット数を増大させるだけで充分な効果が得られる。
When the input level becomes high and exceeds the level at which saturation of the A/D converter occurs, the conversion gain of the A/D converter is restored (
(lower), it is converted using the number of bits of a normal A/D converter. By passing the data converted with a high conversion gain through a high conversion gain table, the data is density-converted using a number of bits that is substantially greater than the number of bits of the A/D converter used. Logarithmic transformation requires finer data when the input value is small, and when the input data is large, the fineness of the input data may be coarser than the data after conversion. Therefore, sufficient effects can be obtained by simply increasing the number of bits of the A/D converter only when the input is low as described above.

第2に、単一のA/D変換器の利得を切り換えるかわり
に複数個のA/D変換器を用いて、おのおのA/D変換
器の利得を異なる値に設定し、前記入力レベルの変化に
応じてA/D変換器を切り換え、又それに応じて変換利
得用テーブルの内容もそれぞれ切り換える事により上述
の第1と同様の作用を発揮できる。
Second, instead of switching the gain of a single A/D converter, a plurality of A/D converters are used and the gain of each A/D converter is set to a different value, and the input level is changed. By switching the A/D converter according to the change and switching the contents of the conversion gain table accordingly, the same effect as in the first example can be achieved.

実施例 以下第1図を参照しながら本発明の第1の実施例につい
て説明する。
EXAMPLE A first example of the present invention will be described below with reference to FIG.

原稿読取センサー(図示せず)からの反射率リニア又は
透過率リニアの信号はアナログ入力端子101へ入力さ
れる。セレクタ103へは、直接アナログ入力端子10
1からと、分割抵抗107と108により分圧されたア
ナログ入力がそれぞれ入力される。一方、基準信号入力
端子102へは、A/D変換器104へのA/D変換利
得を決めるVref端子へ直流電圧を供給する。又、分
圧抵抗109と110により分圧した直流電圧がコンパ
レーター106の比較人力Bへ入力し、もう一方の比較
人力Aは、アナログ入力端子101から直接入力される
。ここで、分圧器107.108と109.111は同
じ分圧比である必要はない。ここでコンパレーター10
6の入力AがBより小さい時はコンパレータ出力はロウ
となり、セレクタ103はA入力を選択し、A/D変換
器104で高利得A/D変換を行ない、その出力は対数
変換LUT105で高利得変換用LUTを選択して対数
変換を行なう。一方、次に、アナログ入力端子電圧が高
くなりコンパレータ入力端子AがBより高くなると、そ
の出力はノ・イとなり、セレクタ103は、B入力を選
択する。従って、A/D変換器104は、標準利得A/
D変換を行ない、その出力はやはり標準利得用の対数変
換LUTを選択して対数変換を行なう。LUT105は
、コンパレータ106の出力により、A/D変換器10
4の高利得又は標準利得動作に応じて、2種のテーブル
を切り換えて動作している。
A linear reflectance or linear transmittance signal from a document reading sensor (not shown) is input to an analog input terminal 101 . Direct analog input terminal 10 to selector 103
1 and analog inputs divided by dividing resistors 107 and 108 are respectively input. On the other hand, a DC voltage is supplied to the reference signal input terminal 102 to a Vref terminal that determines the A/D conversion gain to the A/D converter 104. Further, the DC voltage divided by the voltage dividing resistors 109 and 110 is input to the comparative human power B of the comparator 106, and the other comparative human power A is input directly from the analog input terminal 101. Here, the voltage dividers 107.108 and 109.111 do not need to have the same voltage division ratio. Here comparator 10
When the input A of 6 is smaller than B, the comparator output becomes low, the selector 103 selects the A input, the A/D converter 104 performs high gain A/D conversion, and the output is converted to high gain by the logarithmic conversion LUT 105. A conversion LUT is selected and logarithmic conversion is performed. On the other hand, when the analog input terminal voltage becomes higher and the comparator input terminal A becomes higher than B, its output becomes NO, and the selector 103 selects the B input. Therefore, the A/D converter 104 has a standard gain of A/D.
A D conversion is performed, and the output thereof is subjected to logarithmic conversion by selecting a logarithmic conversion LUT for standard gain. The LUT 105 is connected to the A/D converter 10 by the output of the comparator 106.
It operates by switching between two types of tables depending on the high gain or standard gain operation of 4.

第2図は、第1図の実施例において、アナログ入力、A
/D出力、LUT出力の関係を示す図である。201は
標準変換時のA/D変換直線、202は高利得変換時の
A/D変換直線、203は標準変換時の対数変換曲線、
204は高利得変換時の対数変換曲線を示している(図
中、破線部は入力信号レベルに応じて、A/D変換利得
とLUTの切換により発生しない。)。例えば入力値が
aの時は、図の矢印の様に高利得変換を行ないa′の変
換出力を得、入力値がbの時は、標準利得変換を行なっ
てb′の変換出力を得る。
FIG. 2 shows the analog input, A, in the embodiment of FIG.
FIG. 3 is a diagram showing the relationship between /D output and LUT output. 201 is an A/D conversion straight line during standard conversion, 202 is an A/D conversion straight line during high gain conversion, 203 is a logarithmic conversion curve during standard conversion,
204 shows a logarithmic conversion curve during high gain conversion (in the figure, the broken line portion does not occur due to switching of the A/D conversion gain and LUT depending on the input signal level). For example, when the input value is a, high gain conversion is performed as indicated by the arrow in the figure to obtain a converted output of a', and when the input value is b, standard gain conversion is performed to obtain a converted output of b'.

次に本発明の第2の実施例について説明する。Next, a second embodiment of the present invention will be described.

第3図は、第1図で、A/D変換器の利得を変えるのに
入力レベルを変化したのと異なり、変換基準電圧Vre
fを入力レベルにより切り換えるものである。この図で
301〜308は、第1図の101〜108に対応する
。基準信号入力端子301の直流電圧は分圧器307と
308によシ分圧され、セレクタ303で選択した後、
A/D変換器304のA/D変換基準電圧として利用し
、変換利得を切シ換える。切り換え信号は、アナログ入
力端子301の信号と上記分圧された直流電圧を比較器
306で比較して得て、A/D変換器304の利得切り
換えと対数変換L U T 305の切換えを行なって
いる。
In Fig. 3, unlike Fig. 1 in which the input level was changed to change the gain of the A/D converter, the conversion reference voltage Vre
f is switched depending on the input level. In this figure, 301 to 308 correspond to 101 to 108 in FIG. The DC voltage at the reference signal input terminal 301 is divided by voltage dividers 307 and 308, and after being selected by the selector 303,
It is used as an A/D conversion reference voltage of the A/D converter 304 to switch the conversion gain. The switching signal is obtained by comparing the signal at the analog input terminal 301 and the above-mentioned divided DC voltage using a comparator 306, and then switching the gain of the A/D converter 304 and switching the logarithmic conversion LUT 305. There is.

次に第4図を用いて、本発明の第3の実施例について説
明する。
Next, a third embodiment of the present invention will be described using FIG. 4.

第4図は、第2図で、A/D変換器の利得を2段階に切
シ換えていたものを発展させて、多段階にA/D変換器
の利得を切り換えたものである。
FIG. 4 is an improved version of FIG. 2 in which the gain of the A/D converter is switched in two stages, and the gain of the A/D converter is switched in multiple stages.

入力アナログ信号は、基準入力信号とで、第2のA/D
変換器406でA/D変換し、その出力は、第1のA/
D変換器404の基準電圧V r e fと、濃度変換
用L U T 405を多段階に切り換える。D/A変
換器404は、入力基準電圧402を基準にして、第2
のA/D変換器406の出力により多段階に基準電圧を
発生する。第5図は、第4図の実施例において、多段階
に濃度変換を行なっている様子を示したものである。入
力アナログ信号a、b、c点のレベルが多段階の変換曲
線でそれぞれ、a′、b′、07点に変換される様子を
示している。
The input analog signal is the reference input signal and the second A/D
The converter 406 performs A/D conversion, and the output is converted to the first A/D.
The reference voltage V r e f of the D converter 404 and the density conversion LUT 405 are switched in multiple stages. The D/A converter 404 uses a second input reference voltage 402 as a reference.
A reference voltage is generated in multiple stages based on the output of the A/D converter 406. FIG. 5 shows how density conversion is performed in multiple stages in the embodiment of FIG. 4. It shows how the levels of input analog signals at points a, b, and c are converted to points a', b', and 07, respectively, using a multi-step conversion curve.

以下、第6図を参照しながら、本発明の第4の実施例に
ついて説明する。第6図に示すようにアナログ入力端子
601からの反射率リニア又は透過率リニアの原稿読取
出力信号は2つのA/D変換器603と604へ入力さ
れる。A/D変換器603の基準電圧は、基準信号入力
端子602から入力し、A/D変換器604の基準入力
は基準信号入力端子602の電圧を分圧器608と60
9で分圧した電圧が入力され、A/D変換器604はA
/D変換器603よりも高い変換利得でA/D変換され
る。A/D変換器604が胞和しベル近くになると切換
信号発生器610により、おのおのA/D変換器603
.604の出力に接続したバッファー605.606が
切り換わり、A/D変換器603の出力が対数変換用L
UT607へ入力される。L U T 607は切換信
号発生器610の出力により2つのA/D変換器603
と604に対応した対数変換テーブルを選択するので、
第1〜5図で示した第1の実施例と同じ効果が得られる
A fourth embodiment of the present invention will be described below with reference to FIG. As shown in FIG. 6, a linear reflectance or linear transmittance original reading output signal from an analog input terminal 601 is input to two A/D converters 603 and 604. The reference voltage of the A/D converter 603 is input from the reference signal input terminal 602, and the reference input of the A/D converter 604 is inputted from the voltage of the reference signal input terminal 602 through voltage dividers 608 and 60.
The voltage divided by 9 is input, and the A/D converter 604
A/D conversion is performed with a conversion gain higher than that of the /D converter 603. When the A/D converter 604 becomes saturated and near the bell, the switching signal generator 610 switches the A/D converter 603
.. Buffers 605 and 606 connected to the output of A/D converter 604 are switched, and the output of A/D converter 603 becomes L for logarithmic conversion.
Input to UT607. The LUT 607 outputs two A/D converters 603 by the output of the switching signal generator 610.
Since we select the logarithmic conversion table corresponding to and 604,
The same effect as the first embodiment shown in FIGS. 1 to 5 can be obtained.

発明の詳細 な説明した様に、本発明の効果としては、原稿読取機な
どの輝度−濃度、すなわち対数変換をA/D変換器とL
UTで構成した場合、必要とされるA/D変換器のビッ
ト長よりも粗いビット長のA/D変換器で高い精度の輝
度−濃度変換を行なえ、安価な対数変換器を構成できる
As described in detail, the effects of the present invention include the ability to perform luminance-density, ie, logarithmic conversion, in a document reader, etc., using an A/D converter and L.
When configured with a UT, highly accurate brightness-to-density conversion can be performed using an A/D converter with a bit length coarser than the required bit length of the A/D converter, and an inexpensive logarithmic converter can be configured.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1の実施例における対数変換回路の
ブロック構成図、第2図は第1図の実施例の特性図、第
3図は本発明の第2の実施例における対数変換回路のブ
ロック構成図、第4図は本発明の第3の実施例における
対数変換回路のブロック構成図、第5図は第4図の実施
例の特性図、第6図は本発明の第4の実施例における対
数変換回路のブロック構成図、第7図は従来の対数変換
回路のブロック構成図、第8図は同特性図である。 101.301.401.601・・・アナログ入力端
子、102.302.402.602・・・基準信号入
力端子、103.303.403・・・セレクタ、10
4.304.404.406.603.604・・・A
/D変換器、105.305.405.607・・・L
UT、 107.108.109.110.307.3
08.608.609・・・分圧器、605.606・
・バッファ、610・・・切換信号発生器。 代理人の氏名 弁理士 粟野重孝 ほか1名書 図 101ア丁ログ八n満5 / 306コ:、ノぐL−pノ / 604%交峡呑 \ ざ06ノへソファ
FIG. 1 is a block diagram of a logarithmic conversion circuit according to a first embodiment of the present invention, FIG. 2 is a characteristic diagram of the embodiment of FIG. 1, and FIG. 3 is a logarithmic conversion circuit according to a second embodiment of the present invention. 4 is a block diagram of a logarithmic conversion circuit according to the third embodiment of the present invention; FIG. 5 is a characteristic diagram of the embodiment of FIG. 4; and FIG. 6 is a diagram of the fourth embodiment of the present invention. FIG. 7 is a block diagram of a logarithmic conversion circuit in the embodiment, FIG. 7 is a block diagram of a conventional logarithmic conversion circuit, and FIG. 8 is a characteristic diagram of the same. 101.301.401.601... Analog input terminal, 102.302.402.602... Reference signal input terminal, 103.303.403... Selector, 10
4.304.404.406.603.604...A
/D converter, 105.305.405.607...L
UT, 107.108.109.110.307.3
08.608.609... Voltage divider, 605.606.
- Buffer, 610... switching signal generator. Name of agent: Patent attorney Shigetaka Awano and 1 other person Book 101 Acho Log 8man 5 / 306 Ko:, Nog L-pno / 604% Kokyo Drink\ Za06nohe Sofa

Claims (2)

【特許請求の範囲】[Claims] (1)アナログ信号を入力とし、前記アナログ入力信号
のレベルにより変換利得を変化させるA/D変換手段と
、前記A/D変換手段の変換利得の切換に応じて、参照
すべきデータの切り換えを行なう対数変換テーブルとを
具備する対数変換回路。
(1) An A/D converter that receives an analog signal and changes the conversion gain depending on the level of the analog input signal, and switches the data to be referenced in accordance with the switching of the conversion gain of the A/D converter. A logarithmic conversion circuit comprising a logarithmic conversion table for performing the logarithmic conversion.
(2)アナログ信号を入力とし、変換利得の異なる複数
個のA/D変換手段と、前記アナログ入力信号のレベル
に応じて、前記個々のA/D変換器の変換利得に対応し
た参照すべきデータの切り換えを行なう対数変換テーブ
ルとを具備する対数変換回路。
(2) A plurality of A/D conversion means that input an analog signal and have different conversion gains, and a reference signal corresponding to the conversion gain of each A/D converter according to the level of the analog input signal. A logarithmic conversion circuit comprising a logarithmic conversion table for switching data.
JP63174563A 1988-07-13 1988-07-13 Logarithm converting circuit Pending JPH0223475A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63174563A JPH0223475A (en) 1988-07-13 1988-07-13 Logarithm converting circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63174563A JPH0223475A (en) 1988-07-13 1988-07-13 Logarithm converting circuit

Publications (1)

Publication Number Publication Date
JPH0223475A true JPH0223475A (en) 1990-01-25

Family

ID=15980747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63174563A Pending JPH0223475A (en) 1988-07-13 1988-07-13 Logarithm converting circuit

Country Status (1)

Country Link
JP (1) JPH0223475A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03111033A (en) * 1989-09-26 1991-05-10 Toshiba Corp Magnetic resonance imaging device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03111033A (en) * 1989-09-26 1991-05-10 Toshiba Corp Magnetic resonance imaging device

Similar Documents

Publication Publication Date Title
KR890006089A (en) Digital picture signal encoding device and decoding device
KR890011227A (en) Digital to Analog Converter
US4211999A (en) Converter for converting a high frequency video signal to a digital signal
GB1581819A (en) Apparatus for modifying the scale of a logarithmic signal
JPH0223475A (en) Logarithm converting circuit
EP0294468A1 (en) Digital receiver with dual references
US4979043A (en) Video signal processing circuit
JPS62204617A (en) High resolution analog-digital converter
JPH031709A (en) Variable resistance circuit and variable gain amplifier
US5969659A (en) Analog to digital converters with extended dynamic range
GB2135852A (en) Arrangement for converting an analog video signal into a two-level signal
JPS62144220A (en) capacitive keyboard switch
JP3313664B2 (en) Test method for semiconductor device
KR950010889B1 (en) Frequency selecting circuit
JPH07154259A (en) Analog / digital conversion circuit
JPS6163163A (en) Signal binary coding device
JPS647538B2 (en)
JPH043582A (en) Image scanner
JPS621369A (en) Shading correction circuit for facsimile equipment
JP2616196B2 (en) Control device abnormality detection circuit
KR920004818Y1 (en) Linear control circuit of sound output
JPH0243813A (en) A/d converter
KR950000354Y1 (en) Gain selection circuit of input signal
JPH05232188A (en) Testing circuit for semiconductor integrated circuit
JPS63146513A (en) Method and apparatus for analog/digital