JPH02235365A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH02235365A JPH02235365A JP1056608A JP5660889A JPH02235365A JP H02235365 A JPH02235365 A JP H02235365A JP 1056608 A JP1056608 A JP 1056608A JP 5660889 A JP5660889 A JP 5660889A JP H02235365 A JPH02235365 A JP H02235365A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- lead
- based alloy
- alloy
- lead frame
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/884—Die-attach connectors and bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体素子を載置して半導体装置を組立てる
ために用いられる半導体装置用リードフレーム(以下、
リードフレームと称する)に関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a lead frame for a semiconductor device (hereinafter referred to as
(referred to as lead frames).
(従来の技術〕
第5図は従来のリードフレームを示す斜視図であり、リ
ン青銅等の銅系合金や42アロイ等の鉄系合金の板材を
用いて必要なパターンにエッチングまたは金型でパンチ
ングを行フたものである。図において、(1)は半導体
素子が載置されるアイランド部、(2)は上記半導体素
子を外部に導出して電気的導通をとるためのリード部、
(3)はリードフレームの両端部に配置された枠、(4
) , (5)はそれぞれリード部(2),アイランド
部(1)を枠(3)に連結して支持するタイバー、支持
腕であ名。(Prior art) Fig. 5 is a perspective view showing a conventional lead frame, in which a plate material of a copper alloy such as phosphor bronze or an iron alloy such as 42 alloy is used to form a required pattern by etching or punching with a mold. In the figure, (1) is an island part on which a semiconductor element is placed, (2) is a lead part for leading out the semiconductor element to the outside and establishing electrical continuity.
(3) is a frame placed at both ends of the lead frame;
) and (5) are tie bars and support arms that connect and support the lead part (2) and island part (1) to the frame (3), respectively.
第6図は第5図のリードフレーム上に半導体素子が組立
てられた状態を示す斜視図であり、シリコンで作られた
半導体素子(6)がアイランド部(1)上に載置されて
接合材(7)により固着されている。半導体素子(6)
の電極(8)とリード部(2)との間は金属細線(9)
がボンディングされて電気的につながっていイバー(4
)、支持腕(5)、枠(3)の切断除去、リード部《2
》の曲げが行なわれて半導体装置が製造される。FIG. 6 is a perspective view showing a semiconductor element assembled on the lead frame of FIG. 5, in which a semiconductor element (6) made of silicon is placed on an island part (1) and a bonding material (7) is fixed. Semiconductor element (6)
There is a thin metal wire (9) between the electrode (8) and the lead part (2).
are bonded and electrically connected to each other (4).
), support arm (5), cutting and removal of frame (3), lead part <<2
] is performed to manufacture the semiconductor device.
次に、動作について説明する。半導体素子(6)に通電
するとここで熱が発生し、各部に伝わって温度が上昇す
る。この熱はリード部(2)やパッケージ(図示せず)
から外部に放散される。ところで、材料が異る各部の線
膨張率はそれぞれ異なり、半導体素子(6)はアイラン
ド部(1)に固着されているので、両者の線膨張率の差
と温度変化に応じて応力が生じる。Next, the operation will be explained. When the semiconductor element (6) is energized, heat is generated there, transmitted to various parts, and the temperature rises. This heat is absorbed by the lead part (2) and the package (not shown).
is emitted to the outside. By the way, the coefficients of linear expansion of each part made of different materials are different, and since the semiconductor element (6) is fixed to the island part (1), stress is generated depending on the difference in coefficient of linear expansion between the two and changes in temperature.
第7図は従来の他のリードフレームを示す斜視図であり
、アイランド部(1)がプレス加工により、図において
下方に沈められている。第8図は第7図のリードフレー
ム上に半導体素子が組立てられた状態を示す断面図であ
る。第6図の例では、金属細線(9》の両端で高さ方向
に段差が大きいのでボンデングされた金属細線(9)同
志が近接し過ぎてしまうことがあり、また、図において
リード部(2)よりも上方の寸法が大きくなるので、リ
ード部(2)をパッケージ(図示せず)の厚さ方向の中
央から引き出そうとするとパッケージ(図示せず)の寸
法が大きくなるが、第8図の場合は半導体素子(1)の
位置が低くなるのでそのようなことはない。FIG. 7 is a perspective view showing another conventional lead frame, in which the island portion (1) is sunk downward in the figure by press working. FIG. 8 is a sectional view showing a state in which a semiconductor element is assembled on the lead frame of FIG. 7. In the example shown in Fig. 6, there is a large step in the height direction at both ends of the thin metal wire (9), so the bonded thin metal wires (9) may be too close to each other. ), so if you try to pull out the lead part (2) from the center of the package (not shown) in the thickness direction, the size of the package (not shown) will become larger; In this case, since the position of the semiconductor element (1) is low, such a situation will not occur.
従来のリードフレームは以上のように単一材料で構成さ
れているので、427ロイなどの鉄系合金を用いた場合
は熱伝導率が小さいために、半導体素子で発生した熱の
外部への放散が悪い等の問題があり、また、銅系合金を
用いた場合はシリコンなどで作られた半導体素子と比較
して線膨張率が非常に大きいために、半導体素子に生じ
る応力が大きくなって特性が変化したり、著しいときは
半導体素子に割れが生じることもあるなどの問題点があ
り、最近の半導体素子への高性能化の要請などにより、
半導体素子のサイズが大きくなったようなときは上記の
問題点はますます顕著になる傾向がある。Conventional lead frames are made of a single material as described above, and when iron-based alloys such as 427 Roy are used, their thermal conductivity is low, making it difficult for the heat generated in the semiconductor element to dissipate to the outside. In addition, when copper-based alloys are used, their coefficient of linear expansion is much higher than that of semiconductor elements made of silicon, etc., which increases the stress generated in the semiconductor elements and impairs their characteristics. However, due to the recent demand for higher performance of semiconductor devices,
As the size of semiconductor devices increases, the above problems tend to become more noticeable.
この発明は上記のような問題点を解消するためになされ
たもので、半導体素子に生じる応力を小さくでき、かつ
、熱放散の良いリードフレームを得ることを目的とする
。This invention was made to solve the above-mentioned problems, and aims to provide a lead frame that can reduce the stress generated in a semiconductor element and has good heat dissipation.
この発明に係るリードフレームは、アイランド部とリー
ド部をそれぞれ第1および第2の材料で形成して、その
第1の材料として第2の材料よりも線膨張率が小さいも
のを用い、そして第2の材料として第1の材料よりも熱
伝導率が大きいものを用いたものである。In the lead frame according to the present invention, the island portion and the lead portion are respectively formed of a first material and a second material, the first material is made of a material having a coefficient of linear expansion smaller than that of the second material, and the first material is made of a material having a smaller linear expansion coefficient than the second material. As the second material, a material having higher thermal conductivity than the first material is used.
この発明におけるリードフレームは、アイランド部に用
いられている第1の材料の線膨張率が小さいので半導体
素子に用いられているシリコン等の線膨張率と近くなっ
て、半導体素子に生じる応力が低減され、かつ、第2の
材料の熱伝導率が大きいので半導体素子で発生する熱の
外部への放散が良好となる。つまり、上記両材料それぞ
れの好ましい特性を利用することができる。In the lead frame of the present invention, the linear expansion coefficient of the first material used for the island portion is small, so the linear expansion coefficient is close to that of silicon, etc. used in the semiconductor element, and the stress generated in the semiconductor element is reduced. In addition, since the second material has a high thermal conductivity, heat generated in the semiconductor element can be efficiently dissipated to the outside. In other words, the preferable characteristics of both of the above materials can be utilized.
以下、この発明の一実施例を図について説明する。第1
図はこの発明の一実施例によるリードフレームを示す斜
視図であり、″図において、αQは第1の材料としての
421ロイ等の鉄系合金、αりは第2の材料としてのリ
ン青銅等の銅系合金で、両者を重ね合わせて複合した板
状のクラッド材をエッチングすることにより、図に示す
ような形状に形成したものである。(1)〜(5)は第
5図の場合と同様の形状.機能を有するが、アイランド
部(1)と支持腕(5)は鉄系合金QOで、リード部(
2)とタイパー(4)は銅系合金(ロ)で、そして、枠
(3)は鉄系合金αQと銅系合金αカを重ね合せたまま
で形成されている。第2図は第1図の1−1線に沿った
断面図であり、アイランド部(1),リード部(2》は
2種類の材料を重ね合わせたクラッド材からそれぞれ一
方の材料を除去して形成されているので、図において上
下方向に互にずれている。An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure is a perspective view showing a lead frame according to an embodiment of the present invention. The shape shown in the figure is formed by etching a composite plate-shaped cladding material made of a copper-based alloy. (1) to (5) are the cases shown in Figure 5. It has the same shape and function as , but the island part (1) and support arm (5) are made of iron-based alloy QO, and the lead part (
2) and the tieper (4) are made of a copper-based alloy (b), and the frame (3) is formed by overlapping the iron-based alloy αQ and the copper-based alloy αQ. Figure 2 is a cross-sectional view taken along line 1-1 in Figure 1, and the island part (1) and lead part (2) are made by removing one material from the cladding material, which is made by superimposing two types of materials. Since they are formed in parallel, they are shifted from each other in the vertical direction in the figure.
次に製造方法について説明する。第3図は第1図のリー
ドフレームの製造方法を示す第2図に相当する所の断面
図であり、工程順に同図囚〜(匂で示す。同図(4)は
鉄系合金(IQと銅系合金(ロ)が重ね合わされたクラ
ッド材で、同図(6)のように第1のマスク(自)を銅
系合金(ロ)側のリード部(2),タイパー(4)およ
び枠(3)に相当する所に形成し、矢印の方向からクラ
ッド材の両材料の境界面までエッチングすることにより
、同図(C)のように銅系合金(ロ)を選択的に除去す
る。次に、同図の)のように第2のマスク(至)を鉄系
合金o1側のアイランド部(1).支持腕(5)および
枠(3)に相当する所に形成し、矢印の方向からクラッ
ド材の両材料の境界面までエッチングすることにより、
同図(E)のように鉄系合金00を選択的に除去して第
2図と同様となる。Next, the manufacturing method will be explained. Fig. 3 is a cross-sectional view of a part corresponding to Fig. 2 showing the method for manufacturing the lead frame of Fig. 1. As shown in the same figure (6), the first mask (self) is connected to the lead part (2), tieper (4) and The copper-based alloy (B) is selectively removed by forming it in the area corresponding to the frame (3) and etching it from the direction of the arrow to the interface between the two cladding materials, as shown in Figure (C). Next, as shown in ) in the same figure, a second mask (to) is formed on the iron-based alloy o1 side at a location corresponding to the island part (1), support arm (5) and frame (3), and By etching from the direction of the cladding material to the interface between both materials,
As shown in FIG. 2(E), the iron-based alloy 00 is selectively removed, resulting in a structure similar to that shown in FIG. 2.
上記のリードフレームを用いた半導体装置においては、
アイランド部(1)は鉄系合金αQで形成されているの
で、銅系合金αつよりも線膨張率が小さも)即ち、銅系
合金(ロ)の線膨張率はシリコンのそれの5〜10倍に
なるのに対して、鉄系合金顛の場合はシリコンの1〜1
.5倍になり、シリコンの線膨張係数に近くなる。また
、リード部(2》は銅系合金(ロ)で形成されているの
で鉄系合金よりも熱伝導率が大きく、従って、半導体素
子で発生する熱を外部へ良く伝える。更にこの実施例で
は、銅系合金αηは塑性変形し易いので、Jリードのよ
うな場合でも曲げ加工が容易となる。また、第1図,第
2図で分かるようにアイランド部(11はリード部(2
)に比べて、図において下方に沈んでいるが、第7図の
場合はプレスによる支持腕(6)の曲げ加工を行なうの
に対して、この実施例ではエッチング加工であるので沈
め寸法の精度が良いという効果もある。In the semiconductor device using the above lead frame,
Since the island portion (1) is formed of the iron-based alloy αQ, its coefficient of linear expansion is smaller than that of the copper-based alloy α. In the case of iron-based alloys, it is 1 to 1 times as large as silicon.
.. The coefficient of linear expansion is 5 times that of silicon, which is close to that of silicon. Furthermore, since the lead portion (2) is made of a copper-based alloy (b), it has a higher thermal conductivity than an iron-based alloy, and therefore conducts the heat generated in the semiconductor element to the outside.Furthermore, in this embodiment, , copper-based alloy αη is easily plastically deformed, so it can be easily bent even in cases such as J leads.In addition, as can be seen in Figures 1 and 2, the island part (11 is the lead part (2
), but in the case of Fig. 7, the support arm (6) is bent by a press, whereas in this example, it is etched, so the accuracy of the sinking dimension is There is also the effect that it is good.
第4図はこの発明の他の実施例によるリードフレームの
斜視図で、リード部(2)にアイランド部(1)まで達
してこれと重なり合う延長部(自)を設けたものであり
、半導体素子で発生する熱がリード部(2)に更に良く
伝わり、一従って、外部への熱放散が良好となる。FIG. 4 is a perspective view of a lead frame according to another embodiment of the present invention, in which a lead part (2) is provided with an extension part (self) that reaches and overlaps the island part (1), and the semiconductor element The heat generated in the lead portion (2) is better transmitted to the lead portion (2), and therefore heat dissipation to the outside is improved.
なお、上記実施例では第2の材料としてリン青銅を示し
たが、錫入り銅,銅ニッケル合金などを用いてもよい。In addition, although phosphor bronze was shown as the second material in the above embodiment, tinned copper, copper-nickel alloy, etc. may also be used.
以上のように、この発明によれば、アイランド部とリー
ド部をそれぞれ第1および第2の材料で形成して、その
第1の材料として第2の材料よりも線膨張率が小さいも
のを用い、そして第2の材料として第1の材料よりも熱
伝導率が大きいものを用いるよう構成したので、それぞ
れの材料の好ましい特性を利用することができ、アイラ
ンド部の線膨張率が半導体素子のそれに近いために半導
体素子に生じる応力が小さ《なり、かつ、リード部の熱
伝導率が大きいために半導体素子で発生する熱のリード
部からの熱放散が良くなるという効果がある。As described above, according to the present invention, the island portion and the lead portion are formed of the first and second materials, respectively, and the first material is made of a material having a smaller coefficient of linear expansion than the second material. Since the second material is configured to have a higher thermal conductivity than the first material, it is possible to utilize the favorable characteristics of each material, and the coefficient of linear expansion of the island portion is equal to that of the semiconductor element. Because they are close to each other, stress generated in the semiconductor element is reduced, and because the lead portion has high thermal conductivity, heat generated in the semiconductor element is effectively dissipated from the lead portion.
第1図はこの発明の一実施例によるリードフレームの斜
視図、第2図は第1図の1−1線に沿った断面図、第3
図は第1図のリードフレームの製造方法を示す断面図、
第4図はこの発明の他の実施例によるリードフレームの
斜視図、第5図は従来のリードフレームの斜視図、第6
図は第5図のリードフレーム上に半導体素子が組立てら
れた状態を示す斜視図、I!7図は従来の他のリードフ
レームを示す斜視図、第8図は第7図のリードフレーム
上に半導体素子が組立てられた状態を示す断面図である
。
図において、《1)はアイランド部、(2)はリード部
、(6)は半導体素子、αQは鉄系合金、(ロ)は銅系
合金である。
なお、各図中同一符号は同一または相当部分を示す。
代理人 弁理士 大 岩 増 雄
牽
ヱ
葛4r5A
第
図
兎
図
6:鴨千嚢テ
第3閲
第
図
第
8図
1事件の表示
平成1年特許願第056608号
2発明の名称
半導体装置用リードフレーム
3補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目2番3号
名 称(601 1三菱電機株式会社代表者志岐守
哉
4代理人
住 所 東京都千代田区丸の内二丁目2番3号
三菱電機株式会社内
氏 名(7375)弁理士 大岩 増 雄 他2名5
補正の対象
明細書の発明の詳細な説明の欄
図面《第6図および第8図〉
?補正の内容
(1)明細書第3ページ第14行に「同志が」とあるの
を「が半導体素子(6)のコーナーに」と訂正する.
■明細書第3ページ18行〜19行に「パッケージ(図
示せず)の寸法が大きくなる」とあるのをr図において
半導体素子(6)の上側とアイランド部{1)の下■側
とでモールドされた樹脂(図示せず)の厚さが異なって
、パッケージが反る方向の力が生じる」と訂正する。
(3)図面(第6図および第8図)を別紙の通り訂正す
る.
(金属細線(9)のリード部(21側の先端の盛り上り
を抹消した.)
7添付書類の目録
図面(第6図および第8図)
以上FIG. 1 is a perspective view of a lead frame according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line 1-1 in FIG. 1, and FIG.
The figure is a cross-sectional view showing the manufacturing method of the lead frame shown in Figure 1.
FIG. 4 is a perspective view of a lead frame according to another embodiment of the present invention, FIG. 5 is a perspective view of a conventional lead frame, and FIG.
The figure is a perspective view showing a semiconductor element assembled on the lead frame of FIG. 5, I! FIG. 7 is a perspective view showing another conventional lead frame, and FIG. 8 is a sectional view showing a semiconductor element assembled on the lead frame of FIG. In the figure, <<1) is an island portion, (2) is a lead portion, (6) is a semiconductor element, αQ is an iron-based alloy, and (b) is a copper-based alloy. Note that the same reference numerals in each figure indicate the same or corresponding parts. Agent Patent Attorney Masu Oiwa Yuken Ekatsu 4R5A Figure 6: Kamo Senbukuro 3 Review Figure 8 Figure 1 Display of the Case 1999 Patent Application No. 056608 2 Name of Invention Lead for Semiconductor Device Frame 3 Relationship with the case of the person making the amendment Patent Applicant Address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601 1) Mitsubishi Electric Corporation Representative Moriya Shiki 4 Agent Address Marunouchi, Chiyoda-ku, Tokyo 2-2-3 Mitsubishi Electric Corporation Name (7375) Patent attorney Masuo Oiwa and 2 others 5
Drawings (Figures 6 and 8) in the detailed description of the invention in the specification to be amended? Details of the amendment (1) In the 14th line of page 3 of the specification, the phrase ``comrade'' is corrected to ``in the corner of the semiconductor element (6).'' ■ On page 3 of the specification, lines 18 and 19, it says that "the dimensions of the package (not shown) will be larger" is shown in the upper side of the semiconductor element (6) and the lower ■ side of the island part {1) in figure r. The thickness of the molded resin (not shown) is different, creating a force that causes the package to warp.'' (3) Correct the drawings (Figures 6 and 8) as shown in the attached sheet. (The lead part of the thin metal wire (9) (the bulge at the tip on the 21 side has been erased.) 7 Attached document catalog drawings (Figures 6 and 8)
Claims (1)
素子を外部に導出するリード部とから成るものにおいて
、アイランド部は第1の材料で形成され、リード部は第
2の材料で形成されて、上記第1の材料は上記第2の材
料よりも線膨張率が小さく、上記第2の材料は上記第1
の材料よりも熱伝導率が大きいことを特徴とする半導体
装置用リードフレーム。In a device comprising an island portion on which a semiconductor element is placed and a lead portion leading the semiconductor element to the outside, the island portion is formed of a first material, the lead portion is formed of a second material, The first material has a linear expansion coefficient smaller than that of the second material, and the second material has a coefficient of linear expansion smaller than that of the second material.
A lead frame for semiconductor devices characterized by higher thermal conductivity than other materials.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1056608A JP2754675B2 (en) | 1989-03-08 | 1989-03-08 | Lead frame for semiconductor device, method of manufacturing the same, and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1056608A JP2754675B2 (en) | 1989-03-08 | 1989-03-08 | Lead frame for semiconductor device, method of manufacturing the same, and semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9214529A Division JPH1074883A (en) | 1997-08-08 | 1997-08-08 | Lead frame for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02235365A true JPH02235365A (en) | 1990-09-18 |
| JP2754675B2 JP2754675B2 (en) | 1998-05-20 |
Family
ID=13031957
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1056608A Expired - Lifetime JP2754675B2 (en) | 1989-03-08 | 1989-03-08 | Lead frame for semiconductor device, method of manufacturing the same, and semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2754675B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999044234A1 (en) * | 1998-02-27 | 1999-09-02 | Robert Bosch Gmbh | Lead frame device and method for producing the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5034363A (en) * | 1973-07-30 | 1975-04-02 | ||
| JPS5662345A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Load frame and semiconductor device |
| JPS62136059A (en) * | 1985-12-09 | 1987-06-19 | Mitsubishi Electric Corp | Lead frame for resin sealed semiconductor device |
| JPS62213145A (en) * | 1986-03-13 | 1987-09-19 | Sumitomo Electric Ind Ltd | Lead frame for semiconductor device |
| JPS6339950U (en) * | 1986-09-01 | 1988-03-15 |
-
1989
- 1989-03-08 JP JP1056608A patent/JP2754675B2/en not_active Expired - Lifetime
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5034363A (en) * | 1973-07-30 | 1975-04-02 | ||
| JPS5662345A (en) * | 1979-10-26 | 1981-05-28 | Hitachi Ltd | Load frame and semiconductor device |
| JPS62136059A (en) * | 1985-12-09 | 1987-06-19 | Mitsubishi Electric Corp | Lead frame for resin sealed semiconductor device |
| JPS62213145A (en) * | 1986-03-13 | 1987-09-19 | Sumitomo Electric Ind Ltd | Lead frame for semiconductor device |
| JPS6339950U (en) * | 1986-09-01 | 1988-03-15 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6528868B1 (en) | 1998-02-21 | 2003-03-04 | Robert Bosch Gmbh | Lead frame device and method for producing the same |
| WO1999044234A1 (en) * | 1998-02-27 | 1999-09-02 | Robert Bosch Gmbh | Lead frame device and method for producing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2754675B2 (en) | 1998-05-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP5225513B2 (en) | Press-fit terminals and semiconductor devices | |
| CN101553920B (en) | Methods and apparatus for a quad flat no-lead (QFN) package | |
| JPH06132453A (en) | Semiconductor device and manufacturing method thereof | |
| JP3776427B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2009009957A (en) | Semiconductor device | |
| JPH03177060A (en) | Lead frame for semiconductor device | |
| JP2005142554A (en) | Lead frame and semiconductor package manufacturing method using the same | |
| JP2009038196A (en) | Electronic device and wire bonding method | |
| JPS6215844A (en) | Semiconductor lead frame | |
| JP2005311214A (en) | Semiconductor device and manufacturing method thereof | |
| JP4439143B2 (en) | Resin-sealed semiconductor device | |
| JP5569097B2 (en) | Semiconductor device and lead frame | |
| JP4111199B2 (en) | Semiconductor package and method for mounting the same on a circuit board | |
| JP2754675B2 (en) | Lead frame for semiconductor device, method of manufacturing the same, and semiconductor device | |
| US6928850B2 (en) | Method and tooling for z-axis offset of lead frames | |
| JP2008016469A (en) | Semiconductor device | |
| JP4556732B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2017028131A (en) | Package mounting body | |
| JPH0735403Y2 (en) | Lead frame | |
| JPH1074883A (en) | Lead frame for semiconductor device | |
| JPH05175411A (en) | Lead frame for electronic-part mounting board | |
| JPH06120403A (en) | Lead frame for mounting electronic circuit elements | |
| JP3805933B2 (en) | Island structure of lead frame | |
| JP2564969B2 (en) | Lead frame | |
| JP3545584B2 (en) | Method for manufacturing semiconductor device |