JPH0223652A - Manufacture of semiconductor element - Google Patents
Manufacture of semiconductor elementInfo
- Publication number
- JPH0223652A JPH0223652A JP63172671A JP17267188A JPH0223652A JP H0223652 A JPH0223652 A JP H0223652A JP 63172671 A JP63172671 A JP 63172671A JP 17267188 A JP17267188 A JP 17267188A JP H0223652 A JPH0223652 A JP H0223652A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- drain
- source
- substrate
- channel stopper
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 239000012535 impurity Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims description 12
- 238000009792 diffusion process Methods 0.000 abstract description 4
- 239000013078 crystal Substances 0.000 abstract description 2
- 230000007547 defect Effects 0.000 abstract description 2
- 230000015572 biosynthetic process Effects 0.000 abstract 1
- 238000009413 insulation Methods 0.000 abstract 1
- 108091006146 Channels Proteins 0.000 description 19
- 230000015556 catabolic process Effects 0.000 description 5
- 238000010438 heat treatment Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体素子の製造方法に係り、詳しくはＬＤＤ
構造のＣＭＯ３ＩＣの製造方法に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for manufacturing a semiconductor device, and specifically relates to a method for manufacturing a semiconductor device.
The present invention relates to a method for manufacturing a CMO3IC structure.
従来、この種（７）ＣＭＯ３ＩＣは、「昭和６０年４・
月、沖電気研究開発Ｖｏｌ、 ５２ 、 Ｎｏ、２ 、
第９７〜１０２頁ｊに開示されるものがある。これを第
３図にその平面図及び第４図に断面図を示して説明する
。Conventionally, this type (7) CMO3IC was developed in April 1985.
Moon, Oki Electric Research and Development Vol. 52, No. 2,
There is something disclosed on pages 97-102j. This will be explained by showing a plan view in FIG. 3 and a sectional view in FIG. 4.
即ち、２１は濃度が５×１０目〜５ Ｘ １０”ｃｍ−
”のＮ型基板であり、この基１２１上部所定位置に、表
面濃度が約１０ ” ’ ｃｍ −”のＰ型ソース層２
２とＰ型ドレイン層２３とが形成され、上記基板２１上
に、これらソース層２２及びドレイン層２３を跨ぐよう
にゲート酸化膜２４とゲート電極２５とが順次形成され
、Ｐ型ＭＯ３）ランジスタ（以下ＰＭＯＳという）が形
成されている。そして、かがるＰＭＯＳは、基板２１上
の表面濃度が１０”ｃｎｒ”のオーダーを有するＮ型チ
ャネルストッパー層２６と基板電位を固定するためのＮ
型基板電位固定層２７とにより囲繞されている。That is, 21 has a density of 5 x 10 to 5 x 10"cm-
A P-type source layer 2 with a surface concentration of about 10 cm - is placed at a predetermined position above the base 121.
2 and a P-type drain layer 23 are formed, and a gate oxide film 24 and a gate electrode 25 are sequentially formed on the substrate 21 so as to straddle these source layer 22 and drain layer 23, and a P-type MO3) transistor ( (hereinafter referred to as PMOS) is formed. The PMOS to be bent includes an N-type channel stopper layer 26 on the substrate 21 having a surface concentration on the order of 10"cnr" and an N-type channel stopper layer 26 on the substrate 21 for fixing the substrate potential.
It is surrounded by a type substrate potential fixing layer 27.
更に、上記基板２１上部のチャネルストッパー層２６に
隣接する位置に、Ｐウェル２８が形成され、このＰウェ
ル２８上部所定部には、表面濃度が１０” 〜１０”ｃ
ｌ’のＮ型ソース層２９及びＮ型１１４７層３０が形成
され、高耐圧において、ドレイン電界を緩和するため、
上記ドレイン層３０を囲み表面濃度が１０ ” ｃｗ
−’の低濃度ドレイン層３１が形成されると同時に、ゲ
ート長を一定とするため、上記ソース層２９に部分が重
合する低濃度ソース層３２が形成されている。更に、Ｐ
ウェル２８上には、上記ドレイン層３０．３１及びソー
ス層２９．３２を跨ぐようにゲート酸化膜３３とゲート
電極３４とが順次形成され、Ｎ型ＭＯ３）ランジスタ（
以下ＮＭＯＳという）が形成されている。又、このＮＭ
ＯＳは、Ｐウェル２８上部に形成されたチャネルストッ
パー層３５及びＰウェル電位固定層３６により囲繞され
て居り、このチャネルストッパー３５及びＰウェル電位
固定層３６は、ＰＭＯＳのソース層２２及びドレイン層
２３と同時に形成されると共に、上記チャネルストッパ
ー層２６及び基板電位固定層２７は、ＮＭＯＳのソース
層２９及びドレイン層３０と同時に形成されていた。Further, a P well 28 is formed at a position adjacent to the channel stopper layer 26 on the upper part of the substrate 21, and a predetermined portion of the upper part of the P well 28 has a surface concentration of 10" to 10"c.
l' N-type source layer 29 and N-type 1147 layer 30 are formed to relax the drain electric field at high breakdown voltage.
Surrounding the drain layer 30, the surface concentration is 10'' cw
At the same time as the low concentration drain layer 31 of -' is formed, a low concentration source layer 32 is formed which partially overlaps the source layer 29 in order to keep the gate length constant. Furthermore, P
A gate oxide film 33 and a gate electrode 34 are sequentially formed on the well 28 so as to straddle the drain layer 30.31 and the source layer 29.32, and an N-type MO3) transistor (
(hereinafter referred to as NMOS) is formed. Also, this NM
The OS is surrounded by a channel stopper layer 35 and a P-well potential fixing layer 36 formed on the top of the P-well 28, and the channel stopper 35 and P-well potential fixing layer 36 are surrounded by the source layer 22 and drain layer 23 of the PMOS. The channel stopper layer 26 and substrate potential fixing layer 27 were formed simultaneously with the NMOS source layer 29 and drain layer 30.
然し乍ら、上述した従来のＣＭＯ３ＩＣにおいては、Ｐ
ＭＯＳにおけるチャネルストッパー層２６及びドレイン
層２３が共に高濃度であり、而の両者は自己整合的に形
成されないため、マスク合せマージンが小さい場合は、
合せずれによって、高濃度接合となり、接合耐圧が小さ
くなるので、比較的高耐圧を必要とするデバイスにおい
ては、合せマージンを大きくしなければならず、高密度
の集積化ができないという問題点があった。However, in the conventional CMO3IC mentioned above, P
Both the channel stopper layer 26 and the drain layer 23 in the MOS have a high concentration, and since they are not formed in a self-aligned manner, if the mask alignment margin is small,
Misalignment results in a high-concentration junction, which reduces the junction breakdown voltage. Therefore, in devices that require a relatively high breakdown voltage, the alignment margin must be increased, which poses the problem of not being able to achieve high-density integration. Ta.
本発明の目的は、上述の問題点に鑑み、ドレイン耐圧の
低下が防止できると共に、マスクの合せマージンを小さ
くできる半導体素子の製造方法を提供するものである。SUMMARY OF THE INVENTION In view of the above-mentioned problems, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can prevent a decrease in drain breakdown voltage and reduce a mask alignment margin.
本発明は上述した目的を達成するため、ＬＤＤ構造のＮ
ＭＯＳ及びＰＭＯＳを有する半導体素子の製造方法にお
いて、基板所定部にドレイン層及びソース層を形成する
と共に、上記基板表面に絶縁膜を成長形成する工程と、
該絶縁膜の所定部を開孔した後、不純物を打ち込み、低
濃度ドレイン層及び低濃度ソース層並びに上記ドレイン
層を囲む低濃度のチャネルストッパー層を形成する工程
と、更に、上記絶縁膜を成長させ、その所定部を開孔し
た後、再度不純物を打ち込み、上記低濃度ドレイン層に
囲まれた高濃度ドレイン層及び上記低濃度ソース層に部
分が重合する高濃度ソース層を形成すると共に、上記チ
ャネルスト・ツノイー層とパターン的に接続し、上記ソ
ース層を囲む高濃度の基板電位固定層を形成する工程と
を含むものである。In order to achieve the above-mentioned object, the present invention
In a method of manufacturing a semiconductor device having a MOS and a PMOS, a step of forming a drain layer and a source layer on a predetermined portion of a substrate and growing an insulating film on the surface of the substrate;
After opening a predetermined portion of the insulating film, a step of implanting impurities to form a low concentration drain layer, a low concentration source layer, and a low concentration channel stopper layer surrounding the drain layer, and further growing the insulating film. After opening a hole in a predetermined portion, impurities are implanted again to form a highly doped drain layer surrounded by the lightly doped drain layer and a highly doped source layer partially overlapping with the lightly doped source layer. The method includes the step of forming a high concentration substrate potential fixing layer that is connected to the channel strike layer in a pattern and surrounds the source layer.
本発明においては、第１ＭＯ３のドレイン層は低濃度の
チャネルストッパー層に囲まれるので、拡散層の拡大が
抑制され、上記ドレイン層のマスク合せマージンは小さ
くなる。而も上記チャネルストッパー層は、第２ＭＯ３
の低濃度ドレイン層及びソース層と共に形成されるので
、工数の増大はない。In the present invention, since the first MO3 drain layer is surrounded by a low concentration channel stopper layer, expansion of the diffusion layer is suppressed and the mask alignment margin for the drain layer is reduced. Moreover, the channel stopper layer is composed of the second MO3
Since it is formed together with the lightly doped drain layer and source layer, there is no increase in the number of man-hours.
〔実施例］
本発明製造方法に係る一実施例を、第１図にＣＭＯ３の
工程断面図及び第２図に同平面図を示して説明する。[Example] An example of the manufacturing method of the present invention will be described with reference to FIG. 1 showing a cross-sectional view of the CMO3 process and FIG. 2 showing a plan view thereof.
先ず、第１図（ａ）に示す如く、濃度が５ ＸＩＯ＋４
〜５Ｘ１０”ｃ＋ｎ弓のＮ型Ｓｔ基板１の上部所定位置
に、表面不純物濃度が１０′９〜１０”ｃｍ−３のＰＭ
ＯＳのソース層２及びドレイン層３並びにＮＭＯＳのＰ
ウェル４を夫々形成すると同時に、このＰウェル４の上
部所定位置に、ＮＭＯＳへの寄生ＭＯ３防止用のＰ型チ
ャネルストッパー層５及びＰウェル電位固定層６を、形
成し、熱処理により上記ｓｉ基板１上には、フィールド
酸化膜７を成長形成する。First, as shown in Figure 1(a), the concentration is 5XIO+4
PM with a surface impurity concentration of 10'9 to 10" cm
Source layer 2 and drain layer 3 of OS and P of NMOS
At the same time as forming the wells 4, a P-type channel stopper layer 5 and a P-well potential fixing layer 6 for preventing parasitic MO3 to the NMOS are formed at predetermined positions above the P-well 4, and the Si substrate 1 is heated by heat treatment. A field oxide film 7 is grown thereon.
次に、第１図（ｂ）に示す如く、ホトリソ技術を以て上
記フィールド酸化膜７の所定部を開孔し、Ｐウェル４上
部のチャネルストッパー層５とＰウェル電位固定層６と
の間に、ＮＭＯＳのドレイン耐圧の向上及びホットエレ
クトロン対策のために、Ｎ型不純物、例えば３１ ｐ
＋をイオン注入法により１０′２〜１０Ｉ４ｃ＋ｎ−”
注入し、低濃度ドレイン層８及び低濃度ソース層９を形
成すると同時に、上記ｓＩ基板１上部のドレイン層３と
Ｐウェル４との間にＰＭＯＳの低濃度のチャネルストッ
パー層１ｏを形成する。Next, as shown in FIG. 1(b), a predetermined portion of the field oxide film 7 is opened using photolithography, and a hole is formed between the channel stopper layer 5 above the P-well 4 and the P-well potential fixing layer 6. In order to improve the drain breakdown voltage of NMOS and countermeasures against hot electrons, N-type impurities such as 31 p
+ by ion implantation method to 10'2 to 10I4c+n-"
At the same time, a low concentration channel stopper layer 1o of PMOS is formed between the drain layer 3 and the P well 4 on the sI substrate 1.
その後、第１図（Ｃ）に示す如く、熱処理を行ない、フ
ィールド酸化膜７を更に成長させ、これを上記同様ホト
リソ技術を以て開孔し、Ｎ型不純物、例えば：ｚｐ＋
を１０！５〜１０ ” ｃｍ −”の濃度でイオン注入
又は熱拡散することにより、低濃度ドレイン層８に囲ま
れた高濃度ドレイン層１１と、部分が低濃度ソース層９
に重合する高濃度ソース層１２と、Ｓｉ基板１上部のソ
ース層２を囲み、上記チャネルストッパー層１０とパタ
ーン的に接続されるＮ型不純物層の高濃度の基板電位固
定層１３とを同時に形成する。Thereafter, as shown in FIG. 1(C), a heat treatment is performed to further grow the field oxide film 7, and a hole is opened in this using the same photolithography technique as described above, and an N-type impurity, for example: zp+
By ion implantation or thermal diffusion at a concentration of 10!5 to 10 cm - , the highly doped drain layer 11 surrounded by the lightly doped drain layer 8 and the lightly doped source layer 9 are formed.
A high-concentration source layer 12 that polymerizes to a high concentration, and a high-concentration substrate potential fixing layer 13 of an N-type impurity layer that surrounds the source layer 2 on the top of the Si substrate 1 and is pattern-wise connected to the channel stopper layer 10 are simultaneously formed. do.
更に、第１図（ｄ）に示す如く、熱処理を行ない、上記
フィールド酸化膜７を再度成長させた後、ホトリソ技術
を以て基板電位固定層１３及びソース層２上にコンタク
トホール１４ａ１ ドレイン層３及び高濃度ドレイン領
域１１上にコンタクトホール１４ｂ及び高濃度ソース領
域１２及びＰウェル電位固定層６上にコンタクトホール
１４ｃを夫々形成すると共に、ソース層２及びドレイン
層３間並びにドレイン層８．１１及びソース層９．１２
間を跨ぐようにＰＭＯＳのゲート酸化膜１５とＮＭＯＳ
のゲート酸化膜１６とを夫々形成する。Furthermore, as shown in FIG. 1(d), after performing heat treatment and growing the field oxide film 7 again, contact holes 14a1, drain layer 3 and high A contact hole 14b is formed on the doped drain region 11, and a contact hole 14c is formed on the heavily doped source region 12 and the P-well potential fixing layer 6, respectively. 9.12
The PMOS gate oxide film 15 and the NMOS
A gate oxide film 16 is formed respectively.
しかる後、第１図（ｅ）に示す如＜、Ｓｉ基板１上に、
メタル蒸着を行なった後、上記コンタクトホール１４ａ
上に、ＰＭＯＳのソース電極１７、コンタクトホール１
４ｂ上に、出力電極１８及びコンタクトホール１４ｃ上
に、ＮＭＯＳのソース電極１９、更にゲート酸化膜１５
．１６上に、ＰＭＯＳのゲート電極２０並びにＮＭＯＳ
のゲート電極２１が夫々形成されるようにメタルの配線
ホトリソを行なう。斯くして、出力電極１８は、ＰＭＯ
Ｓのドレイン層３及びＮＭＯＳＯ高濃度ドレイン層１１
に接続されるため、出力信号が得られ、第２図に示すよ
うに、ソース電極１９は、Ｐウェル電位固定層６及びチ
ャネルストッパー層５に夫々接続される。更に、ソース
電極１７は、基板電位固定層１３及びチャネルストッパ
ー層１０に接続され、このチャネルストッパー層１０は
、ドレイン層３及びゲート酸化膜１５を囲み且つソース
側において、高濃度の基板電位固定層１３に重ね合され
る。After that, as shown in FIG. 1(e), on the Si substrate 1,
After performing metal vapor deposition, the contact hole 14a is
On top, PMOS source electrode 17 and contact hole 1
4b, an NMOS source electrode 19 and a gate oxide film 15 are formed on the output electrode 18 and the contact hole 14c.
．． 16, a PMOS gate electrode 20 and an NMOS
Metal wiring photolithography is performed so that gate electrodes 21 are formed respectively. Thus, the output electrode 18 is a PMO
S drain layer 3 and NMOSO high concentration drain layer 11
As shown in FIG. 2, the source electrode 19 is connected to the P-well potential fixing layer 6 and the channel stopper layer 5, respectively. Furthermore, the source electrode 17 is connected to a substrate potential fixing layer 13 and a channel stopper layer 10, and this channel stopper layer 10 surrounds the drain layer 3 and gate oxide film 15 and is formed of a highly concentrated substrate potential fixing layer on the source side. It is superimposed on 13.
以上説明したように本発明によれば、第１ ＭＯＳのド
レイン層を囲むチャネルストッパー層を低濃度層とした
ので、拡散層の広がりが抑制され、上記ドレイン層のマ
スク合せマージンが小さくできると共に、高濃度接合が
防止でき、結晶欠陥によるリーク電流が低減できる他、
高密度化ができる。As explained above, according to the present invention, since the channel stopper layer surrounding the drain layer of the first MOS is a low concentration layer, the spread of the diffusion layer is suppressed, and the mask alignment margin of the drain layer can be reduced. In addition to preventing high concentration junctions and reducing leakage current due to crystal defects,
High density is possible.
更に、上記低濃度チャネルストッパー層と第２ＭＯ３の
低濃度ドレイン層及びソース層とは、同一工程内で形成
されるので、工数の増加が防止できる。又、第１ＭＯ３
のソース層周辺を、高濃度の基板電位固定層が囲繞する
ため、メタル電極とのオーミック性が良好で、而も基板
電位の変動が防止できる等により上述の課題を解消し得
る。Furthermore, since the low concentration channel stopper layer and the second MO3 low concentration drain layer and source layer are formed in the same process, an increase in the number of steps can be prevented. Also, the 1st MO3
Since the source layer is surrounded by a highly concentrated substrate potential fixing layer, the ohmic relationship with the metal electrode is good, and fluctuations in the substrate potential can be prevented, so that the above-mentioned problems can be solved.
第１図及び第２図は本発明方法に係る実施例を示すもの
で、第１図は工程断面図、第２図は平面図、第３図及び
第４図は従来例を示すもので、第３図はＣ’Ｍ ＯＳの
平面図、第４図は同断面図である。
１・・・Ｓｔ基板、２・・・ソース層、３・・・ドレイ
ン層、４・・・Ｐウェル、５・・・チャネルストッパー
層、６・・・Ｐウェル電位固定層、７・・・フィールド
酸化膜、８・・・低濃度ドレイン層、９・・・低濃度ソ
ース層、１０・・・チャネルストッパー層、１１・・・
高濃度ドレイン層、１２・・・高濃度ソース層、１３・
・・基板電位固定層、１４ａ、’ １４ｂ、 １４ｃ
ｍｖンタクトホール、１５．１６・・・ゲート酸化膜、
１７・・・ソース電極、１８・・・出力電極、１９・・
・ソース電極、２０．２１・・・ゲート電極。1 and 2 show an embodiment of the method of the present invention, FIG. 1 is a cross-sectional view of the process, FIG. 2 is a plan view, and FIGS. 3 and 4 show a conventional example. FIG. 3 is a plan view of the C'MOS, and FIG. 4 is a sectional view thereof. DESCRIPTION OF SYMBOLS 1... St substrate, 2... Source layer, 3... Drain layer, 4... P well, 5... Channel stopper layer, 6... P well potential fixing layer, 7... Field oxide film, 8...Low concentration drain layer, 9...Low concentration source layer, 10... Channel stopper layer, 11...
High concentration drain layer, 12... High concentration source layer, 13.
...Substrate potential fixing layer, 14a,' 14b, 14c
mv tact hole, 15.16...gate oxide film,
17... Source electrode, 18... Output electrode, 19...
- Source electrode, 20.21... gate electrode.
Claims (1)
の製造方法において、 基板所定部にドレイン層及びソース層を形成すると共に
、上記基板表面に絶縁膜を成長形成する工程と、 該絶縁膜の所定部を開孔した後、不純物を打ち込み、低
濃度ドレイン層及び低濃度ソース層並びに上記ドレイン
層を囲む低濃度のチャネルストッパー層を形成する工程
と、 更に、上記絶縁膜を成長させ、その所定部を開孔した後
、再度不純物を打ち込み、上記低濃度ドレイン層に囲ま
れた高濃度ドレイン層及び上記低濃度ソース層に部分が
重合する高濃度ソース層を形成すると共に、上記チャネ
ルストッパー層とパターン的に接続し、上記ソース層を
囲む高濃度の基板電位固定層を形成する工程とを含むこ
とを特徴とする半導体素子の製造方法。[Claims] A method for manufacturing a semiconductor device having an NMOS and a PMOS having an LDD structure, comprising: forming a drain layer and a source layer on a predetermined portion of a substrate, and growing an insulating film on the surface of the substrate; After opening a predetermined portion of the film, implanting impurities to form a low concentration drain layer, a low concentration source layer, and a low concentration channel stopper layer surrounding the drain layer, further growing the insulating film, After opening a hole in a predetermined portion, impurities are implanted again to form a highly doped drain layer surrounded by the lightly doped drain layer and a highly doped source layer partially overlapping with the lightly doped source layer, and to form the channel stopper. A method of manufacturing a semiconductor device, comprising the step of forming a highly concentrated substrate potential fixing layer that surrounds the source layer and is connected to the source layer in a pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63172671A JP2554361B2 (en) | 1988-07-13 | 1988-07-13 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63172671A JP2554361B2 (en) | 1988-07-13 | 1988-07-13 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0223652A true JPH0223652A (en) | 1990-01-25 |
| JP2554361B2 JP2554361B2 (en) | 1996-11-13 |
Family
ID=15946211
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63172671A Expired - Lifetime JP2554361B2 (en) | 1988-07-13 | 1988-07-13 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2554361B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613562A (en) * | 1992-03-31 | 1994-01-21 | Hyundai Electron Ind Co Ltd | Method for manufacturing CMOS transistor with increased junction breakdown voltage |
| JP2006253376A (en) * | 2005-03-10 | 2006-09-21 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53122377A (en) * | 1977-03-31 | 1978-10-25 | Fujitsu Ltd | Semiconductor device |
| JPS5666071A (en) * | 1979-11-01 | 1981-06-04 | Fujitsu Ltd | Manufacture of complementary type mis semiconductor device |
| JPS60143659A (en) * | 1984-12-10 | 1985-07-29 | Hitachi Ltd | Complementary Insulated Gate Field Effect Transistor Integrated Circuit |
-
1988
- 1988-07-13 JP JP63172671A patent/JP2554361B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS53122377A (en) * | 1977-03-31 | 1978-10-25 | Fujitsu Ltd | Semiconductor device |
| JPS5666071A (en) * | 1979-11-01 | 1981-06-04 | Fujitsu Ltd | Manufacture of complementary type mis semiconductor device |
| JPS60143659A (en) * | 1984-12-10 | 1985-07-29 | Hitachi Ltd | Complementary Insulated Gate Field Effect Transistor Integrated Circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613562A (en) * | 1992-03-31 | 1994-01-21 | Hyundai Electron Ind Co Ltd | Method for manufacturing CMOS transistor with increased junction breakdown voltage |
| JP2006253376A (en) * | 2005-03-10 | 2006-09-21 | Oki Electric Ind Co Ltd | Semiconductor device and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2554361B2 (en) | 1996-11-13 |
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