JPH0223654A - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH0223654A JPH0223654A JP63174119A JP17411988A JPH0223654A JP H0223654 A JPH0223654 A JP H0223654A JP 63174119 A JP63174119 A JP 63174119A JP 17411988 A JP17411988 A JP 17411988A JP H0223654 A JPH0223654 A JP H0223654A
- Authority
- JP
- Japan
- Prior art keywords
- amorphous silicon
- present
- semiconductor equipment
- resistance
- silicon
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 10
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 239000002184 metal Substances 0.000 claims description 2
- 239000000758 substrate Substances 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000006386 memory function Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Landscapes
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、半導体装置に関し、特に電気的にプログラム
可能な半導体素子の構造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to the structure of an electrically programmable semiconductor element.
［従来の技術］
従来の構造を第２図に示す。２０１の半導体基板上に２
０３の基板とは異種導電型の拡散層を設け、その両端に
電極２０４．２０５を構成する。[Prior Art] A conventional structure is shown in FIG. 2 on the 201 semiconductor substrate
A diffusion layer of a conductivity type different from that of the substrate No. 03 is provided, and electrodes 204 and 205 are formed at both ends of the diffusion layer.
この時、一方の電極２０５と拡散層２０３の間にアモル
ファスシリコン２０６をはさむ。本素子の動作を説明す
る。通常アモルファスシリコンの抵抗値は、数ＭΩ〜数
ＧΩと非常に高い状態にある。これに、それの両端子２
０４．２０５の間に一定以上の電圧を印加すると、２０
６のアモルファスシリコンが構造変化を起し、数百Ω近
傍程度まで抵抗が低下する。本素子はかかる抵抗の変化
を記憶機能として用いるものである。At this time, amorphous silicon 206 is sandwiched between one electrode 205 and the diffusion layer 203. The operation of this device will be explained. Normally, the resistance value of amorphous silicon is very high, ranging from several MΩ to several GΩ. To this, both terminals 2 of it
If a voltage above a certain level is applied between 04.205 and 20
The amorphous silicon of No. 6 undergoes a structural change, and its resistance decreases to around several hundred ohms. This element uses such changes in resistance as a memory function.
［発明が解決しようとする課題］
プログラム特性つまり、書込み電圧、電流と、低下した
抵抗値の関係が本素子の有益性を決定する。回路設計上
は、書込み電圧、電流とも低く、かつ書き込み後の抵抗
値が極力低い方が望ましい。[Problems to be Solved by the Invention] The programming characteristics, that is, the relationship between the write voltage, current, and reduced resistance value determine the usefulness of the device. In terms of circuit design, it is desirable that both the write voltage and current be low, and that the resistance value after writing be as low as possible.
書き込み電圧は、２０６のアモルファスシリコン層の厚
みを薄く制御することによって低くできる。これに対し
て、書込み電流を低くすることは、書き込み後の抵抗を
高くするため、この特性改善が本素子の性能向上のポイ
ントであった。The write voltage can be lowered by controlling the thickness of the amorphous silicon layer 206 to be thin. On the other hand, lowering the write current increases the resistance after writing, so improving this characteristic was the key to improving the performance of this device.
［課題を解決するための手段］
本発明では従来例に於ける拡散層２０３のかわりに多結
晶シリコン膜を下部電極に用いるものである。[Means for Solving the Problems] In the present invention, a polycrystalline silicon film is used for the lower electrode instead of the diffusion layer 203 in the conventional example.
［実 施 例］
本発明の実施例を第１図に示す。１０１の半導体基板上
に１０２の絶縁膜を設け、その上に本発明の素子を形成
する。[Example] An example of the present invention is shown in FIG. An insulating film 102 is provided on a semiconductor substrate 101, and an element of the present invention is formed thereon.
１０４は多結晶シリコンを示し、１０７の金属配線との
間に、１０５のアモルファスシリコンをはさんだ構造で
ある。本発明は、説明するまでもない、通常よく知られ
た製造方法で容易に実現できる。104 indicates polycrystalline silicon, and the structure is such that amorphous silicon 105 is sandwiched between it and metal wiring 107. The present invention does not need to be explained and can be easily realized by a generally well-known manufacturing method.
［発明の効果］
電圧、電流を印加することによってアモルファスシリコ
ンの抵抗値が低下する原理については、確定した理論的
説明はまだないものの、−前約には、ジュール熱によっ
てアモルファスシリコンが融解し、冷却過程で結晶化す
ることにより低抵抗化するといわれている。本発明はこ
の原理に基づくもので、ジュール熱の熱放散を妨ぎ、効
率の高い書き込み特性を得るものである。−前約にシリ
コンの熱伝導率は、シリコン酸化膜等の絶縁膜に較べて
高い。このため第２図の従来例では、発生したジュール
熱が半導体基板に散逸し、また熱容量が基板全体である
ため非常に大きい。このため書込み効率が低い。これに
対して本発明は、下部電極が多結晶シリコンであり、周
囲がほぼ絶縁膜で囲まれており、また形状がパターン化
されて限定されているため熱容量も小さくできる。これ
によって低い入力エネルギーで充分昇温することができ
るために効率のよい書込みができ、低電流で低抵抗化が
可能となった。[Effects of the invention] Although there is still no established theoretical explanation for the principle by which the resistance value of amorphous silicon decreases by applying voltage or current, it is known that amorphous silicon melts due to Joule heat, It is said that resistance decreases by crystallizing during the cooling process. The present invention is based on this principle, and aims to prevent the dissipation of Joule heat and obtain highly efficient writing characteristics. -The thermal conductivity of silicon is higher than that of insulating films such as silicon oxide films. Therefore, in the conventional example shown in FIG. 2, the generated Joule heat is dissipated into the semiconductor substrate, and the heat capacity is very large because it is the entire substrate. Therefore, writing efficiency is low. In contrast, in the present invention, the lower electrode is made of polycrystalline silicon, is almost surrounded by an insulating film, and has a patterned and limited shape, so that the heat capacity can be reduced. This makes it possible to sufficiently raise the temperature with low input energy, allowing efficient writing, and making it possible to reduce resistance with low current.
第１図は、本発明を示す半導体装置の構造断面図。 第２図は、従来例を示す半導体装置の構造断面図。 FIG. 1 is a structural sectional view of a semiconductor device showing the present invention. FIG. 2 is a structural sectional view of a semiconductor device showing a conventional example.
Claims (1)
電極の一方は、金属であり、他方は多結晶シリコンであ
り、概２層電極間にはアモルファスシリコンがはさまれ
ていることを特徴とする半導体装置。In a semiconductor device consisting of two layers of electrodes, one of the two layers of electrodes is metal, the other is polycrystalline silicon, and amorphous silicon is sandwiched between the two layers of electrodes. A semiconductor device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174119A JPH0223654A (en) | 1988-07-12 | 1988-07-12 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63174119A JPH0223654A (en) | 1988-07-12 | 1988-07-12 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0223654A true JPH0223654A (en) | 1990-01-25 |
Family
ID=15972973
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63174119A Pending JPH0223654A (en) | 1988-07-12 | 1988-07-12 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0223654A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328865A (en) * | 1991-09-04 | 1994-07-12 | Vlsi Technology, Inc. | Method for making cusp-free anti-fuse structures |
| KR20230086961A (en) * | 2021-12-09 | 2023-06-16 | 엘지디스플레이 주식회사 | Display device |
-
1988
- 1988-07-12 JP JP63174119A patent/JPH0223654A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5328865A (en) * | 1991-09-04 | 1994-07-12 | Vlsi Technology, Inc. | Method for making cusp-free anti-fuse structures |
| KR20230086961A (en) * | 2021-12-09 | 2023-06-16 | 엘지디스플레이 주식회사 | Display device |
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