JPH02236658A - information processing equipment - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention]

[Industrial Application Field 1] The present invention relates to an electronic information processing device such as a neural network, and particularly to an information processing device in which the amount of hardware thereof is significantly reduced. [Prior art 1] Neural networks have multiple information processing units called neurons, and each neuron mutually receives signals output from several other neurons. Each neuron is equipped with multiple circuits called synapses, and these circuits multiply signals received from other neurons by coefficients (hereinafter referred to as weight values) determined for each neuron. The output of each neuron is then determined according to the sum of these products. An example of such a neural network is introduced in an article from page 115 of the August 10, 1987 issue (No. 4 2 7) of Nikkei Electronics magazine. Also, Nikkei Microdevice Magazine 19
The article starting on page 72 of the July 1988 issue also introduces an example of a neural network constructed entirely of digital circuits. Although digital circuits require more hardware than analog circuits, they are resistant to element variations and noise, and are easy to improve accuracy.
Suitable for high integration. [Problem to be solved by the invention 1] By the way, in order to perform more complex information processing using a neural network, it is necessary to increase the number of neurons. However, in a neural network with a conventional structure, the amount of wiring interconnecting each 221ron and the number of synapses increases in proportion to the square of the number of neurons, making it difficult to scale up. If the number of neurons is increased beyond a certain level, this becomes dramatically difficult to achieve. In particular, in the case of digital circuits that are suitable for integration in terms of calculation accuracy and noise resistance, the multipliers that make up the synapse require a large number of elements, making this problem even more serious. A first object of the present invention is to provide an information processing device such as a neural network in which the amount of hardware does not increase dramatically even if the number of neurons, which are information processing units, is increased. . A second object of the present invention is to realize a large-scale neural network constructed of digital circuits. A third object of the present invention is to provide an information processing device that can configure a large-scale neural network without reducing yield even when the number of neurons is increased. A fourth object of the present invention is to provide an information processing device that can suppress a decrease in operating speed due to an increase in the number of neurons and can construct a large-scale neural network at high speed. A fifth object of the present invention is to provide an information processing system that can realize a large-scale neural network using fewer types of photomasks. [Means for Solving the Problems] The first or second object of the present invention can be achieved by time-divisionally transmitting signals between neurons using common hardware. The first or second object of the present invention can also be achieved by storing weight values in a semiconductor memory device, and storing only a predetermined number of weight values in descending order of absolute value. The second object of the present invention can be achieved by layering buses that interconnect neurons. The third object of the present invention can be achieved by widening the width and spacing of the wires that make up the upper layer bus. The fourth object of the present invention can be achieved by pipelining signal transmission on the bus. The fourth object of the present invention can also be achieved by storing the weight values in the order in which they are accessed. The fifth object of the present invention can be achieved by providing a portion of the bus that connects to its neighbor while shifting its position.

[Effect]

By transmitting signals between neurons in a time-sharing manner using common hardware, the number of synapses required per neuron is only one, so even if the number of neurons is increased, it is not possible to dramatically increase the number of synapses. The amount of hardware will no longer increase. Therefore, it becomes possible to realize a large-scale neural network. By storing the weight values in the semiconductor storage device, it becomes easy to replace the weight values. The amount of hardware can be saved by storing only a predetermined number of data, starting from the one with the largest absolute value. In addition, by layering the bus with WI, it is possible to prevent the load on a single bus from becoming heavy even when the number of neurons is increased, making it possible to realize a large-scale neural network. When a neural network is configured on a WSI (wafer scale integrated circuit), if the bus is layered, if a failure such as a disconnection or short circuit occurs in a bus in a higher layer, it will affect a large area and reduce the yield. By widening the wiring width and spacing of only the buses in the upper hierarchy, it is possible to reduce the failure rate in that part. By pipelining the signal transmission on the bus, 1
This makes it possible to send signals from several neurons to other neurons within the time it takes for signals to be sent from one neuron to another, thereby increasing operating speed. By storing the weight values in the order in which they are accessed, it is possible to read out the next weight value to be accessed in advance, thereby increasing the operating speed. By providing a bus that connects adjacent devices while shifting their positions, it is possible to provide different signals to each integrated circuit even if the integrated circuits have the same shape. Therefore, by arranging neuron circuits created using the same mask, WSI (
This makes it possible to construct wafer-scale integrated circuits.

【Example】

An embodiment of the present invention will be explained below using FIG. In FIG. 1, 100 is a neuron, and in order to simplify the explanation, this figure shows a case where four neurons are connected. Each neuron includes a memory 101 for storing weight values, a multiplier 102 for multiplying the input signal and the weight value, an adder 103 and a latch circuit 104 for calculating the sum of the products, and a latch circuit 104 for calculating the sum of the products. a latch circuit 105 for storing the contents of the latch circuit 105, and a tri-state output buffer circuit 106 for outputting the contents of the latch circuit 105.
, a decoder 107 is provided for determining whether the neuron is selected or not. 100 neurons each
is connected to the control device 200 via a bus. 301
, 302, 303, and 304 respectively transmit input signals, address signals, clock signals, and cycle signals to the control device 2.
This is a bus for sending data from 00 to each neuron 100.
305 outputs output signals from each neuron 100 to the control device 2;
This is the bus for sending to 00. In this embodiment, the latch circuit 104 is one in which data is taken in by the edge of the clock signal from the bus 303. Also,
Each neuron 100 is assigned a unique address, and the decoder 107 is set to output a signal when the address matches the address signal from the control device 200. Next, the operation of this device will be explained. The control device 200 is
As shown in FIG. 2, the address signal is a signal that sequentially repeats the address of each neuron, the clock signal is a signal that causes the latch circuit 104 to take in data each time each address is specified, and the cycle signal is a signal that causes the latch circuit 104 to take in data each time an address is specified. Each time the circuit goes around, a signal is sent to the latch circuit 105 to cause the data to be taken in. The address signal sent from the control device 200 to each neuron 100 via the bus 302 is applied to the decoder circuit 107, and only the buffer circuit 106 in the neuron specified by the address signal outputs the signal to the output bus 305. ．． Buffer circuits 106 in other neurons enter a high resistance state. Therefore, the contents of the latch circuit 105 in the neuron 100 specified by the address signal are sent to the control device 200. In the control device 200, the signal is sent as it is or after being subjected to function conversion using a sigmoid function or the like, and sent to each neuron 100 via the input bus 301. In each neuron 100, the weight value between the other party designated by the address signal at that time is read from the memory 101, and the multiplier 100 multiplies the weight value and the input signal sent from the control circuit 200 via the bus 301. The adder 103 calculates the sum of the product and the numerical value accumulated in the latch circuit 104 so far, and the sum is added to the latch circuit 104. When a clock signal is applied from the bus 303, the sum is taken into the latch circuit 104. Therefore, during one address cycle, the sum of the products of the signals and weight values from all neurons is the latch time Il
It is found within t104. Then, when a cycle signal is applied from the bus 304, the sum is taken into the latch circuit 105 and becomes the new output value of each neuron 100.
In this way, the circuit in Figure 1 operates as a neural network. By the way, if the neuron 100 is configured as shown in Figure 1,
If you try to construct a large-scale neural network by increasing the number of neurons, as the number of neurons increases beyond a certain point, the capacity added to the bus will increase and the operation speed will slow down. FIG. 3 shows a part of an embodiment of the present invention in which the bus is structured in a hierarchical structure to avoid this problem.
A group of neurons 150 are shown. By connecting a large number of these as described later (Figure 4), a large-scale neural network can be realized. In Figure 3, 1
0o is a neuron, 301 to 305 are buses of the first floor (m<lowest layer), and this part corresponds to the neuron 100 in Figure 1.
and are configured in the same way as buses 301-305. However, in order to configure a large-scale neural network, the number of bits of the address bus 302 and the capacity of the memory 101 that stores the weight values need to be larger than in the case of FIG. 1. 311, 312, 313, 314,
315 is a second layer bus for transmitting input signals, address signals, clock signals, cycle signals, and output signals, respectively. 311 to 314 of the second layer buses
are connected to the first layer buses 301 to 301 through the buffer circuit 158.
The output bus 315 of the second layer receives the signal from the output bus 305 of the first layer via the tri-state buffer 156. 157 is for determining whether or not there is a neuron 100 designated by the address signal in this neuron group 150. When it is determined that there is a neuron 100 specified by the address signal, the data on the output bus 305 of the first level calendar is transferred to the second level. It is sent to the output bus 315 of the hierarchy, and when it is determined that there is no output bus, the tri-state bus sofa 156
Puts the output of into a high resistance state. By preparing a large number of neuron groups 150 and connecting the buses 311 to 315 of the second layer, it is possible to connect a large number of neurons 100 without significantly increasing the capacity added to each bus. Figure 4 shows an example of the connection method. FIG. 4 shows an embodiment configured as a WSI (wafer scale integrated circuit) on one semiconductor substrate 500. Each neuron group 150 is shown in FIG. 3, and 60 neuron groups are depicted in this figure. 31
Reference numerals 1 to 315 indicate second-level buses arranged in the horizontal direction, and a plurality of sets are provided over the entire surface of the board. 321 to 325 are the third-level calendar buses installed in the vertical direction, and only one set is installed in the center of the board. In this embodiment, two to four neuron groups 150 are connected by second-level buses 311 to 315, and second-level buses 311 to 315 are connected to buffer unit 3.
50 to third layer buses 321 to 325. The structure of the buffer unit 350 consists of first layer buses 301 to 305 and second layer buses 311 to 315 in FIG.
The structure is similar to that of the connection section of , and consists of an input buffer, decoder, and output buffer. Then, the third layer bus 32
A control device i1200 is provided at one end of each of 1 to 325. In this way, it is possible to realize a neural network that connects all the neurons provided on the entire surface of the board while keeping the maximum length of the bus to at most the diameter of the board.
Regarding the power supply, the second layer buses 311 to 315
A large number of power supply points can be secured by running a power supply bus parallel to the power supply and supplying power from the power supply pads 450 provided at both ends. In addition, buses for power supply, buses 311 to 315 in the second hierarchy, and buses 32 in the third hierarchy are also used.
Regarding the wiring used for 1 to 325 etc., neuron group 150
It is desirable to use wires that have a wider line width and wider spacing than the wires inside the buffer section 350. This is because these buses have long wire lengths, and special care must be taken to ensure that wiring resistance does not increase, and this may occur if there is a failure such as a disconnection or short circuit in a bus higher up in the hierarchy. This is because these buses especially need to have low failure rates, as many neurons become unusable. For failures that affect only a small number of neurons, it is possible to avoid using the failed part by setting the weight value for the failed neuron to O on the normal neuron side. Also, the control device 200 is connected to this wafer 5.
It is also possible to provide a buffer circuit at this position, without providing it above 00, and connect it to an externally provided control device. If the control device 200 breaks down, the entire system becomes unusable, but if only this part is provided externally, it can be replaced in the event of a breakdown. It is also conceivable to reduce the failure rate by multiplexing the control device 200 or the buffer circuit for connection with the outside, or to provide it in the center of the wafer where the yield is high. Furthermore, a plurality of substrates 500
It is also possible to prepare a neural network and connect it to the fourth layer bus via this buffer circuit to construct an even larger neural network. By the way, if you increase the number of bus layers, the terminal neuron 1
The delay time until the signal output from 00 reaches the terminal neuron lOO again via the control device 200 increases. However, by inserting a latch circuit in the buffer that connects the upper layer bus and the lower layer bus to synchronize signal transmission, pipeline processing is possible and the actual processing time does not increase. ．． An example of the timing is
This will be explained in detail using Figure 5. This figure shows a case where the number of neurons is 100. As for the clock signal, use a high-speed circuit as much as possible and connect it to bus 3 on the third layer.
23 to the second layer bus 313, and then the first layer bus 3
Supplied so that the propagation time to 03 is shortened. All other signals are transmitted in synchronization with the clock signal of each layer. The address signal is the address 1 to 1 of each neuron.
00 and addresses 101 to 105 necessary for time division control are repeatedly supplied, and an interval of one clock is provided between returning from the maximum value 105 to the minimum value 1. In order to transmit this in synchronization with the clock signal, it is shifted by one clock when propagating to the second and first layers. Since each neuron is connected to the first layer address bus 302, the output value of the neuron specified by the address signal on this bus is output to the first layer M output bus 305. This output signal is then sent to the output bus 315 of the second hierarchy and the output bus 325 of the third hierarchy while being shifted by one clock in synchronization with the clock signal. This is applied to the input bus 321 of the third IlIJ layer via the control circuit 200, but if it is synchronized with the clock signal in the control circuit 200, it will be shifted by one clock as shown in the figure. Then, this signal is again shifted by one clock and sent to the second layer input bus 311 and the first layer input bus 301. Therefore, five clocks after the address signal arrives on the address bus 302 of the first layer, the signal from the neuron specified by the address reaches each neuron. Therefore, each neuron calculates the cumulative addition by regarding the signal as being from the neuron whose address is 5 smaller than the value indicated by the address signal at that time. By doing this, the period of the clock signal can be made shorter than when signal transmission between buses is not synchronized. Furthermore, when attempting to form an integrated circuit over the entire surface of a semiconductor substrate with a diameter of several inches, as shown in Figure 4, the entire surface is exposed at once during the process of exposing the photoresist coated on the substrate to form a pattern. If this is attempted, the resolution will deteriorate, so, for example, the neuron group 150 will be exposed in several times as one exposure unit. In that case, if the patterns of each neuron group 150 are even slightly different, it is necessary to prepare a mask for each pattern, which is uneconomical because the number of types of masks becomes enormous. On the other hand, each neuron has an individually determined address, and a function to identify this address is required. In other words, it is necessary to be able to identify individual addresses without changing the contents of each neuron group 150 at all. An example of realizing this is shown in Figure 6. Figure 6 shows the right half of one row of neuron groups in Figure 4. In Figure 6, 150 is a neuron group. Among these, 100 are neurons, 3
11 to 315 are buses of the second layer, 156 is a tri-state buffer, and 158 is a buffer, and their connection relationship is the same as in FIG. 3. 350 is a part that connects the buses 321 to 325 on the third hierarchy and the buses 311 to 315 on the second hierarchy, 166 is a tristate buffer, and 166 is a tristate buffer;
68 is a buffer. The decoder 157 mounted in each neuron group 150 in FIG. 3 is mounted in the bus connecting section 350 between the third layer and the second layer in FIG. 6. The output of this decoder 157 is a 4-bit bus 31
G to each neuron group 150, and this bus is formed so as to shift one bit each time it passes through one neuron group 150, as shown in the figure. This decoder 157 then selects the neuron 100 pointed to by the address signal.
Only the output corresponding to the neuron group 150 including the neuron group 150 is set to high level. Then, although each neuron group 150 has exactly the same shape, the target neuron group 1
You can select only one. Also, each neuron 1
00 can determine whether or not it has been selected based on the lower two bits of the address signal and the signal sent from the decoder 157. Furthermore, with respect to the connection section 350, only one desired row can be selected using a similar method. In this case, the upper bit of the address signal
- is decoded and sent from the control device 200 to each connection unit 350 via a 9-bit bus 326. Since the 9-bit bus 326 is configured to shift one bit for each row, it is possible to select only one desired row, even though each connection portion 350 has exactly the same shape. can. Based on the above, the types of photomasks required to create the neural network shown in Figure 4 are:
For neuron group 150 on the right side, neuron group 15 on the left side
The number of sets can be kept to five: one for 0, one for the connection part 350, one for the connection circuit with the control device 200 or the outside, and one for the power supply pad 450. Note that if this method is used with a substantially circular semiconductor substrate, there will be empty numbers in the address, but if the empty numbers are skipped when sending an address signal from the control device 200, the processing time will not increase. Needless to say, 6 Also, the decoder 1 in each neuron 100
07 as well, if it is provided in each neuron group 150 instead of being provided in each neuron 100, each neuron 1
00 can all be made into the same circuit, making the design easier. By the way, as the number of connected neurons increases, the first
The number of weight values to be stored in the memory 101 in each neuron 100 shown in the figure also increases, and a memory with a large capacity is required. FIG. 7 shows an embodiment for saving the capacity of this memory 101. This circuit attempts to save storage capacity by storing only a predetermined number of weight values in pairs with the other party's address in descending order of absolute value, and treating other weight values as 0. be. In FIG. 7, 111 and 112 are memory cell arrays, 113 is a pointer, 114 is a comparator, and 115 is a selector. In the memory cell array, 111 is a part for storing the address of the other party, and 112 is a part for storing the weight value, and the address of the other party and the weight value are stored in pairs in each row of the memory cell array. At this time, the order in which the addresses are stored in each line is arranged in ascending order. Furthermore, as described above, the address signals sent from the control device 200 to each neuron via the bus 302 are also sent in ascending order. The pointer 113 is initially set to point to the first row of the memory cell arrays 111 and 112. Then, the contents stored in the first row are read out, and the address information is added to one end 122 of the comparator 114 and the weight value information is added to one end 124 of the selector 115, respectively. The address information added to the comparator 114 at this time is the smallest number of address information stored in the memory cell array 111. On the other hand, the address signal sent from the control device 200 via the address bus 302 is applied to the other end of the comparator 114. Since the address signals are sent in ascending order, the comparator 1
Until the signal 122 applied to the memory cell array 111 matches for the first time, the address signal is a smaller number and therefore does not exist in the memory cell array 111. At this time, the output 123 of the comparator 114 is at the -1 level, and the numerical value It O ## added to the other terminal 125 is output to the output terminal 126 of the selector 115. The output of this selector 115 is the weight value for the party pointed to by the address signal 302 at that time. In this case, the other party is not stored in the memory cell array 111, that is, the absolute value of the weight value is small, and the weight value is regarded as 0. Furthermore, while the output 123 of the comparator 114 is at a low level, the output 127 of the AND circuit 116 is always at a low level, and the pointer 113 continues to point to the same row. However, when the address information applied to the terminal 122 and the address signal sent via the address bus 302 match, the output 123 of the comparator 114 becomes high level, and the weight value information applied to the terminal 124 is output. appears at the output terminal 126 of the selector 115. This is the weight value for the party pointed to by the address signal at that time. Then, the pointer 113 points to the next row in synchronization with the clock signal sent via the bus 303. Then, the address information stored in that row and the address bus 3
02 until the address signal sent matches.
The selector 115 continues to output It O I+ and repeats the same operation thereafter. Then, when a cycle signal is sent via the bus 304, the pointer 113 returns to the first position.
Return to line. As described above, the circuit shown in FIG. 7 operates so as to accurately read weight values with large absolute values stored in the memory cell array 112, and to regard other weight values as O. In addition, as mentioned above, this memory is always read in ascending order, so when an address signal is sent, it can be instantly determined whether the information exists or not, so it can be read without increasing the access time. be able to. FIG. 8 shows an example of the configuration of the neuron 100 shown in FIG. 1 in more detail. In FIG. 8, a memory 101 for storing weight values, a multiplier 102, an adder 103, a latch circuit 104, a latch circuit 1o5, a tristate bath sofa 106, and a decoder 1
07 and the operations of buses 301 to 305 on the first floor calendar are as follows:
This is as explained in the figure. Shifter 807 and selector 803 are circuits for stabilizing operation. Also, a decoder 8o1, a selector 802, a tristate bath sofa 804, a latch circuit 805, a selector 806
, 808, and buses 831 to 838 are for self-learning by the neural network of the present invention. The shifter circuit 807 changes the output value of the latch circuit 104 to 17
It is configured to shift by 2 times, 1/4 times, 178 times, etc. The selector 803 normally transmits the output of the multiplier 102 to the adder 103, but is configured to transmit the output of the shifter circuit 807 when a cycle signal (bus 304) is input. Further, when the selector 803 transmits the output of the shifter circuit 807, the adder 103 is configured to perform a subtraction operation. The selector 808 is
The output of the latch circuit 104 is used as the adder 10 except during self-learning.
Add to 3. Then, normally the adder rI103 and the latch circuit 104 perform the above-mentioned cumulative addition operation, but when a cycle signal is input, the output of the latch circuit 104 is taken into the latch circuit 105 and multiplied by 1/2. or 3/
The latch circuit 104 is multiplied by 4 or 778 times.
is added to the input side of . This is the clock signal (bus 30
3), the data is taken into the latch circuit 104 and new cumulative addition begins. In this case, a weighted average of the value calculated in the previous cycle and the value to be calculated in the current cycle is calculated, and although it takes time for the calculation results to converge, it is less likely to oscillate. Self-study operations are performed as follows. Note that pack propagation (
The mathematical basis for this method is described in detail in, for example, an article in the August 10, 1987 issue of Oral Electronics, page 115 onwards. First, the output value of each neuron is obtained by repeating the cumulative addition operation and stored in the latch circuit 105. Next, the address of the neuron belonging to the output layer is sent to the control device 2 via the address bus 302.
The content of the latch circuit 105 is read into the control unit 12200 side and the difference between the expected output value (
Hereinafter, this value will be referred to as the δ value) and is written to the latch circuit 805 of that neuron via the bus 833. For neurons that do not belong to the output layer, address bus 3
The signal on 02 is fixed to the address of the neuron for which the δ value is to be determined, and the δ value is determined by cumulatively adding the product of the weight value of each neuron and the δ value of each neuron for that neuron. The weight value is applied from the memory 101 in each neuron, and the δ value is applied from the latch circuit 805 in each neuron to the multiplier 102 in each neuron via selectors 802 and 806, respectively. This first determines the product. next,
The address of each neuron is sequentially sent from the control device 1i 200 via the bus 831, and the current product is read into the control device 1i 200 via the bus 832. This value is cumulatively added within the control device 200 to obtain the δ value, which is written to the latch circuit 805 of the target neuron. Once the δ values of all neurons have been determined, the multiplier 102 calculates the product of the appropriate coefficient sent via the bus 837 and the δ value stored in the latch circuit 805, and adds the product to one end of the adder 103. And address bus 302
While passing the address signal applied through the adder 103, the weight value stored in the memory 101 and the value added to one end of the adder 103 are added together, and the result is updated as a new weight value. Self-learning occurs by repeating this process. It goes without saying that it is also possible to perform learning on a separate computer, write the weight values obtained as a result directly into the memory 101, and perform only normal operations on the neural network of the present invention. stomach.

【Effect of the invention】

As described above, according to the present invention, it is possible to realize a neural network in which the amount of hardware does not increase dramatically even when the number of neurons is increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a timing diagram for explaining its operation, FIG. 3 is a block diagram showing a part of another embodiment of the present invention, and FIG. 5 is a timing chart for explaining its operation, and FIGS. 6 to 8 are block diagrams showing a part of still other embodiments of the present invention. Description of symbols 100...neuron, 101...memory for storing weight values, 1o2...multiplier forming a synapse, 200...control device, 301-305...first
Floor JI bus, 311-315...2nd floor bus,
321 to 325: third layer buses. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] 1. Multiple functional blocks (hereinafter referred to as neurons)
There is an individually determined coefficient (hereinafter referred to as a weight value) between each neuron and another neuron,
In an information processing device configured such that the output value of each neuron is determined according to the sum of products of output values of other neurons and weight values, an address signal for specifying one of the plurality of neurons is used. , an address bus for transmitting the address signal and an output bus for transmitting the output signal of each neuron, and the neuron sends an output signal to the output bus only when specified by the address signal. An information processing device characterized by being configured as follows. 2.Equipped with multiple neurons, each neuron has an individually determined weight value between each neuron and other neurons, and the output value of each neuron is the sum of the products of the output values of other neurons and the weight values. In the information processing device configured to be determined according to An information processing device comprising a second layer bus that is commonly provided and connected to the first layer buses of the plurality of groups. 3. The information processing apparatus according to claim 2, wherein the second layer bus is wired with a wider conductor than the first layer bus. 4. A clock signal is provided, and signal transmission between the first layer bus and the second layer bus is performed in synchronization with the clock signal.
information processing equipment. 5. In an information processing device in which a plurality of semiconductor integrated circuits having the same shape are provided on the same semiconductor substrate and a common bus is provided to connect the plurality of semiconductor integrated circuits, the common bus is connected to the plurality of semiconductor integrated circuits. An information processing device characterized in that the wiring is made of a conductor wider than the signal wiring in a semiconductor integrated circuit. 6. In an information processing device in which a plurality of semiconductor integrated circuits having the same shape are provided on the same semiconductor substrate and a common bus is provided to connect the plurality of semiconductor integrated circuits, a clock signal is provided and the common bus is provided. An information processing device characterized in that signal transmission between the bus and the signal wiring in the plurality of semiconductor integrated circuits is performed in synchronization with the clock signal. 7. In an information processing device in which a plurality of semiconductor integrated circuits having the same shape are provided on the same semiconductor substrate and a plurality of sets of common buses connected to the plurality of semiconductor integrated circuits are provided, At least one set of the buses directly connects signals at corresponding positions in the plurality of semiconductor integrated circuits, and at least one of the other sets of the plurality of buses
An information processing device characterized in that the pairs connect signals at corresponding positions in the plurality of semiconductor integrated circuits while shifting them to each other. 8. The information processing apparatus according to claim 7, wherein the bus connected while being shifted transmits a signal provided for selecting a specific one from among the plurality of semiconductor integrated circuits. 9. Equipped with multiple neurons, each neuron has an individually determined weight value between each neuron, and the output value of each neuron is the sum of the products of the output values of other neurons and the weight values. 1. An information processing apparatus configured to determine the weight value according to the weight value, wherein the weight value is stored in a semiconductor memory device provided in a neuron on the side receiving the signal. 10. A plurality of neurons are provided, and each neuron has an individually determined weight value between each neuron and another neuron,
In an information processing device configured such that the output value of each neuron is determined according to the sum of the products of the output values of other neurons and weight values, the weight values are determined from a predetermined value on the signal receiving side starting from the one with the largest absolute value. An information processing device characterized by storing only the number of items. 11. The information processing apparatus according to claim 9 or 10, wherein the weight values are arranged and stored in the order in which they are accessed.