JPH02237232A - Optical receiving circuit - Google Patents

Optical receiving circuit

Info

Publication number
JPH02237232A
JPH02237232A JP1056265A JP5626589A JPH02237232A JP H02237232 A JPH02237232 A JP H02237232A JP 1056265 A JP1056265 A JP 1056265A JP 5626589 A JP5626589 A JP 5626589A JP H02237232 A JPH02237232 A JP H02237232A
Authority
JP
Japan
Prior art keywords
circuit
threshold voltage
apd
voltage
peak value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1056265A
Other languages
Japanese (ja)
Inventor
Kaoru Fukushima
福島 薫
Teruhiko Takahashi
高橋 輝彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Miyagi Ltd
Original Assignee
NEC Corp
NEC Miyagi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Miyagi Ltd filed Critical NEC Corp
Priority to JP1056265A priority Critical patent/JPH02237232A/en
Publication of JPH02237232A publication Critical patent/JPH02237232A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Optical Communication System (AREA)
  • Manipulation Of Pulses (AREA)
  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To reduce a deviation from an optimum threshold voltage at a full AGC time by setting a voltage proportional to the bias voltage control voltage of an avalanche photo diode (APD) to be the threshold voltage of an identification circuit. CONSTITUTION:An output from APD 1 is given to the identification circuit 10 through an equalizing amplifier circuit 2 and is given to a peak value detection circuit 3. The peak value detection circuit 3 detects the peak value of a light-receiving level. The peak value signal is amplified in amplifier circuits 4 and 5 and is given to APD 1 through a DC/DC converter 6 as the bias voltage control voltage. The output of the amplifier circuit 4 is converted the gain level in a gain/level conversion circuit 9 and is given to the identification circuit 10 as the threshold voltage. The identification circuit 10 identifies the light- receiving level based on the threshold voltage. Thus, the deviation from the optimum threshold voltage at the time of AGC can be reduced, and identification in the identification circuit can be set optimum.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は光受信回路に関し,特に受光素子としてアバラ
ンシェフォトダイオード(APD)を用いた光受信回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an optical receiving circuit, and more particularly to an optical receiving circuit using an avalanche photodiode (APD) as a light receiving element.

〔従来の技術〕[Conventional technology]

一般に,APDを用いた光受信回路では,APDからの
出力を等化増幅回路を介して識別回路に与え,一方,等
化増幅回路の出力はピーク検出回路に与えられ,ピーク
検出回路での検出ピーク値に基づいてAPDのバイアス
電圧を制御している。
Generally, in an optical receiving circuit using an APD, the output from the APD is given to an identification circuit via an equalization amplifier circuit, while the output of the equalization amplifier circuit is given to a peak detection circuit, which detects the output from the APD. The bias voltage of the APD is controlled based on the peak value.

識別回路では予め定められたスレッショルド電圧に基づ
いて受光レベルを識別しており,このスレッショルド電
圧は等化増幅器から与えられるかまたは識別回路自体で
発生している。
The identification circuit identifies the received light level based on a predetermined threshold voltage, and this threshold voltage is provided by an equalizing amplifier or generated by the identification circuit itself.

つまり,従来の光受信回路では受光レベルに対してスレ
ッショルド電圧は常に一定電圧となっている。
In other words, in conventional optical receiving circuits, the threshold voltage is always a constant voltage with respect to the received light level.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述のように従来の光受信回路の場合,識別回路のスレ
ッショルド電圧を受光レベルに対して一定としている。
As mentioned above, in the case of the conventional optical receiver circuit, the threshold voltage of the identification circuit is kept constant with respect to the light reception level.

ところが,APDでは,電流増倍率(M)の増減に応じ
てAPDの出力に重畳される雑音分布が変化する。この
結果,AFDの出力,つまり受光レベルに応じて最適の
スレッショルド電圧が変化する。
However, in an APD, the noise distribution superimposed on the output of the APD changes as the current multiplication factor (M) increases or decreases. As a result, the optimal threshold voltage changes depending on the output of the AFD, that is, the level of received light.

従って,従来の光受信回路では,Fu11(全)AGO
の際,受光レベルに対して常にスレッショルド電圧一定
としているから,最適なスレッショルド電圧からずれる
という問題点がある。
Therefore, in the conventional optical receiver circuit, Fu11 (all) AGO
In this case, since the threshold voltage is always kept constant with respect to the light reception level, there is a problem that the threshold voltage deviates from the optimum threshold voltage.

〔問題点を解決するための手段〕[Means for solving problems]

本発明によれば,受光レベルに応じてバイアス電圧が調
整される受光素子と,該受光素子からの出力を受け,該
出力のレベルを予め定められたスレッショルド電圧に基
づいて識別する識別回路とを有する光受信回路において
,前記バイアス電圧を制御する制御電圧に応じて前記ス
レッショルド電圧を調整する調整手段を備えることを特
徴とする光受信回路が得られる。
According to the present invention, a light receiving element whose bias voltage is adjusted according to a received light level, and an identification circuit that receives an output from the light receiving element and identifies the level of the output based on a predetermined threshold voltage are provided. There is obtained an optical receiving circuit comprising: an adjusting means for adjusting the threshold voltage in accordance with a control voltage for controlling the bias voltage.

〔実施例〕〔Example〕

以下本発明について実施例によって説明する。 The present invention will be explained below with reference to Examples.

第1図を参照して,本発明による光受信回路はAPD 
1,等化増幅回路2,ピーク値検出回路5,増幅回路4
及び5,DC/DCコンバータ6,識別回路9,及び利
得・レベル変換回路10を備えている。
Referring to FIG. 1, the optical receiving circuit according to the present invention is an APD.
1, equalization amplifier circuit 2, peak value detection circuit 5, amplifier circuit 4
and 5, a DC/DC converter 6, an identification circuit 9, and a gain/level conversion circuit 10.

APD 1からの出力は等化増幅回路2を介して識別回
路9に与えられるとともにピーク値検出回路乙に与えら
れる。ピーク値検出回路3では受光レベルのピーク値を
検出し,ピーク値信号として出力する。このピーク値信
号は増幅回路4及び5で増幅され,さらにDo/DC!
コンバータ6を介してバイアス電圧制御電圧としてAP
D 1に与えられる。
The output from the APD 1 is given to the identification circuit 9 via the equalization amplifier circuit 2 and also given to the peak value detection circuit B. The peak value detection circuit 3 detects the peak value of the received light level and outputs it as a peak value signal. This peak value signal is amplified by amplifier circuits 4 and 5, and then Do/DC!
AP as bias voltage control voltage via converter 6
D 1 is given.

増幅回路4の出力は利得・レベル変換回路10に与えら
れ,利得レベル変換されてスレッショルド電圧として識
別回路9に与えられる。
The output of the amplifier circuit 4 is applied to a gain/level conversion circuit 10, where the gain level is converted and the output is applied to the identification circuit 9 as a threshold voltage.

識別回路9はこのスレッショルド電圧に基づいて受光レ
ベルを識別する。
The identification circuit 9 identifies the received light level based on this threshold voltage.

ところで,  Full AGOの際には,APD1の
受光レベルの変動に応じてAPD 1のバイアス電圧制
御電圧7が変動して,APD1の電流増倍率(M)を変
化させる。この際,APD1の電流増倍率(M)の変化
に対応して,APD1における過剰増倍雑音量が増減す
る。この過剰増倍雑音量は等化増幅回路2の等化波形出
力のハイレベル,ロウレベルに等しく重畳されるわけで
はなく,どちらか一方に偏る。その結果,利4・レベル
変換回路10からのスレッショルド電圧はAPDの電流
増倍率(M)による過剰増倍雑音量の変化により変化す
る。即ち,APD1のバイアス電圧制御電圧と比例した
電圧を識別回路9のスレッショルド電圧とすることによ
り,最適スレッショルド電圧からのずれを小さくするこ
とができる。その結果,識別回路における識別を最適と
することができる。
By the way, during Full AGO, the bias voltage control voltage 7 of the APD 1 changes in accordance with the change in the light reception level of the APD 1, thereby changing the current multiplication factor (M) of the APD 1. At this time, the amount of excessive multiplication noise in the APD 1 increases or decreases in response to a change in the current multiplication factor (M) of the APD 1. This excessively multiplied noise amount is not superimposed equally on the high level and low level of the equalized waveform output of the equalizing amplifier circuit 2, but is biased toward one side. As a result, the threshold voltage from the gain/level conversion circuit 10 changes due to the change in the amount of excessive multiplication noise due to the current multiplication factor (M) of the APD. That is, by setting the threshold voltage of the identification circuit 9 to a voltage proportional to the bias voltage control voltage of the APD 1, deviation from the optimum threshold voltage can be reduced. As a result, the identification in the identification circuit can be optimized.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明では,APDのバイアス電圧
制御電圧と比例する電圧を識別回路のスレッショルド電
圧としているから,  FullAGO時における最適
スレッショルド電圧からのずれを極めて小さ《すること
ができるという効果がある。
As explained above, in the present invention, since the voltage proportional to the bias voltage control voltage of the APD is used as the threshold voltage of the discrimination circuit, there is an effect that the deviation from the optimum threshold voltage during Full AGO can be extremely small. .

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明による光受信回路の実施例を示すブロッ
ク図である。 1・・・アバランシェフォトダイオード(APD),2
・・・等化増幅回路,3・・・ピーク値検出回路,4,
5・・・増幅回路,6・・・Do/Doコンバータ,7
・・・APDのバイアス電圧制御電圧,8・・・スレッ
ショルド電圧,9・・・利得・レベル変換回路。 以下余白
FIG. 1 is a block diagram showing an embodiment of an optical receiving circuit according to the present invention. 1... Avalanche photodiode (APD), 2
... Equalization amplifier circuit, 3 ... Peak value detection circuit, 4,
5... Amplifier circuit, 6... Do/Do converter, 7
... APD bias voltage control voltage, 8... Threshold voltage, 9... Gain/level conversion circuit. Margin below

Claims (1)

【特許請求の範囲】[Claims] 1、受光レベルに応じてバイアス電圧が調整される受光
素子と、該受光素子からの出力を受け、該出力のレベル
を予め定められたスレッショルド電圧に基づいて識別す
る識別回路とを有する光受信回路において、前記バイア
ス電圧を制御する制御電圧に応じて前記スレッショルド
電圧を調整する調整手段を備えることを特徴とする光受
信回路。
1. An optical receiving circuit having a light receiving element whose bias voltage is adjusted according to the level of received light, and an identification circuit that receives the output from the light receiving element and identifies the level of the output based on a predetermined threshold voltage. An optical receiving circuit characterized in that it comprises an adjusting means for adjusting the threshold voltage according to a control voltage that controls the bias voltage.
JP1056265A 1989-03-10 1989-03-10 Optical receiving circuit Pending JPH02237232A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1056265A JPH02237232A (en) 1989-03-10 1989-03-10 Optical receiving circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1056265A JPH02237232A (en) 1989-03-10 1989-03-10 Optical receiving circuit

Publications (1)

Publication Number Publication Date
JPH02237232A true JPH02237232A (en) 1990-09-19

Family

ID=13022249

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1056265A Pending JPH02237232A (en) 1989-03-10 1989-03-10 Optical receiving circuit

Country Status (1)

Country Link
JP (1) JPH02237232A (en)

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