JPH02237273A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To avoid the invasion of noise onto an image pickup video signal by giving a power voltage to a nonvolatile memory only for a prescribed period during a vertical blanking period and reading out the flaw address of a solid- state image pickup element, thereby writing the address into a random access memory. CONSTITUTION:A power voltage is given to a nonvolatile memory 5 only for a prescribed period during the vertical blanking period of an image pickup signal from a solid-state image pickup element 2 based on a control signal from a timing signal generating circuit 7 to read out the flow address of the solid-state image pickup element 2, thereby writing the address into a random access memory 9. Then the flaw address of the solid-state image pickup element 2 is read from the random access memory 9 to correct the signal of the flaw address correspondence section of the video signal obtained from the solid-state image pickup element 2. Thus, the invasion of noise into the image pickup video signal from the solid-state image pickup element is avoided by giving a power voltage to the nonvolatile memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device including a solid-state imaging device such as a CCD and a nonvolatile memory in which defective addresses thereof are stored.

[Summary of the invention]

The present invention includes a solid-state image sensor, a non-volatile memory in which defective addresses of the solid-state image sensor are stored, and a timing signal generation circuit that supplies timing signals to the solid-state image sensor and the non-volatile memory, respectively. Based on the control signal from the timing signal generation circuit, the
Applying power supply voltage only for the predetermined period required for reading,
In a solid-state imaging device that reads a defective address of a solid-state imaging device and corrects a signal in a portion corresponding to the defective address of an imaged video signal from the solid-state imaging device, a random access memory is provided, and a control signal from a timing signal generation circuit is provided. Based on this, the power supply voltage is applied to the nonvolatile memory only during a predetermined period during the vertical retrace period of the imaged video signal from the solid-state image sensor, and the defective address of the solid-state image sensor is read out and written to the random access memory. By reading the defective address of the solid-state image sensor from the random access memory and correcting the signal of the defective address corresponding part of the video signal obtained from the solid-state image sensor, the power supply voltage can be applied to the nonvolatile memory. This makes it possible to avoid noise from being mixed into the captured video signal from the solid-state image sensor.

[Prior Art] In a solid-state imaging device (semiconductor imaging device) such as a CCD, if there is a crystal defect in a part of the semiconductor crystal, electric charges are likely to be generated in the defective part due to thermal causes. In some parts, the dark current is larger than in parts without crystal defects. For this reason, the video signal obtained by imaging
Noise with a level higher than the white level is mixed in, making the reproduced image difficult to see. Furthermore, black noise due to crystal defects may be mixed into the video signal obtained by imaging.

Therefore, conventionally, as disclosed in Japanese Patent Publication No. 6 0-3 4 8 7 2, the address data of the defective part of the solid-state image sensor, that is, the data of its horizontal address and vertical address, has been prepared in advance. By writing data into ROM, when sampling and holding the video signal obtained from the solid-state image sensor during imaging, the signal corresponding to the address of the defective part can be replaced with the previous signal, or the signals before and after it can be replaced. Replacement with an average signal is performed.

In addition, as disclosed in the same publication, instead of writing the data of the address of the defective part of the solid-state image sensor directly into the ROM, the data of the address of the defective part of the solid-state image sensor is written at the reference point, that is, at the first horizontal scanning line of the field of the solid-state image sensor. Data on the scanning start point and the distances on the horizontal scanning line between adjacent ones of one or more defective portions that follow sequentially are also written into the ROM.

A conventional solid-state imaging device of this type will be described below with reference to FIG. Figure 1 shows the main parts of the solid-state imaging device, and (2) shows the CCD (red,
(consisting of three CCDs for green and blue signals or one COD for monaural signals), and employs, for example, an interline transfer method as a charge transfer method. and,
This COD (2) includes a timing signal generation circuit (IC
) (7), horizontal and vertical transfer pulses based on horizontal and vertical synchronization pulses, etc. are provided. C C D (2
) is supplied to a sample and hold circuit (3) and sampled and held. This sample bold circuit (3) is supplied with a sampling pulse from a timing signal generation circuit (7).

The sample and hold output from the sample bold circuit (4) is supplied to the signal processing circuit (4). The signal processing circuit (4) performs gain correction, composite signal processing, etc. on the sample and hold output, and outputs a composite video signal to the output terminal (8).

(5) EEFROM (Electrically Erasable and Programmable Memory) is a non-volatile memory.
This is a read-only memory (read-only memory) that stores various data, but here it is shared to store the defective address of C O D (2). This R O
M (5) is supplied with an address signal from the timing signal generation circuit (7) at the time of reading. The readout output is the control circuit (IC) (6)
The defective address data therein is supplied to the timing signal generation circuit (7).

Next, for R O M (5), C C D (2
) writing of a defective address will be explained. Although not shown, an address detection circuit is provided outside the solid-state imaging device. Then, C O D (2) is irradiated with uniform light of various intensities (including light with an intensity of O), and a video signal obtained from the signal processing circuit (4) and a timing generation circuit (7) are generated. Based on the horizontal and vertical synchronization pulses obtained from C C D (2)
Detect defective addresses. Data of the detected defective address and data indicating whether the field is odd or even, or
The reference point, i.e., the scan start point of the first horizontal scan line of the field of C C D (2) and sequentially following <1+[l
Data on the distance on the horizontal scanning line between adjacent defective parts of il and a data indicating whether the field is odd or even are supplied to R OM (5) and written there.

Next, based on the data of the defective address written in R O M (5) in this way, C C D (
2) will be explained with reference to FIG. 4 as well. Figure 4 A and B are respectively C C
The horizontal and vertical synchronization pulses that form the basis of the horizontal and vertical transfer pulses supplied to D (2) are shown. Now, in Figure 4B,
If there is a defect in the line indicated by "×", in the horizontal retrace period before and after it, the power supply voltage (AC power supply voltage is rectified and smoothed by a rectifier circuit, and the smoothing capacitor is The timing signal generation circuit (for example, a DC voltage of 5 cm) with f4W applied to both ends is applied.
7) to R OM (5) is supplied with a power supply voltage modulation control signal shown in FIG. 4C. Then, during the earlier horizontal retrace period, the vertical address V of the defective address shown in FIG. 4E stored in addresses O, 1, and 2 of R O M (5) shown in FIG. 4D is read out. At the same time, the horizontal address H of the defective address stored in addresses 3, 4, and 5 of ROM (5) shown in FIG. 4D is read out and loaded into the counter of the timing signal generation circuit (7). Cheating. This counter counts horizontal and vertical transfer pulses.

Then, by the count output of this counter, C O D
When the arrival of a defective portion of the imaged video signal supplied from (2) to the sample hold circuit (3) is detected, the timing signal generation circuit (7) temporarily stops supplying the sampling signal to the sample bold circuit (3). for example, to hold previously sampled data. Below, this operation is expressed as the number of defective parts in C O D (2) &
, l repeat.

[Problem to be solved by the invention]

In this way, in the conventional solid-state imaging device, the power supply voltage is applied to R O M (5) only when reading the address of the defective part of CCD (2) from R O M (5). Power consumption can be reduced compared to always applying the power supply voltage to R O M (5), but the timing of supplying the power supply voltage to R O M (5) is during the horizontal retrace period, but the smoothing capacitor Since the discharge current from the C O D (2) flows to the ground line even during the video period after the horizontal retrace period, the captured video signal output from the C There was a drawback that noise caused by sushi was mixed in. still,
In particular, R OM (5) is a bipolar transistor I
In the case of C, if the power supply voltage is always applied, the power consumption will be too large to be ignored.

In view of the above, the present invention provides a solid-state image sensor, a non-volatile memory in which defective addresses of the solid-state image sensor are stored, and a timing signal generation circuit that supplies timing signals to the solid-state image sensor and the non-volatile memory, respectively. Based on the control signal from the timing signal generation circuit, a power supply voltage is applied to the nonvolatile memory only for a predetermined period required for reading out the defective address of the solid-state image sensor, and the defective address of the solid-state image sensor is read out. In a solid-state imaging device that corrects the signal of the defective address corresponding part of the captured video signal, when reading the defective address of the solid-state imaging device from the nonvolatile memory, even if the power supply voltage is supplied to the nonvolatile memory, the solid state The purpose of this invention is to propose something that can avoid noise from being mixed into the captured video signal output from the image sensor, making the reproduced image difficult to see.

[Means to solve the problem]

The present invention provides a solid-state image sensor (2) and a solid-state image sensor (2).
Non-volatile memory (5) in which the defective address of 2) is stored
and the solid-state image sensor (2) and non-volatile memory (5),
Based on the control signal from the timing signal generation circuit (7), the power supply voltage is applied to the nonvolatile memory (5) only for a predetermined period required for reading the nonvolatile memory (5). , read the defect address of the solid-state image sensor (2), and read the signal of the defect address corresponding part of the imaged video signal from the solid-state image sensor (2). In a solid-state imaging device configured to correct ili,
A random access memory (9) is provided, and based on a control signal from a timing signal generation circuit (7), a non-volatile memory is provided only during a predetermined period during a vertical retrace period of the captured video signal from the solid-state image sensor (2). Applying power supply voltage to the memory (5), reading out the defective address of the solid-state image sensor (2),
The defect address of the solid-state image sensor (2) is written in the random access memory (9), and the defect address of the solid-state image sensor (2) is read from the random access memory (9), and the signal of the defect address corresponding part of the video signal obtained from the solid-state image sensor (2) is written. Try to correct it.

[Effect]

According to the present invention, the timing signal generation circuit (7)
Based on the control signal from the solid-state image sensor (2), a power supply voltage is applied to the non-volatile memory (5) only during a predetermined period during the vertical retrace period of the captured video signal from the solid-state image sensor (2).
) and write it to the random access memory (9), and write it to the random access memory (9).
), the defect address of the solid-state image sensor (2) is read out, and the signal of the defect address corresponding portion of the video signal obtained from the solid-state image sensor (2) is corrected.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. 1. In FIG. 1, parts corresponding to those in the conventional example shown in FIG. Omitted. 1st
As shown in the figure, timing signal generation circuit (IC) (7)
A RAM (random access memory) (9) is provided. This R A M (9) consists of a CMOS transistor, and the address of the defective part of C C D (2),
That is, since it is sufficient to have a capacity to store horizontal and vertical addresses for the maximum possible number of defective parts, the capacity can be quite small, so that the power supply voltage is constantly supplied to this RAM (9). However, the power consumption is extremely small. Note that (7a) indicates a timing generator.

Next, a method of correcting the video signal from CCD (2) based on the data of the defective address written in ROM (5) will be explained with reference to FIG. 2 as well. FIGS. 2A and 2B show the horizontal and vertical synchronization pulses underlying the horizontal and vertical transfer pulses supplied to CCD(2), respectively. Now, suppose that there is a defect in the line indicated by "x" in FIG. 2B. In this case, as shown in Figure 2C,
During the vertical retrace period, for example, the timing signal generator (7a) outputs the timing signal from the timing signal generator (7a) so that the power supply voltage is supplied to R O M (5) over one horizontal cycle period. The power supply voltage modulation control signal shown in FIG. 2C is supplied to R O M (5), and during the high level period of the power supply voltage modulation control signal as shown in FIG.
From the timing signal generator (7a) to R O M (5)
By providing horizontal and vertical address signals to
The C O D stored in that R O M (5)
(2) All defective addresses are read out during the high level period of the power supply voltage modulation control signal in FIG. 2E, and R A
Write in M (9). Then, when the high level period of this power supply voltage modulation control signal ends, the ROM
The address signal input terminal (5) is made to exhibit high impedance, so that the timing signal generation circuit (
7) The timing signal generator (7a) will no longer be destroyed.

After that, from this R A M (9), R O M
Using the same address counter [built in the timing signal generator (7a)] as for (5), R
The vertical address ■ of the defective address shown in FIG. 2F stored in addresses O, 1, and 2 of A M (9) is read out, and the addresses 3 and 4 of R A M (9) shown in FIG. 2 F are read out. , 5 of the defective address is read out and loaded into the built-in counter of the timing signal generator (7a). This counter counts horizontal and vertical transfer pulses.

I3 Then, by the count output of this counter, C C D
When the arrival of a defective portion of the imaged video signal supplied from (2) to the sample and hold circuit (3) is detected, the timing signal generation circuit (7) temporarily stops supplying the sampling signal to the sample and hold circuit (3). for example, to hold previously zumbling data. Thereafter, this operation is repeated as many times as there are defective parts in C O D (2).

According to the solid-state imaging device described above, the random access memory (9) is provided, and based on the control signal from the timing signal generation circuit (7), the captured video signal from the solid-state imaging device (2) is processed during the vertical blanking period. A power supply voltage is applied to the nonvolatile memory (5) only during a predetermined period of time, the defective address of the solid-state image sensor (2) is read out, and the random access memory (9) is read out.
), the defective address of the solid-state image sensor (2) is read from the random access memory (9), and the signal corresponding to the defective address of the video signal obtained from the solid-state image sensor (2) is corrected. This makes it possible to avoid noise from being mixed into the captured video signal from the solid-state image sensor (2) due to the application of the power supply voltage to the nonvolatile memory (5).

〔Effect of the invention〕

According to the present invention described above, a random access memory is provided, and power is supplied to the nonvolatile memory only during a predetermined period during a vertical retrace period of an imaged video signal from a solid-state image sensor based on a control signal from a timing signal generation circuit. Apply voltage, read the defective address of the solid-state image sensor, write it to the random access memory, read the defective address of the solid-state image sensor from the random access memory, and write the defective address correspondence section of the video signal obtained from the solid-state image sensor. Since the signal is corrected, it is possible to avoid noise from being mixed into the captured video signal from the solid-state image sensor due to applying the power supply voltage to the nonvolatile memory.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a timing chart 1 for explaining the same, Fig. 3 is a block diagram showing a conventional example, and Fig. 4 is a timing chart for explaining the same. It is. (2) is COD, (3) is sample hold circuit, (4
) is a signal processing circuit, (5) is a ROM, (6) is a control circuit, (7) is a timing signal generation circuit, (7a)
is a timing signal generator, (8) is an output terminal, and (9) is a RAM.

Claims (1)

[Scope of Claims] A solid-state image sensor, a non-volatile memory in which defective addresses of the solid-state image sensor are stored, and a timing signal generation circuit that supplies timing signals to the solid-state image sensor and the non-volatile memory, respectively. and based on a control signal from the timing signal generation circuit,
A power supply voltage is applied to the nonvolatile memory only for a predetermined period required for reading out the defective address of the solid-state image sensor, and the signal of the defective address corresponding portion of the imaged video signal from the solid-state image sensor is corrected. In the solid-state imaging device, a random access memory is provided, and the non-volatile memory is activated only during a predetermined period during a vertical retrace period of a captured video signal from the solid-state imaging device based on a control signal from a timing signal generation circuit. Applying a power supply voltage to the memory, reading the defective address of the solid-state image sensor and writing it into the random access memory, reading the defective address of the solid-state image sensor from the random access memory, and reading the defective address of the solid-state image sensor obtained from the solid-state image sensor. A solid-state imaging device characterized in that the signal of the defective address corresponding portion of the video signal is corrected.