JPH0223885B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a clock mechanism for an electronic computer, and in particular reduces the number of gates and the number of input/output pins in the clock mechanism, and also reduces the overhead required for reading and writing the clock mechanism. Relating to techniques suitable for reducing.

[Background of the invention]

An example of a conventional clock mechanism is shown in FIG. Here, it is assumed that register 2 (hereinafter referred to as TTM) is composed of 32 bits. The value of TIM is always incremented by 1 by the adder circuit 3 and set in the register 4 at an appropriate timing. The selection circuit 1 normally inputs the output of the register 4 to TIM. TIM is triggered once every microsecond and sets the value of register 4. Through this series of operations, TIM can be used as a clock that increases by 1 every microsecond. In addition, writing TIM (time setting)
And TIM reading (time reading) is commanded by a microprogram. Now, when writing of TIM is commanded, selection circuit 1 selects INBUS and sets the value of INBUS in TIM. if,
If the write command and TIM update time overlap, only the write command will be executed and the TIM will not be updated. Also, when TIM reading is commanded,
The TIM value is output to OUTBUS. At this time, if the TIM update timing and the output timing to OUTBUS are made different, the TIM can be read at any time by the microprogram. Figure 5 shows the time chart.
In FIG. 5, stages A to J are each one machine cycle, and one machine cycle is 100 nanoseconds. Therefore, a total of 10 machine cycles from A to J is 1 microsecond. TIM is always stage A
Suppose that it is updated in the latter half of . In the fifth case 1,
This shows the contents of OUTBUS when reading is commanded by the microprogram at stage A. In this way, by outputting the contents of TIM to OUTBUS from the first half to the second half of stage A, the microprogram can decode the contents. Fifth
Case 2 in the figure shows the situation when reading is commanded at stage B. Similarly, no matter where reading is commanded in stages C to J, reading is possible immediately. As described above, the example shown in FIG. 1 is very efficient in terms of microprogramming, but as is clear from FIG. 1, it requires a width of 4 bytes and has the disadvantage of requiring a very large amount of hardware.

FIG. 2 shows another conventional example. Here, registers 9 to 12 (hereinafter referred to as TIM0 to 3) each consist of 8 bits, and the total of TIM0 to 3 is 32 bits.
Consists of bits. When updating TIM0 to TIM3 once every microsecond, the selection circuit 13 selects TIM3, 2, 1,
One byte of TIM0 to TIM3 is selected consecutively in the order of 0 and inputted to the 1-byte wide adder circuit 14.
The addition circuit 14 always adds +1 when the selection circuit 13 selects TIM3;
When TIM2 is selected, depending on whether or not there is a carry when adding +1 to the value of TIM3, if there is a carry, +1 is added, and if there is no carry, the value is sent as is to register 15. . The selection circuit 13
When TIM1 and TIM0 are selected, as when TIM2 is selected, +1 or the value as is is sent to the register 15 depending on whether or not there is a carry when adding the lower byte. Selection circuits 5 to 8 normally select register 15, and only when writing is commanded.
Select INBUS (4 bytes). Also, when read is commanded, the values of TIM0 to TIM3 are output to OUTBUS (4 bytes). Figure 6 shows a time chart of this method. A to J are the same as in FIG. In this method, since the adder circuit is 1 byte wide, TIM3, 2, 1,
0 is updated at stages A, B, C, and D, respectively. In this system, writing can be performed at any time when writing is commanded by the microprogram, but when reading is commanded, only stages E to J and A can be read. (Case 1 of OUTBUS in Figure 6 shows the case where reading is commanded at stage E, and case 2 shows the case where reading is commanded at stage A.) This is because, for example, reading is commanded at stage C,
If read immediately, TIM0 and TIM1
is the value before the update, but TIM2 and TIM3 are the values after the update, so the overall value of TIM0 to TIM3 is:
Unable to show correct current time. Therefore, in this method, reading by the microprogram is normally prohibited during stages A to D, and its execution is delayed until stage E is reached. Therefore, compared to the method shown in FIG. 1, the method shown in FIG. 2 has the disadvantage that although the number of gates is reduced, the number of input/output pins is not reduced, and the overhead on the microprogram is increased.

FIG. 3 shows yet another conventional example. The example in FIG. 3 is similar to the example in FIG. 2 with regard to updating TIM0 to TIM3. The difference from the example in FIG. 2 is that INBUS and OUTBUS are made 1 byte wide to reduce the number of input/output pins. Therefore, in the example shown in Figure 3, when writing is commanded by the microprogram, updating of TIM0 to TIM3 is stopped and the selection circuit 1
6 performs writing by selecting the INBUS side. Further, for reading, when TIM0 to TIM3 are not being updated, the selection circuit 17 selects one of TIM0 to TIM3 and reads it onto OUTBUS. Figure 7 shows a time chart of this method. In this method, reading is possible only when TIM0 to TIM3 are not updated, and since it takes four machine cycles to read, it can only be read in the four cases shown in OUTBUS cases 1 to 4. (Stage A in case 4 is actually TIM3
The selection circuit 1 in Fig. 3 is in the update operation.
7 selects TIM3, so change the value of TIM3.
It is possible to output to OUTBUS. )Therefore, although the system shown in FIG. 3 has a smaller number of input/output pins than the system shown in FIG. 2, it has the disadvantage that the overhead on the microprogram further increases.

In the above explanation, to simplify the explanation, the number of bytes of the clock is 4 bytes, the update interval of the lowest bit is 1 microsecond, and the clock is +1 clock 1.
However, the clocks actually used in electronic computers have a large number of bytes, have a long update interval for the least significant bit, and in addition to clocks that increase by +1, clocks that decrease by -1 are also used. However, when various measures are taken to reduce the amount of hardware, the period during which microprograms needlessly wait increases, which affects the execution of other urgent microprograms, which in turn worsens the performance of the computer. It was hot.

[Purpose of the invention]

An object of the present invention is to provide a clock mechanism that reduces the amount of hardware by reducing the number of gates and input/output pins without increasing the overhead of microprograms or adding complicated control circuits. It's about doing.

[Summary of the invention]

The present invention focuses on the problem that the conventional example has when reading the clock mechanism, and provides a circuit in the hardware that can be read out in a time-sharing manner at any time. By imposing limitations, the objectives of the present invention are achieved.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. FIG. 4 is similar to the conventional example shown in FIG. 3 except for the method of using the selection circuit 18 and the addition of the selection circuit 19. In other words, in FIG. 3, the selection circuit 17 is used for updating TIM0 to TIM3 and
However, in FIG. 4, the selection circuit 18 is used exclusively for updating TIM0 to TIM3, and the selection circuit 19 is used exclusively for outputting to OUTBUS. FIG. 8 is a time chart showing the update status of TIM0 to TIM3 in FIG. 4 and the read status in four cases, cases 1 to 4. As shown in Figure 8, TIM3,
2, 1, and 0 are updated in the latter half of stages A, B, C, and D, respectively. In case 1, the microprogram reads TIM3 at stage A, but at stage B.
The contents on OUTBUS are shown when reading TIM2 is commanded at stage C, TIM1 is commanded at stage C, and TIM0 is commanded at stage D. When each stage is instructed to read, it immediately outputs the contents of the instructed register onto OUTBUS through the selection circuit 19 in FIG. 4. The microprogram outputs OUTBUS at the center timing of each stage.
Import the contents of. Case 2 shows a case where a read command for TIM3 by the microprogram is issued at stage B, and read commands are issued up to TIM0 as shown in the figure below. In case 3,
A case is shown in which a read command for TIM3 is issued at stage J, and read commands for TIM0 are similarly issued thereafter. In this way, in the present invention, stages A to J
No matter where a microprogram read command is issued, reading is possible immediately. However, it must be noted here that the microprogram must issue read commands in the order of TIM3, 2, 1, and 0, and continuously. If you do not read TIM0, 1, 2, 3 in order, or read TIM3, 2, 1, 0 consecutively (see case 4), TIM0 to 3 as a whole may not be usable as the correct current time. be. (This is because the value before the update and the value after the update may be mixed depending on the byte position.) However, this level of restriction on microprograms has no important effect on the microprogram. not give.

When it is desired to set the time in TIM0 to TIM3 by a microprogram, it is also possible to temporarily stop updating TIM0 to TIM3 and then set the value, as explained in the conventional example in FIG. However, this requires a special control circuit in the hardware. However, according to the present invention, values can be set in TIM0 to TIM3 without adding any special control circuit by the method described below. Figure 9 shows that a TIM3 write command is issued by the microprogram at stage B.
Similarly, the TIM2 write command is at stage C,
Time charts are shown when the TIM1 write command is issued at stage D and the TIM0 write command is issued at stage E. In addition, TIM3, 2,
1 and 0 are the same as the 8th stage, respectively stages A, B,
Assume that C and D have been updated. In this case, if you put the desired value in TIM3 to INBUS in the microprogram from the first half of stage B to the first half of stage C, TIM3 will be set in the second half of stage B.
The contents of INBUS can be written. Subsequently, TIM2, 1, and 0 can be written in the same manner. FIG. 10 shows a time chart when a write command is issued by a microprogram from stage J. Further, FIG. 11 shows a time chart when a write command is issued by a microprogram from stage A. When update and write overlap in this way, only the write operation is performed and no update operation is performed. Note that this operation is
If the update timing of TIM0 to 3 and the data input timing from INBUS are set to the same timing, this can be easily achieved by selecting the INBUS side in the selection circuit shown in Figure 4 using the write request signal from the microprogram. No special control circuit is required. In this way, in the present invention, stage A
No matter where a microprogram write command is issued between ~J, writing is possible immediately. However, it must be noted here that the microprogram must issue write commands in the order of TIM3, 2, 1, and 0, and consecutively. If TIM0, 1, 2, and 3 are written in this order, or if TIM3, 2, 1, and 0 are not written in succession, it may not be possible to set the correct time for TIM0 to TIM3 as a whole. In Figure 12,
A time chart is shown when another microprogram is executed between TIM2 and TIM1 and TIM3, 2, 1, and 0 are not written consecutively. In this case, TIM3 and TIM2 write the time and then
It will be +1 at the next stage, but TIM1 and
Since TIM0 is not incremented by 1, an incorrect time will be set for TIM0-3 as a whole. However, this level of restriction on the microprogram does not have any significant effect on the microprogram.

In the explanation so far, for convenience of explanation, TIM3,
Although it is assumed that 2, 1, and 0 must be read or written continuously, in reality, this is not always necessary. For example, as shown in Figure 13
If you want to execute another microprogram for one machine cycle between TIM2 and TIM1, use TIM3,
2, 1, and 0 may be updated at stages A, B, D, and E, respectively. In other words, the necessary microprogram restrictions are as follows in the chronological order of updates of TIM3, 2, 1, and 0.
This is to match the read and write time series.

In addition, in the above explanation, for convenience of explanation, the number of bytes of the clock is 4 bytes, one machine cycle is 100 nanoseconds, and the update interval of the least significant bit of the clock is 1 microsecond. The machine cycle and the update interval of the least significant bit of the clock may be any value. The update interval of the least significant bit of the clock may not be evenly divisible by the machine cycle. (In that case,
Stages can be created by synchronizing the update interval of the least significant bit of the clock with machine cycles. ) The present invention can be applied to multiple types of clocks, such as updating a clock that increases by +1 in stages A to D, and updating a clock that increases by -1 in stages E to H. Furthermore, the clock can be updated not only by +1 and -1 but also by other additions and subtractions. Also, in FIG. 4, the adder circuit 14
The upper and lower positions of the register 15 may be changed.

〔Effect of the invention〕

According to the present invention, since a clock mechanism can be realized with less hardware, there is an effect of reducing the cost of an electronic computer. Furthermore, since the overhead of microprograms is reduced, it has the effect of improving the performance of electronic computers.

[Brief explanation of drawings]

1, 2, and 3 show the configuration of the conventional example, FIG. 4 shows the configuration of an embodiment of the present invention, FIG. 5 shows the time chart of FIG. 1, and FIG. 7 shows the time chart of FIG. 3, and FIGS. 8 to 13 show the time chart of FIG. 4. 1... Selection circuit, 2... Register, 3... Addition circuit, 4... Register, 5 to 8... Selection circuit, 9
~12...Register, 13...Selection circuit, 14...
...Addition circuit, 15...Register, 16-19...
selection circuit.

Claims (1)

[Claims] 1. The time storage unit consisting of multiple bits of the clock mechanism of a computer is divided into multiple blocks, and the operation of updating the value of the block based on the presence or absence of a carry from the lower block in units of blocks is performed starting from the lowest block. By sequentially updating the value of the time storage unit as many times as there are blocks up to the top block, and repeating this series of time updating operations at regular intervals, the stored time is updated at regular intervals. In the clock mechanism of an electronic computer, the clock mechanism has a function of reading out the time in block units from the lowest block to the lowest block in response to a time read command. The chronological order of the read timing of each block in the period up to the reading of the block is made to match the chronological order of the update timing of each block in the period from updating the lowest block to updating the highest block at the time of time update. Therefore, the period between a series of time update operations and the next series of time update operations, as well as
The feature is that even when any block is being updated during a series of time update operations, a series of time read operations can be executed without interrupting the update operation or waiting until the update of the topmost block is completed. A clock mechanism for an electronic computer.