JPH02239352A - Storage device - Google Patents

Abstract

PURPOSE:To detect the abnormality of a storage block at an early stage by reading information out of the storage block which has executed writing immediately before and confirming the normality of information when a next access does not continue in the same storage block. CONSTITUTION:When a data write request with respect to an address '0' is outputted to an external control signal bus 19, a storage control part 6 stores the address '0', opens a gate 8 and instructs a storage block 2 of the writing of data. The storage instruction of data on a bus 9 is given to an error detection part 7 by using an error detection part control signal 15. As to the write request with respect to a next address '1', data is written in a storage block 3. At that time, the control part 6 simultaneously gives a read instruction to the block 2. The reading is executed on an error detection-only bus 10. At that time, the detection part 7 compares data on the bus 10 with data in the block 2 which is previously stored and which has been written immediately before. When data do not coincide, the occurrence of data errors is informed to the control part 6.

Description

[Detailed description of the invention] (Industrial application field) The present invention relates to storage devices.

[Conventional technology]

Conventionally, errors in information in a main storage device are determined based on the read information when the information is read, and the normality of the information is not determined unless the information is actually needed.

(Problem to be Solved by the Invention) In the conventional information storage method described above, once the information is stored, the correctness of the information cannot be determined until it is actually needed, and the writing process may be incorrect. Even if there is, abnormality can only be detected during read processing, so it is difficult to generate correct write data when an abnormality occurs, and it is difficult to perform optimal recovery processing.

An object of the present invention is to provide a storage system that allows early detection of abnormalities in storage blocks.

[Means to solve the problem]

The storage device of the present invention has an internal data bus, an error detection dedicated data bus, and the first (I-1.2....,M) (1-.1).
+ (K-1)M A storage block group consisting of M storage blocks to which addresses of (K-1.2,...,N) are assigned and connected to an internal data bus; , is connected to an internal data bus and a data bus dedicated to error detection, is provided with a data storage section therein, and when the first error detection section control signal is input, stores the data on the internal data bus in the data storage section; When the second error detection unit control signal is input, the error detection unit compares the data on the error detection dedicated data bus with the data stored in the data storage unit, and outputs an error detection signal if they do not match. Write and read data are accessed independently to a memory block, and when there is an access request to a memory block, data on the internal data bus is written to the corresponding memory block or data is transferred from the corresponding memory block to the internal data bus. In the case of writing data, the write address is further stored internally and the first error detection unit control signal is output to the error detection unit. If the access is different from the memory block to which the data was accessed, the access is executed, the data written just before is read from the memory block to the error detection dedicated data bus, and the second error detection unit control signal is sent to the error detection unit. and a storage control section that reports to the outside that a data error has occurred when an error detection signal is input from the error detection section.

[Effect]

Therefore, an abnormality in the storage block can be detected early without degrading the normal access function to the storage block.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a main memory device according to an embodiment of the present invention;
FIG. 2 is a memory block address allocation diagram, and FIG. 3 is a timing diagram showing the operation of this embodiment.

The main memory device is composed of memory blocks 2.3, 4.5, a memory control section 6, an error control section 7, a gate 8, an internal data bus 9, and a data busco 0 dedicated to error detection. an external control signal bus 19 and an external data bus 2 including
0. The address allocation of memory blocks 2 to 5 is as shown in FIG. 2, and memory block 2 has addresses of 0.4, 8.・・・． 4N-4. Memory block 3 has 1, 5, 9. ..., 4N-3, memory block 4
2.6.10.・・・． 4N-2. memory block 5
3,7.11. ..., 4N-1 (N is an integer) addresses are assigned. Therefore, when accessing consecutive addresses, four memory blocks 2.3
．． 4.5 are sequentially accessed, and the four storage blocks 2.3.4.5 are accessed almost equally within a short period of time.

The error detection unit 7 is connected to the storage blocks 2 to 5 and the internal data bus 9.
It is connected by an error detection dedicated data bus 10 and has an internal data storage section, and receives a first error detection section control signal 1.
5 is input from the storage control unit 6, the data on the internal data bus 9 is stored in the data storage unit, and when the second error detection unit control signal 16 is input from the storage control unit 6, the error detection dedicated data bus The data on 0 is compared with the data of the memory block stored in the data storage section to which writing was performed immediately before, and if they do not match, an error detection signal 17 is output to the storage control section 6. The storage control unit 6 is externally connected to an external control signal bus 9, and controls each storage block 2, 3, .
4.5, data is independently written and read, and when there is an access request to a memory block, the gate 8 is heard by the gate υ1 control signal 18, and the corresponding memory block is accessed on the internal data bus 9. Write data or read data from the corresponding storage block onto the internal data bus 9, and in the case of data write, further:
The error detection unit 7 stores the write address internally.
The first error detection unit control signal 15 is output to the memory block, and if the object of the current access to the memory block is different from the memory block to which writing was performed immediately before, the access is executed, and the access is executed to the memory block to which writing was performed immediately before. reads the data from the storage block to the error detection dedicated data bus 10,
When the second error detection section control section signal 16 is outputted to the error detection section 7 and then the error detection signal 17 is inputted from the error detection section 7, the occurrence of a data error is reported to the outside.

Next, the operation of the main memory device Vf11 of this embodiment will be explained with reference to the timing diagram of FIG.

FIG. 3 shows addresses 0, 1, 2, etc. according to an external request.
3 is a timing diagram when data is pulled into address 3 and data is read out to address 4, 5.6. FIG.

First, when a data write request for address O is issued to the external control signal bus 19, the storage control unit 6 determines which storage block is to be accessed, and stores the address in an address storage unit provided within the storage control unit 6. do. In this case, since the address is 0, the access is to the memory block 2, and at the same time the address O is stored, the gate 8 is opened by the gate control signal 18, the external data bus 20 and the internal data bus 9 are connected, and the memory block control signal 11 to instruct the memory block 2 to write data, and then use the first error detection unit control code 15 to instruct the error detection unit 7 to connect the internal data bus to the data storage unit provided in the error detection unit 7. Give an instruction to store the data on 9.

Similar control is performed for the data write request to the next address 1, and data is written to the storage block 3. At the same time, in order to judge the normality of the data written to the memory block [1] stored in the memory control unit 6 of the memory block 2, in this case address O, the memory control unit 6 gives a read instruction to memory block 2 (hereinafter, a cycle in which reading is executed to determine the normality of data written to the address that was written immediately before is referred to as a verify read cycle) a This memory block Since the continuation to 2 is a verify read υ cycle, the storage block 2 outputs data onto the data bus 10 dedicated to error detection. At this time, the error detection section 7 receives an instruction from the storage control section 6 through the second error detection control signal 16, and collects the data on the error detection dedicated data busco 0 and the memory block to which writing was performed immediately before. If the two data do not match, it is recognized as an error and the storage controller 6 is notified through the error detection signal 17 that a data error has occurred. Upon receiving this data error detection notification, the storage control unit 6 immediately sends an external control signal bus 19 to the main storage device 1.
Report that a data error has occurred.

Similar control is performed for a data write request to the next address 2, and data is written to storage block 4, and at the same time, a verify read cycle is executed to storage block 3.

Note that the present invention can also be applied to general storage devices.

〔Effect of the invention〕

As explained above, the present invention provides a plurality of memory blocks to which addresses are assigned at regular intervals, a memory control unit that simultaneously and independently controls each memory block, and an error detection unit that detects an error in information in a memory element. When a storage device is configured with a detection unit and information is written to a storage block, if the next access is not consecutive to the same storage block, the previous access is executed at the same time as the next access to another block. By reading information from the same address of the memory block where the error detection was performed and confirming the normality of this information using the error detection unit, the reliability of the information is improved and an abnormality in the memory block can be detected at an early stage.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a main memory device according to an embodiment of the present invention;
FIG. 2 is a memory block address allocation diagram, and FIG. 3 is a timing diagram showing the operation of this embodiment. DESCRIPTION OF SYMBOLS 1... Main memory device, 2-5... Memory block, 6... Storage control part, 7... Error detection part, 8... Gate, 9... Internal data bus, 1o...・Data bus dedicated to error detection, 11 to 14... Storage block control signal, 15... First error detection section control signal, 16... Second error detection section control signal, 17... Error detection signal, 18... gated Ill signal, 19... external control signal bus, 20... external data bus.

Claims (1)

[Claims] 1. The internal data bus, the error detection dedicated data bus, and the I-th (I=1, 2,...,M) (I-1)+(K-
1) A memory block group consisting of M memory blocks to which M (K=1, 2,...,N) addresses are assigned and connected to an internal data bus, an internal data bus, and a data bus dedicated to error detection. is connected to the internal data bus and has a data storage section therein, and when the first error detection section control signal is input, the data on the internal data bus is stored in the data storage section, and when the second error detection section control signal is input, the data storage section is connected to the internal data storage section. , an error detection unit that compares the data on the error detection data bus with the data stored in the data storage unit and outputs an error detection signal if they do not match, and an error detection unit that writes data independently to each storage block. When a read access is performed and an access request is made to a memory block, data on the internal data bus is written to the corresponding memory block, or data is read from the corresponding memory block onto the internal data bus, and in the case of data writing, Furthermore, it stores the write address internally and outputs a first error detection unit control signal to the error detection unit, and if the target of the current access to the memory block is different from the memory block to which writing was performed immediately before, the access At the same time, the data written just before is read from the memory block to the error detection dedicated data bus, the second error detection unit control signal is output to the error detection unit, and then the error detection signal is output from the error detection unit. A storage device that has a storage control unit that reports to the outside that a data error has occurred when input.