JPH02246264A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To make it possible to arrange MOS transistors in the close proximity and to improve the integration density of a device by forming the base electrode of a bipolar transistor in the same step at either of the step for foming P-type or N-type polycrystalline silicon layer. CONSTITUTION:The following steps are provided: the step for forming the gate electrode of one MOS transistor Q1 with a P-type polycrystalline silicon layer 9; the step for covering the side surface of the P-type polycrystalline silicon layer 8 with an insulating film 12; and the step for forming the gate electrode of another MOS transistor Q2 with an N-type polycrystalline silicon layer 10. A base electrode B of a bipolar transistor is formed in the same step as the step for forming either of the P-type polycrystalline silicon layer 9 or the N-type polycrystalline silicon layer. Thus, the high integration density of the device can be achieved without increasing the manufacturing steps.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a bipolar transistor and a MOS transistor are assembled on the same substrate, and a method for manufacturing the same.

[Conventional technology]

Conventionally, this type of semiconductor device has been developed in the direction of higher speed and higher integration of the device as a whole.

That is, as the performance of MOS transistors has been improved through finer processing, bipolar transistors have also been arranged in parallel to achieve higher precision.

For example, when forming a lMo5 transistor, its gate electrode is formed and is used as part of a mask for forming a drain layer and a source layer, considering that this gate electrode will not be removed in subsequent steps. So-called self-alignment
) method is used. By using the same structure, the problem of mask displacement does not occur, so that the distance between the drain layer and the source layer can be significantly reduced.

On the other hand, even in bipolar transistors, the above-mentioned self-alignment method has come to be used.

That is, a base electrode made of a polycrystalline silicon layer containing impurities (for example, p-type) is formed surrounding the emitter formation region, and the impurities are diffused from the semiconductor surface exposed at the center of the base electrode, and at the same time heat treatment is performed. In addition, impurities contained in the base electrode are also diffused to form a base layer. Then, an emitter electrode made of a polycrystalline silicon layer containing impurities (for example, n-type) is connected to the semiconductor surface exposed from the base electrode, and heat treatment is applied to remove impurities contained in the emitter electrode. An emitter layer is formed in the base layer by diffusion (1988. International
Electron Device Meeting
achnical digest P748-P751
reference).

In recent years, when forming a MOS transistor together with the above-mentioned bipolar transistor, it has been manufactured using a self-alignment method, and its gate electrode has been made to contain an impurity (an impurity of a conductivity type different from that of the semiconductor layer in which the channel layer is formed). Polycrystalline silicon layers have come to be used. This is because if a polycrystalline silicon layer is used as a gate electrode, it can prevent problems such as forming an oxide film on the sidewalls of the gate electrode, which makes it easy to insulate, and preventing metal particles from diffusing toward the semiconductor substrate. This is because it has advantages such as high reliability.

[Problem to be solved by the invention]

However, in a semiconductor device constructed in this way, each M
When the OS transistor is of the same channel type, for example, an n-channel type, the impurities contained in the polycrystalline silicon that constitutes its gate electrode are all of the same n-type, and when the bipolar transistor is of the npn type, the impurities contained in the polycrystalline silicon that constitutes its base electrode are all of the same type. This was different from the p-type impurity contained in crystalline silicon.

This has the advantage that the n-type polycrystalline silicon layer, which is the gate electrode of each MOS transistor, can be formed in the same process, but each n-type polycrystalline silicon layer must be separated by a certain distance or more to ensure electrical insulation. As a matter of fact, there was a restriction on the minimum distance between these.

Therefore, the present invention has been made in view of the above circumstances, and provides a semiconductor device and a method for manufacturing the same that can achieve a high degree of integration without increasing the number of manufacturing steps.

[Means to solve the problem]

In order to achieve such an object, the present invention provides at least two MOS transistors of the same channel type each having a gate electrode made of a polycrystalline silicon layer containing an impurity, and a base electrode made of a polycrystalline silicon layer containing an impurity. In a semiconductor device including a bipolar transistor made of a crystalline silicon layer, a step of forming a gate electrode of one MOS transistor from a first conductivity type polycrystalline silicon layer, and a step of forming a side surface of the first conductivity type polycrystalline silicon layer. and forming a gate electrode of the other MOS transistor with a polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer, The electrode is formed simultaneously with either the step of forming the first conductivity type polycrystalline silicon layer or the step of forming polycrystalline silicon of a conductivity type different from the first conductivity type polycrystalline silicon layer. It is characterized by the fact that it is made to do so.

In the above structure, when forming a polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer, there is no description of the step of covering the side surfaces of this polycrystalline silicon layer with an insulating film. , the insulating film may be constructed in the same manner as the first conductivity type polycrystalline silicon layer.

Further, the emitter electrode of the bipolar transistor described above is also made of a polycrystalline silicon layer containing impurities, and this polycrystalline silicon layer is connected to the step of forming the first conductivity type polycrystalline silicon layer and the step of forming the first conductivity type polycrystalline silicon layer. Among the steps of forming polycrystalline silicon of a conductivity type different from that of the conductivity type polycrystalline silicon layer, the formation is performed simultaneously with the steps other than the step of forming the base electrode of the bipolar transistor.

In addition, in each of the above manufacturing methods, for a MOS transistor in which a polycrystalline silicon layer containing an impurity different from the channel type is formed, the channel region between the drain layer and the source layer is This method is characterized by adding a step of forming a semiconductor layer of the same type to connect the drain layer and the source layer.

Furthermore, although the above-mentioned semiconductor devices incorporate MOS transistors of the same channel type,
The MOS transistors do not necessarily have to be the same, but may include two or more MOS transistors of different channel types.

Furthermore, although the above configuration has been described for a semiconductor device in which bipolar transistors are incorporated on the same substrate, it can also be applied to a semiconductor device in which only a plurality of MOS transistors are incorporated. That is, in a semiconductor device including at least two or more MOS transistors of the same channel type whose gate electrodes are made of a polycrystalline silicon layer containing impurities, the gate electrode of one MOS transistor is made of a polycrystalline silicon layer of a first conductivity type. a step of forming the gate electrode of the other MOS transistor with a conductivity type different from that of the first conductivity type polycrystalline silicon layer; This process consists of a step of forming a polycrystalline silicon layer.

[Effect]

As mentioned above, two or more MOSs having the same channel type and each having a gate electrode made of a polycrystalline silicon layer containing impurities
In a semiconductor device including a transistor and a bipolar transistor whose base electrode is formed of a polycrystalline silicon layer containing impurities, the impurities in the polycrystalline silicon layers constituting each gate electrode are made to be different, and at least one of the polycrystalline silicon layers is By forming each polycrystalline silicon layer in a separate process with the side surfaces of the silicon layer insulated, the polycrystalline silicon layers can be placed close to each other. Since the side surfaces of one polycrystalline silicon layer are insulated, in an extreme case, they may come into contact with each other. Thereby, each MOS transistor can be arranged close to each other, and the degree of integration can be improved.

In this case, the number of steps increases by forming each of the polycrystalline silicon layers in separate steps, but since the base electrode of the bipolar transistor is a polycrystalline silicon layer containing the same impurity in one step, By forming it simultaneously with the polycrystalline silicon layer, the number of steps in manufacturing the entire device does not increase.

In this case, by insulating the side surface of the base electrode of the other MOS transistor, the wiring layer extending from this gate electrode and another wiring layer made of polycrystalline silicon can be placed close to each other. You will also be able to do things.

When the emitter electrode of the bipolar transistor is formed of a polycrystalline silicon layer containing impurities, this polycrystalline silicon layer is formed in the same process as one gate electrode of each of the MOS transistors. This makes it possible to further reduce the number of steps.

In the case of MOS transistors of the same channel type, if the impurities contained in the polycrystalline silicon constituting the gate electrode are different, the threshold value (v
th) When there is a difference in voltage but it is desired that the voltages be the same, the channel region between the drain layer and source layer of a MOS transistor in which a polycrystalline silicon layer containing impurities different from the channel type is formed. This can be achieved by forming a semiconductor layer of the same type that connects the drain layer and the source layer.

Furthermore, the above-mentioned semiconductor device incorporates MOS transistors of the same channel type, and although it is rare, MOS transistors of different channel types are not necessarily the same.
Especially by applying it to a device in which two or more S transistors are incorporated.

Wiring layers extending from each gate electrode can also be arranged close to each other.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor device and a method for manufacturing the same according to the present invention will be described below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention.

In the same figure, an area where an npn type bipolar transistor is formed on the same semiconductor substrate surface and an area where an n-channel type MO8 (Metal Oxide) consisting of a memory cell are shown.
There is a region where a transistor (de Sem1conductor) is formed.

The region where the bipolar transistor is formed is
A p-type semiconductor layer 3 and an n-type semiconductor layer 2 are sequentially formed on a p-type semiconductor substrate 4. A base layer consisting of a p-type diffusion layer 6 and a V-type diffusion layer 7 is formed on the surface of this n-type semiconductor layer 2, and an emitter layer consisting of an n-type diffusion layer 5 is further formed on a part of the surface of this base layer. is formed. The base layer has a small layer thickness immediately below the emitter layer, and
It consists of an intrinsic base region with a low concentration and an external region with a large layer thickness and a high concentration around the intrinsic base region.

In this way, the surface of the base layer and the surface of the emitter layer formed on a part of the base layer are exposed,
On the surface of the n-type semiconductor layer 2.

So-called selective oxidation (Local Oxidation)
Field oxide film 1 is formed by
is formed.

Further, in a region of the field oxide film 1 adjacent to the base layer, there is a part where the field oxide film 1 is not formed, and a T-type diffusion layer 8 that reaches the A-type semiconductor layer 3 is formed in this part. has been done. This T-type diffusion layer 8 is
It is connected to the n-type semiconductor layer 2 configured as a collector layer and becomes a collector 31C layer.

A lead electrode is formed on the surface of the base layer 7, which is the base layer, and extends over the oxide film 1. This extraction electrode has a multilayer structure, in which a p-type polycrystalline silicon layer 9, a tungsten polycide layer 11, and an insulating film 12 are laminated in order from the me-type diffusion layer 7 surface.

Furthermore, a side spacer 13 made of an insulating material is formed on the side surface of the extraction electrode on the side of the mold diffusion layer 7 in such a manner that the mold diffusion layer 5 is exposed. A polycrystalline silicon layer, for example, forming an emitter electrode is formed on the surface of the A-type diffusion layer 5 exposed from the side spacer 13. This polycrystalline silicon layer contains t-type impurities.

In the region where the MOS transistor is formed, a p-type semiconductor M19 is formed on the p-type semiconductor substrate 4. Two MOS transistors are formed on the surface of this p-type semiconductor layer 19. That is, p-type semiconductor layer 1
Male type diffusion layers 15, 16, and 17 are formed on the surface of the n+1 diffusion layers 15 and 16, and between the n+1 diffusion layers 15 and 16, and on the surface of the male type diffusion layer 1.
A gate oxide film 20 is formed on the surface of the p-type semiconductor layer 19 between layers 6 and 17. And each gate oxide film 2
Gate electrodes each having a multilayer structure are formed on the surfaces of the gate electrodes 0, and on the gate oxide film 2o between the A-type diffusions N15 and 16, a p-type polycrystalline silicon layer 9 is sequentially formed from the gate oxide film 20 side. , a tungsten polycide layer 11 and an insulating film 12 are laminated to provide a low resistance meter. °Also.

On the gate oxide film 20 between the A-type semiconductor layers 16 and 17 on the other side, an n-type polycrystalline 2922 layer 10. A tungsten polycide layer 11 and an insulating film 12 are laminated. The side wall surfaces of each of these gate electrodes are covered with side spacers 13 made of an insulating material.
is formed.

Note that the two MOS transistors configured in this manner have a common male-type diffusion layer, and are configured to improve the degree of integration. Further, in a so-called channel formation region on the surface of the p-type semiconductor layer 19 under the gate oxide film 20 between the r1+ type diffusion layers 15 and 16, an n-type semiconductor layer 18 having a relatively small layer thickness is formed. The reason for this is that in the MOS transistor on which the n-type semiconductor layer 18 is formed, the conductor layer of the gate electrode adjacent to the gate oxide film 2o is formed of the p-type polycrystalline silicon layer 9. In order to compensate for the fact that the conductor layer of the corresponding portion of the MOS transistor on the other side is formed of two n-type polycrystalline silicon layers 10, the respective threshold voltages (Vth) are different. It is something.

A field oxide film 1 is formed on the surface of the p-type semiconductor layer 19 outside the formation region of the MOS transistor constructed in this manner by a one-selective oxidation method. This oxide film 1 is normally formed at the same time as the oxide film 1 on the region where the bipolar transistor is formed.

The two MOS transistors in FIG. 1 can be used, for example, as shown in FIG.
This corresponds to the transfer MOS transistor Q and the driver MOS transistor Q2 of the memory cells of ando+*Access Memory). Both the transfer MOS transistor Q and the driver MOS transistor Q2 are N-channel type MOS transistors, and the transfer MOS transistor Q2 is an N-channel type MOS transistor.
Since the sources of the transistors and the drains of the driver MOS transistors are commonly connected at the storage node N2, in FIG. The male-type diffusion layer 16 is supplied with a power supply voltage (Vcc) via a resistor R based on the circuit shown in FIG. Also, transfer MOS transistor Q
A signal from the data line is input to the T-type diffusion layer 15, which is the drain of the driver MOS
The n-type diffusion layer 17, which is the source of the transistor, is connected to ground.

Note that the bipolar transistor shown in FIG. 1 is shown as a transistor that is indirectly electrically connected to the memory cell of the static RAM but constitutes a separate circuit.

Next, an embodiment of the method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 3(a) to 3(j).

Here, the surface processing of the semiconductor substrate prepared before entering the step of FIG. 3(a) will be briefly described.

First, on the surface of a p-type semiconductor substrate, a type diffusion layer is selectively formed in a region where a bipolar transistor is to be formed.
An intrinsic semiconductor layer containing no impurities is formed on the surface of the male-type diffusion layer and on the surface of the p-type semiconductor substrate in other regions by, for example, an epitaxial growth method. Thereafter, a semiconductor formed by this epitaxial growth method is formed. From the surface of the layer, the region where the bipolar transistor is to be formed is selectively doped with an n-type impurity, and the other regions are selectively doped with a p-type impurity. and to reach the p-type semiconductor substrate.

As shown in FIG. 3(a), the semiconductor substrate thus formed has a T-type semiconductor layer 3 and an N-type semiconductor layer 2 sequentially formed on a P-type semiconductor substrate 4 in the bipolar transistor formation region. will be formed. In addition, in other regions, that is, in the MOS transistor formation region, p
A p-type semiconductor layer 19 of the same conductivity type is formed on the p-type semiconductor substrate 4.

Then, on the surfaces of the n-type semiconductor layer 2 and the p-type semiconductor layer 19 formed in this way, regions other than the bipolar transistor arrangement region and the MOS transistor arrangement region are respectively oxidized to a relatively thick film by a well-known selective oxidation method. A large field oxide film 1 is formed, and the n-type semiconductor layer 2 and p-type semiconductor layer 2 exposed from this field oxide film 1 are
A relatively thin oxide film 37 is formed on the surface of the type semiconductor layer 19.

This oxide film 37 is a gate oxide film of a MOS transistor. Next, an n-type impurity is doped into the MOS transistor formation region of one of the two MOS transistors through the gate oxide film 37. A semiconductor layer 18 is formed. This n-type semiconductor layer 18 becomes a conductive layer formed in the channel layer formation region of the one MOS transistor (FIG. 3(a)).

Next, an n-type polycrystalline 2022 layer 10. A tungsten polycide layer 11 having low resistance and an insulating film 12 are successively formed (FIG. 3(b)).

By a well-known photoetching technique, the n-type polycrystalline silicon layer 10 and tungsten polycrystalline silicon layer 10 formed on the gate oxide film 37 of the MOS transistor on the side where the n-type semiconductor layer 18 is not formed of the two MOS transistors are removed. Only the side layer 11 and the insulating film 12 are left and the others are removed.

In this way, the remaining n-type polycrystalline 2022 layer 10
．． A gate electrode is formed by the tungsten polycide layer 11 and the insulating film 12.

Next, an n-type semiconductor layer 16.1 that becomes a drain layer and a source layer by selectively doping with n-type impurities
form 7. In this case, the gate electrode is
It serves as a mask during draping of mold impurities,
This eliminates the misalignment that occurs when other masks are used, so it is possible to form n-type semiconductor layers 16 and 17 with an improved degree of integration (Figure 3 (C)).
.

Then, an insulating film 39 is formed on the end side surface of the gate electrode. This insulating film 39 is CVD (ChemicalV
It is formed by depositing an oxide film over the entire surface by an apor deposition method and then etching back by anisotropic dry etching. At this time, the oxide film 37 is also removed. As a result, the semiconductor surface is exposed, and only the oxide film 37 functioning as a gate oxide film remains (FIG. 3(d)).

Next, a relatively thin oxide film 40 is formed on the exposed semiconductor surface by heat treatment or the like, and then only the oxide film 40 in the base layer formation region in the bipolar formation region is selectively etched, for example, by wet etching. This oxide film 40 is formed on the MO on the side where the n-type semiconductor layer 18 is formed.
This is the gate oxide film of the S transistor (third
Figure (e)).

In this way, the p-type polycrystalline silicon layer 9, the tungsten polycide layer 11, and the insulating film 12 are sequentially formed over the entire surface area where a part of the n-type semiconductor layer 2 is exposed (see FIG. 3).
f)).

Of the two MOS transistors, a portion corresponding to the formation region of the gate electrode of the MOS transistor on which the n-type semiconductor layer 18 is formed and the base electrode of the bipolar transistor is left, and the other region is p in
type polycrystalline silicon layer 9, tungsten polycide layer 11
First, the insulating film 12 is removed. Using the gate electrode as a part of a mask, a t-type impurity is selectively doped to form a t-type semiconductor layer 15, which is a drain layer. Furthermore, a male type impurity is selectively doped in the region where the collector of the bipolar transistor is taken out to transform the male type diffusion layer 8 into the t type semiconductor layer 3.
(Fig. 3 (g)).

Next, an insulating film 39 is formed on the side end surface of each electrode formed in the previous step.
form. This insulating film 39 is formed by depositing an oxide film over the entire surface using the CVD method, and then etching back using anisotropic dry etching. At this time, the oxide film 4
Also removes 0. As a result, only the oxide film 40 functioning as a gate oxide group remains among the oxide films 40 (FIG. 3(h)).

Next, an oxide film 42 is formed on the exposed semiconductor surface, and by removing the oxide film 42 surrounded by the base electrode formed in the bipolar base layer formation region, the two surfaces of the n-type semiconductor layer are removed. to expose. Then, the exposed surface of the n-type semiconductor layer 2 is doped with p-type impurities to form a p-type semiconductor layer 6. At this time, the p-type impurity doping is performed using the base electrode as a mask, and this eliminates mask displacement that occurs when other masks are used. (Fig. 3(i)).

Furthermore, by performing heat treatment, the p-type impurity in the p-type polycrystalline silicon layer 9 constituting the base electrode is diffused into the n-type semiconductor layer 2, thereby forming a p+ type hot conductor layer 7. As a result, the p-type semiconductor layer 6 formed in the previous step is formed as an intrinsic base region, and the final semiconductor layer 7 is formed as an extrinsic base region.

Thereafter, an n-type polycrystalline silicon 2932 layer 14 is formed on the exposed surface of the p-type semiconductor layer 6 by photoetching, and this is used as an emitter electrode, and the n-type polycrystalline silicon 2932 layer 14 is heated by heat treatment. An n-type impurity is diffused into the p-type semiconductor layer 6 to form a t-type semiconductor layer 5 as an emitter layer (FIG. 3(j)).

Thereafter, electrodes are taken out of aluminum or the like from the source layer and drain layer of each MOS transistor and the collector layer of the bipolar transistor, and a wiring layer is formed to complete the process.

Next, FIG. 4 shows an example of wiring on the surface of a semiconductor device having the basic configuration shown in FIG. 1.

A sectional view taken along line A--A in FIG. 4 is shown in FIG. 5. FIG. 5 particularly shows a cross section of a portion of the MOS transistors shown in FIG. 2 where transfer MOS transistor Q1 and driver MOS transistor Q2 are formed. What is different from FIG. 1 is driver MOS transistor Q3. This is a cross-sectional view taken along the channel length direction. More specifically than in FIG. 1, a three-layer wiring layer is formed with inter-glabella insulating films 23A and 23B interposed therebetween. That is, M.O.
There is an insulating film 23A between the eyebrows that covers the electrode of the S transistor.
The driver MO is inserted through the hole formed in this glabella insulating film 23.
An n-type polycrystalline 2932 layer 14 connected to the gate electrode of the S transistor Q2 (this n-type polycrystalline 2932 layer 14 is an emitter electrode of a bipolar transistor, for example)
An i-type polycrystalline silicon layer 22 consisting of a high-resistance wiring layer (formed simultaneously with the polycrystalline silicon layer 14) and a high-resistance wiring layer connected to the polycrystalline silicon layer 14 is formed extending over the interlayer insulating film 23A. Furthermore, a glabellar insulating film 23B is formed, and a metal wiring N24 connected to the annular semiconductor layer 15, which is the drain of the transfer MOS transistor Q3, is formed by drilling a hole on the glabellar insulating film 23B.

In such a configuration, a wiring layer made of a material corresponding to that shown in FIG. 5 is shown in FIG. Among these, especially between the p-type polycrystalline silicon layer 9 that constitutes each gate electrode of transfer MOS transistors Q, , Q, and the n-type polycrystalline 2912 layer 10 that constitutes the gate electrode of driver MOS transistor Q. distance Q^, and said p
type polycrystalline silicon layer 9 and an n-type polycrystalline 2912 layer 10 constituting the gate electrode of the driver MOS transistor Q4.
The distance between QB and QB can be made much shorter than before.

FIG. 7 is a plan view showing an embodiment in which the MOS transistors shown in FIG. 2 are arranged differently and wired. As is clear from the figure.

Transfer MOS transistors Q, , Q, and driver MOS transistors Q, , Q, are arranged diagonally. In this case as well, the gate electrodes of the transfer MOS transistors Q, Q3 are p-type polycrystalline silicon layers 9, and the gate electrodes of the driver MOS transistors Q, Q, are n-type polycrystalline silicon layers 2912.
It is composed of 10 layers.

Each of the n-type polycrystalline silicon layers 10 is arranged between the p-type polycrystalline silicon reservoirs 9, and the distance between them can be made much smaller than in the conventional case.

Next, FIG. 6 is a block diagram showing another embodiment of the semiconductor device according to the present invention. The same materials and functions as in Figure 1 are the same.
It is shown in the appendix. The difference in configuration from FIG. 1 lies in the region formed in the MOS transistor, and the driver MOS transistor Q2 is configured as a so-called vertical MOS transistor. Therefore, the region where the MOS transistor is formed is formed by forming the I-type semiconductor layer 4 on the I-type semiconductor layer, the p-type semiconductor layer 4 and the p-type semiconductor layer.
A groove is formed to divide the A-type semiconductor layer 16 formed on the surface of the p-type semiconductor layer 19, and a gate oxide film 20 is formed on the bottom and inside of this groove. In addition, a gate electrode made of an n-type polycrystalline silicon layer 1o is filled. The trench is formed until it reaches the beam-type semiconductor layer 4, the A-type semiconductor layer 4 is used as a drain layer, the A-type semiconductor layer 4 is used as a source layer, and a channel layer is formed along the gate oxide film 20. It looks like this.

In this way, the vertical MOS transistor is converted into a driver MOS.
Transistor Q2. By using Q and arranging in the same manner as shown in FIG. 7, the wiring layer arrangement as shown in FIG. 8 is achieved. The dimensions of the MOS transistor in Fig. 8 are the same as those in Fig. 7, and this, together with the nature of vertical MOS transistors with a high degree of integration, makes it possible to significantly improve the degree of integration. It becomes like this.

〔Effect of the invention〕

As described above, according to the present invention, there are two or more MOS transistors of the same channel type whose gate electrodes are made of a polycrystalline silicon layer containing impurities.

In a semiconductor device including a bipolar transistor in which a base electrode is formed of a polycrystalline silicon layer containing impurities, impurities in the polycrystalline silicon layers constituting each gate electrode are made to be different, and at least one of the polycrystalline silicon layers is If each polycrystalline silicon layer is formed in a separate process with the side surfaces insulated, each polycrystalline silicon layer can be placed close to each other. Since the side surfaces of one polycrystalline silicon layer are insulated, in an extreme case, they may come into contact with each other. This allows each MOS
Transistors can be placed close to each other and the degree of integration can be improved.

In this case, the number of steps increases by forming each of the polycrystalline silicon layers in separate steps, but since the base electrode of the bipolar transistor is a polycrystalline silicon layer containing the same impurity in one step, By forming it simultaneously with the polycrystalline silicon layer, the number of steps in manufacturing the entire device does not increase.

In this case, by insulating the side surface of the base electrode of the other MOS transistor, the wiring layer extending from this gate electrode and another wiring layer made of polycrystalline silicon can be placed close to each other. You will also be able to do things.

When the emitter electrode of the bipolar transistor is formed of a polycrystalline silicon layer containing impurities, this polycrystalline silicon layer is formed in the same process as one gate electrode of each of the MOS transistors. This makes it possible to further reduce the number of steps.

In the case of MOS transistors of the same channel type, if the impurities contained in the polycrystalline silicon constituting the gate electrode are different, the threshold value (V
tb) If there is a difference in voltage but you want them to be the same, use the channel region between the drain layer and source layer of a MOS transistor that forms a polycrystalline silicon layer containing impurities different from the channel type. This can be achieved by forming a semiconductor layer of the same type that connects the drain layer and the source layer.

Furthermore, although the above-mentioned semiconductor devices incorporate MOS transistors of the same channel type,
By applying the present invention to a device in which two or more MOS transistors of different channel types are incorporated, even though they are not necessarily the same, it becomes possible to arrange them close to each other even in wiring layers extending from respective gate electrodes.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional configuration diagram showing one embodiment of a semiconductor device according to the present invention, and FIG. 2 is a MOS incorporated in the semiconductor device.
3(a) to 3(j) are process diagrams showing an embodiment of the method for manufacturing a semiconductor device according to the present invention, and FIG. 4 is a diagram showing a wiring layout of a semiconductor device according to the present invention. FIG. 5 is a plan view showing one embodiment, and FIG. 5 is a block diagram showing a cross section taken along line A-A in FIG. 4. FIG. 7 is a plan view showing one example of the wiring layout of the semiconductor device having the configuration shown in FIG. 6, and FIG. 8 is a plan view showing another example of the wiring layout of the semiconductor device having the configuration shown in FIG. 6. It is a diagram. DESCRIPTION OF SYMBOLS 1... Field oxide film, 2... N-type semiconductor layer, 3
...♂-type semiconductor layer, 4...p-type semiconductor substrate. 5... type diffusion layer, 6... p type diffusion layer, 7... type diffusion layer, 8... diffusion layer, 9... p type polycrystalline silicon layer, 10... n-type polycrystalline silicon layer, 11...
Tungsten polycide layer, 12... Insulating layer, 13.
...Side spacer, 14... is made of mold polycrystalline silicon,
15... A-type semiconductor layer, 16... A-type semiconductor layer, 1
7... is a type semiconductor layer, 18... is an n-type semiconductor layer, 20
...Gate oxide film, E...Emitter, B...Base, C...Collector, D...Data line, Vcc...
- Power supply voltage, R1...high resistance, Q...transfer MOS transistor, Q2...driver MOS transistor.

Claims (1)

[Claims] 1. At least two or more M having the same channel type and whose gate electrodes are made of a polycrystalline silicon layer containing impurities.
In a semiconductor device including an OS transistor and a bipolar transistor whose base electrode is made of a polycrystalline silicon layer containing impurities, a step of forming a gate electrode of one MOS transistor from a first conductivity type polycrystalline silicon layer; , a step of covering the side surface of the first conductivity type polycrystalline silicon layer with an insulating film, and forming a gate electrode of the other MOS transistor with a polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer. The base electrode of the bipolar transistor is made of polycrystalline silicon of a conductivity type different from the step of forming the first conductivity type polycrystalline silicon layer and the first conductivity type polycrystalline silicon layer. A method for manufacturing a semiconductor device, characterized in that the semiconductor device is formed at the same time as one of the steps of forming the semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising the step of coating a side surface of the polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer with an insulating film. 3. In the first aspect of the present invention, the emitter electrode of the bipolar transistor is also constituted by a polycrystalline silicon layer containing impurities, and this polycrystalline silicon layer is used as the first conductivity type polycrystalline silicon layer. The process and the process of forming polycrystalline silicon of a conductivity type different from the first conductivity type polycrystalline silicon layer are performed at the same time as the process other than the process in which the base electrode of the bipolar transistor is formed simultaneously. A method for manufacturing a featured semiconductor device. 4. In any one of claims 1 to 3, in each MOS transistor, in a MOS transistor in which a polycrystalline silicon layer containing an impurity different from that of a channel type is formed, its drain layer and source layer are A method of manufacturing a semiconductor device, comprising the step of forming a semiconductor layer of the same type connecting the drain layer and the source layer in a channel region between the drain layer and the source layer. 5. A semiconductor comprising two or more MOS transistors with different channel types, each of which has a gate electrode made of a polycrystalline silicon layer containing an impurity, and a bipolar transistor whose base electrode is made of a polycrystalline silicon layer containing an impurity. In the device, a step of forming the gate electrode of one MOS transistor with a first conductivity type polycrystalline silicon layer, a step of covering the side surface of the first conductivity type polycrystalline silicon layer with an insulating film, and a step of forming the gate electrode of the other MOS transistor with an insulating film are performed. forming a gate electrode with a polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer, and the base electrode of the bipolar transistor is formed of a polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer. Manufacturing a semiconductor device, characterized in that the step of forming polycrystalline silicon and the step of forming polycrystalline silicon of a conductivity type different from the first conductivity type polycrystalline silicon layer are performed simultaneously. Method. 6. At least two or more M having the same channel type and whose gate electrodes are made of a polycrystalline silicon layer containing impurities.
In a semiconductor device including an OS transistor, a step of forming a gate electrode of one MOS transistor with a first conductivity type polycrystalline silicon layer, and a step of covering a side surface of the first conductivity type polycrystalline silicon layer with an insulating film. and the other M
A method for manufacturing a semiconductor device, comprising the step of forming a gate electrode of an OS transistor using a polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer. 7. At least two or more M having the same channel type and whose gate electrodes are made of a polycrystalline silicon layer containing impurities.
In a semiconductor device including an OS transistor and a bipolar transistor whose base electrode is formed of a polycrystalline silicon layer containing impurities, one transistor is formed of a polycrystalline silicon layer of a first conductivity type, and whose side surfaces are insulated. the other transistor has a gate electrode formed of a polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer; 1. A semiconductor device comprising a base electrode formed of a polycrystalline silicon layer. 8. The semiconductor device according to claim 7, wherein a side surface of the polycrystalline silicon layer of a conductivity type different from the first conductivity type polycrystalline silicon layer is covered with an insulating film. 9. The semiconductor device according to claim 7, wherein the bipolar transistor has an emitter electrode formed of a polycrystalline silicon layer. 10. In claim 9, in each MOS transistor in which a polycrystalline silicon layer containing an impurity different from the channel type is formed, the channel region between the drain layer and the source layer is A semiconductor device characterized in that a semiconductor layer of the same type is formed to connect the drain layer and the source layer.