JPH02246359A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02246359A
JPH02246359A JP1068363A JP6836389A JPH02246359A JP H02246359 A JPH02246359 A JP H02246359A JP 1068363 A JP1068363 A JP 1068363A JP 6836389 A JP6836389 A JP 6836389A JP H02246359 A JPH02246359 A JP H02246359A
Authority
JP
Japan
Prior art keywords
stage
resin
sheathing
semiconductor device
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1068363A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Aoki
強 青木
Eiji Yokota
横田 栄二
Kazumi Ebihara
蛯原 一美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Original Assignee
Kyushu Fujitsu Electronics Ltd
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kyushu Fujitsu Electronics Ltd, Fujitsu Ltd filed Critical Kyushu Fujitsu Electronics Ltd
Priority to JP1068363A priority Critical patent/JPH02246359A/en
Publication of JPH02246359A publication Critical patent/JPH02246359A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/30Die-attach connectors
    • H10W72/321Structures or relative sizes of die-attach connectors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/536Shapes of wire connectors the connected ends being ball-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/50Bond wires
    • H10W72/531Shapes of wire connectors
    • H10W72/5363Shapes of wire connectors the connected ends being wedge-shaped
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00Interconnections or connectors in packages
    • H10W72/851Dispositions of multiple connectors or interconnections
    • H10W72/874On different surfaces
    • H10W72/884Die-attach connectors and bond wires
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent the deterioration of the performance and shortening of the lifetime of a semiconductor chip due to heating at the time of mounting by increasing the bonding power of a stage, on which the semiconductor chip is loaded, and a resin sheathing sealing the chip and stage. CONSTITUTION:Through-holes 13 are filled with one parts of a resin sheathing 4 and one parts of the resin sheathing are formed, and the expansion of the resin sheathing 4 peeling the resin sheathing 4 and a stage 12 is inhibited by engaging force with a resin filled into the through-hole 13 and the through-hole 13. That is, the stage 12 and the resin sheathing 4 are bonded by the adhesion of a surface and a surface and engaging force stronger than the adhesion of the engaging of one parts of the sheathing resin 4 with the through-holes 13. Consequently, even when moisture intruding into the resin sheathing 4 intends to expand, the deformation of sheathing is inhibited by bonding power utilizing engaging force. Accordingly, no crack is generated, the reliability of a device is improved and the service life thereof can be lengthened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は樹脂封止された半導体装置、特に実装時の加熱
によって封止樹脂に生じるクランクをなくすための新規
構成に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a novel configuration for eliminating cranks that occur in the sealing resin due to heating during mounting.

3、発明の詳細な説明 〔従来の技術〕 第7図は樹脂封止された従来の半導体装置を示す模式断
面図、第8図は該半導体装置における樹脂外装の熱膨張
を示す模式断面図である。
3. Detailed Description of the Invention [Prior Art] FIG. 7 is a schematic sectional view showing a conventional semiconductor device sealed with resin, and FIG. 8 is a schematic sectional view showing thermal expansion of the resin exterior of the semiconductor device. be.

第7図において、半導体装置1は金属ステージ3に半導
体チップ2を搭載し、半導体チップ2のパッド(図示せ
ず)とリード端子5とを金属細線10で接続し、半導体
チップ2.金属ステージ3゜金属細線10等を封止する
樹脂外装4の側端面より、複数本のリード端子5のリー
ド部が導出されてなる。
In FIG. 7, a semiconductor device 1 has a semiconductor chip 2 mounted on a metal stage 3, and pads (not shown) of the semiconductor chip 2 and lead terminals 5 are connected with thin metal wires 10. The lead portions of a plurality of lead terminals 5 are led out from the side end surface of the resin sheath 4 that seals the thin metal wire 10, etc. of the metal stage 3.

かかる半導体装置lは、リード端子5を外部回路にはん
だ付けし実装されるが、該実装のため例えば230℃程
度にリード端子5を加熱すると、樹脂外装4も熱せられ
ることになる。すると、リード端子5の導出部に沿って
および樹脂外装4を透過し樹脂外装4内に侵入した水分
が膨張して第8図に示す如く、樹脂外装4の下部はステ
ージ3から剥がれて膨らみ、ステージ3の端部からクラ
ック6の発生することがあった。
Such a semiconductor device 1 is mounted by soldering the lead terminals 5 to an external circuit, and when the lead terminals 5 are heated to, for example, about 230° C. for this mounting, the resin sheath 4 is also heated. Then, the moisture that has entered the resin sheath 4 along the lead-out portion of the lead terminal 5 and through the resin sheath 4 expands, and as shown in FIG. 8, the lower part of the resin sheath 4 peels off from the stage 3 and swells. Cracks 6 were sometimes generated from the ends of the stage 3.

このようなりラック6は、外装4の気密性を損なって半
導体装置1の借問性を低下せしめ、寿命を短縮すること
になる。
In this way, the rack 6 impairs the airtightness of the exterior casing 4, reduces the reliability of the semiconductor device 1, and shortens its life.

第9図は他の従来例によるステージの断面図(イ)とそ
の平面図(ロ)であり、ステージ7は下面に複数の凹部
(デインプル)8を形成し、樹脂外装との密着面積を拡
大させたものである。
FIG. 9 is a cross-sectional view (A) and a plan view (B) of a stage according to another conventional example, in which the stage 7 has a plurality of recesses (dimples) 8 formed on the lower surface to enlarge the area of contact with the resin exterior. This is what I did.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

凹部8によって樹脂外装4との密着面積を増やし、その
ことによってステージ7と樹脂外装4との密着力を高め
た半導体装置は、クラック6の発生を多少なりとも抑制
する効果を有するが不完全であり、別の対策が強く望ま
れていた。
A semiconductor device in which the area of contact with the resin sheath 4 is increased by the recess 8, thereby increasing the adhesion between the stage 7 and the resin sheath 4, has the effect of suppressing the occurrence of cracks 6 to some extent, but it is incomplete. However, other countermeasures were strongly desired.

本発明の目的は、前記クラックが発生しないように構成
し、半導体装置の信転性を高め長寿命にすることである
An object of the present invention is to improve the reliability of a semiconductor device and extend its life by configuring a semiconductor device so that the cracks do not occur.

〔課題を解決するための手段〕[Means to solve the problem]

本発明による半導体装置はその実施例を示す第1図およ
び第6図によれば、半導体チップ搭載用の金属板ステー
ジ12が下面より上面で大きく開口する複数個の貫通孔
13を具え、ステージ12およびその上面に搭載した半
導体チップ2を樹脂外装4にて封止してなる、 または、半導体チップ搭載用の金属板ステージ】6にス
テージ16の下面の開口より上面の開口がステージ16
の側方にずれた複数個の貫通孔17を具え、ステージ1
6およびその上面に搭載した半導体チップを樹脂封止し
てなる。
According to FIG. 1 and FIG. 6 showing an embodiment of the semiconductor device according to the present invention, a metal plate stage 12 for mounting a semiconductor chip is provided with a plurality of through holes 13 that are opened larger on the upper surface than on the lower surface. and a semiconductor chip 2 mounted on the upper surface thereof is sealed with a resin sheath 4, or a metal plate stage for mounting a semiconductor chip] 6 has an opening on the upper surface than the opening on the lower surface of the stage 16.
Stage 1
6 and a semiconductor chip mounted on its upper surface are sealed with resin.

〔作用〕[Effect]

上記手段によれば、樹脂外装の一部が貫通孔に充填し形
成され、樹脂外装とステージとを剥がすような樹脂外装
の膨張は、貫通孔と該貫通孔に充填された樹脂の係合力
によって抑止されるようになる。即ち、従来技術では面
と面との密着力により樹脂外装の膨張変形を抑制する構
成であったが、本発明によるステージと樹脂外装とは面
と面との密着力および、貫通孔に外装樹脂の一部が係合
し該密着力より強固である係合力によって結合するよう
になる。
According to the above means, a part of the resin exterior is formed by filling the through hole, and the expansion of the resin exterior that causes the resin exterior and the stage to be peeled off is caused by the engagement force between the through hole and the resin filled in the through hole. becomes inhibited. That is, in the prior art, the expansion and deformation of the resin exterior was suppressed by the adhesive force between surfaces, but the stage and resin exterior according to the present invention have a structure that suppresses the expansion and deformation of the resin exterior by the adhesive force between the surfaces and the through hole. A part of the two is engaged, and the two are bonded by an engagement force that is stronger than the adhesion force.

そのため、樹脂外装内に侵入した水分が膨張しようとし
ても、前記係合力を利用した結合力によって外装の変形
が抑止されるようになり、樹脂外装にはクラックが発生
しないようになる。
Therefore, even if moisture that has entered the resin exterior tries to expand, the deformation of the exterior is suppressed by the bonding force using the engagement force, and cracks do not occur in the resin exterior.

〔実施例〕〔Example〕

以下に、図面を用いて本発明の実施例による半導体装置
を説明する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to an embodiment of the present invention will be described below with reference to the drawings.

第1図は本発明の一実施例による半導体装置を示す模式
断面図、第2図は第1図に示すステージの平面図である
FIG. 1 is a schematic sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a plan view of the stage shown in FIG. 1.

前出図と共通部分に同一符号を使用した第1図において
、半導体装置11はステージ12の上面に半導体チップ
2を搭載し、半導体チップ2のパッド(図示せず)とリ
ード端子5とを金属細線10で接続し、半導体チップ2
.ステージ12.金属細線10等を封止する樹脂外装4
の側端面より、複数本のリード端子5のりτド部が導出
されてなる。
In FIG. 1, in which the same reference numerals are used for parts common to those in the previous figure, a semiconductor device 11 has a semiconductor chip 2 mounted on the upper surface of a stage 12, and pads (not shown) of the semiconductor chip 2 and lead terminals 5 are connected with metal. Connected with thin wire 10, semiconductor chip 2
.. Stage 12. Resin exterior 4 for sealing thin metal wire 10 etc.
A plurality of lead terminals 5 are led out from the side end surface.

半導体チップ2は、その下面に被着された密着層9の熱
圧着等によってステージ12の上面に搭載されており、
樹脂外装4の一部分4aはステージ12にあけた貫通孔
13内に充填し形成される。
The semiconductor chip 2 is mounted on the upper surface of the stage 12 by thermocompression bonding or the like with an adhesive layer 9 adhered to the lower surface of the semiconductor chip 2.
A portion 4a of the resin sheath 4 is formed by filling a through hole 13 formed in the stage 12.

第1図および第2図において、鉄−ニッケル合金等にて
なるステージ12には、複数個(図は25個)の貫通孔
13が設けられており、封止用樹脂がステージ12の下
面より注入される各貫通孔13の断面形状は、下面より
上面で大きく開口するテーバ状または段付き状である。
In FIGS. 1 and 2, a stage 12 made of iron-nickel alloy or the like is provided with a plurality of through holes 13 (25 in the figure), and a sealing resin is applied from the bottom surface of the stage 12. The cross-sectional shape of each through hole 13 to be injected is tapered or stepped, with the upper surface opening larger than the lower surface.

第3図(イ) l (D)は本発明によってステージに
あけた貫通孔の実施例を示す拡大断面図である。
FIGS. 3(A) and 3(D) are enlarged sectional views showing an embodiment of a through hole formed in a stage according to the present invention.

第3図(イ)においてテーバ状の貫通孔13aは、図中
に一点鎖線で示す如きエツチングマスク14と15をス
テージ12に形成し、エツチングによって形成したもの
である。
In FIG. 3(a), the tapered through hole 13a is formed by etching by forming etching masks 14 and 15 on the stage 12 as shown by the dashed line in the figure.

第3図(U)において、小径部13cと大径部13dよ
りなる段付きの貫通孔13bは、打抜きプレス加工によ
って小径部13cと同径の孔をステージ12にあけたの
ち、押しプレス加工により大径部13dをステージ12
の上面に形成し、しかるのち平面押し加工によって大径
部13dの形成による盛り上がりを潰し、ステージ12
の上面を平らにしたものである。
In FIG. 3(U), the stepped through hole 13b consisting of the small diameter part 13c and the large diameter part 13d is formed by punching a hole with the same diameter as the small diameter part 13c in the stage 12 by punching, and then by pressing. The large diameter portion 13d is placed on the stage 12.
The stage 12 is formed on the upper surface, and then flattened by flat pressing to crush the bulge caused by the formation of the large diameter portion 13d.
The top surface is flat.

かかるステージ12に半導体チップ2を搭載したのち、
一部分4aが貫通孔13内に充填し形成される樹脂外装
4とステージ12との結合力は、ステージ12の下面と
該下面に密着する樹脂外装4の密着力と、貫通孔13内
に侵入し形成された樹脂外装4の一部分4aの係合力と
の合力であり、該密着力が12g /+u+”程度であ
るのに対し該係合力は、密着力よりはるかに強力である
ことが実験によって確認された。
After mounting the semiconductor chip 2 on the stage 12,
The bonding force between the stage 12 and the resin sheath 4 formed by filling the through hole 13 with the portion 4a is determined by the adhesion force between the lower surface of the stage 12 and the resin sheath 4 that is in close contact with the lower surface, and the adhesion force between the resin sheath 4 and the stage 12, which are formed by filling the through hole 13 with the portion 4a. This is the resultant force with the engagement force of the part 4a of the formed resin sheath 4, and while the adhesion force is about 12g/+u+'', it has been confirmed through experiments that the engagement force is much stronger than the adhesion force. It was done.

下記の表1は、本発明に係わるステージ12とその下面
に形成させた樹脂体との結合力および、表1 下面に凹部の設けられた従来のステージ7とその下面に
形成させた樹脂体との結合力(密着力)を、第4図に示
すような試料によって実測したー実測例である。
Table 1 below shows the bonding strength between the stage 12 according to the present invention and the resin body formed on its lower surface, and Table 1 shows the bonding force between the stage 12 according to the present invention and the resin body formed on its lower surface. The bonding force (adhesion force) was actually measured using a sample as shown in FIG. 4. This is an example of actual measurement.

第4図は表1の結合力測定に使用した試料の側面図であ
る。
FIG. 4 is a side view of the sample used for the bond strength measurement in Table 1.

第4図において、試料はステージ12または7の下面に
樹脂体21をモールド形成し、ステージ12または7の
上面および樹脂体21の下面には、引っ張り試験用のシ
ャンク20を接着してなる。ただし、本発明に係わるス
テージ12は、厚さ0.3amの51角の鉄−ニッケル
合金板に、エツチングにより下面開口径が0.35mm
、上面開口径が0.55mmである61個のテーバ状貫
通孔13をあけたものであり、従来のステージ7は5■
−角の鉄−ニッケル合金板に61個の凹部8を形成した
ものである。
In FIG. 4, the sample is made by molding a resin body 21 on the lower surface of the stage 12 or 7, and adhering a shank 20 for tensile testing to the upper surface of the stage 12 or 7 and the lower surface of the resin body 21. However, the stage 12 according to the present invention is made of a 51 square iron-nickel alloy plate with a thickness of 0.3 am, and a lower opening diameter of 0.35 mm by etching.
, 61 tapered through holes 13 with an opening diameter of 0.55 mm on the top surface are drilled, and the conventional stage 7 has a diameter of 5 mm.
- 61 recesses 8 are formed in a square iron-nickel alloy plate.

表1から明らかなように、本発明によるステージ12と
樹脂体21との結合力は、従来のステージ7と樹脂体2
1との結合力の約80倍の強さを発揮する。
As is clear from Table 1, the bonding force between the stage 12 and the resin body 21 according to the present invention is higher than that of the conventional stage 7 and the resin body 2.
It exhibits a bond strength approximately 80 times stronger than that of 1.

このような結合力の差異は、密着力のみを利用した従来
のステージ7と樹脂体21とがその接合面で分離し易い
のに対し、貫通孔13に樹脂体21の一部が充填される
本発明のステージ12と樹脂体21との分離は、樹脂体
21の該充填部分を引きちぎる必要があるためである。
This difference in bonding force is caused by the fact that in the conventional stage 7 and resin body 21 that utilize only adhesion force, it is easy to separate at the joint surface, whereas the through hole 13 is partially filled with the resin body 21. The stage 12 and the resin body 21 of the present invention are separated because the filled portion of the resin body 21 needs to be torn off.

第5図(<)、(0)は本発明に係わるステージを使用
した前記結合力測定用試料の結合力測定後における要部
を示す断面図である。
FIGS. 5(<) and 5(0) are cross-sectional views showing the main parts of the sample for bonding force measurement after the bonding force measurement using the stage according to the present invention.

分離されたステージ12と樹脂体21の要部を示す第5
図において、ステージ12より引き離された樹脂体21
は貫通孔13の下面開口部で破断され、樹脂体21を引
き離したステージ12の貫通孔13には樹脂体21の一
部21aが残るようになる。
The fifth figure shows the main parts of the separated stage 12 and resin body 21.
In the figure, a resin body 21 separated from the stage 12
is broken at the lower opening of the through hole 13, and a portion 21a of the resin body 21 remains in the through hole 13 of the stage 12 from which the resin body 21 has been separated.

表2 前記の表2は、本発明による半導体装置11と従来技術
による半導体装置1とを、温度85℃、湿度85%の高
温高温雰囲気中で吸湿させたのち、200°Cの高温雰
囲気中で約60秒間乾燥させたとき、樹脂外装4に発生
するクランクの有無を調べた実験データである。
Table 2 The above Table 2 shows that the semiconductor device 11 according to the present invention and the semiconductor device 1 according to the prior art were exposed to moisture in a high temperature atmosphere of 85° C. and humidity of 85%, and then in a high temperature atmosphere of 200° C. This is experimental data for examining the presence or absence of cranks that occur in the resin sheath 4 when it is dried for about 60 seconds.

表2から明らかなように、半導体装置11では樹脂外装
4にクランクが発生しないようになる。
As is clear from Table 2, in the semiconductor device 11, no crank occurs in the resin sheath 4.

第6図は本発明の他の実施例による半導体装置のステー
ジの平面図(イ)とその一部の拡大断面図(U)である
FIG. 6 is a plan view (A) of a stage of a semiconductor device according to another embodiment of the present invention and an enlarged sectional view (U) of a portion thereof.

第6図(イ)において、金属板ステージ16は複数個の
貫通穴17を具え、ステージ16の上面に対し下面で右
方向へずれるように形成された貫通穴17は、例えば第
6図(II)に示す如く、ステージ16の上面に設けた
エツチングマスク18に対し、ステージ16の上面に設
けたエツチングマスク19が右方向へずれるように形成
し、マスク18.19を利用してエツチングによって形
成する。
In FIG. 6(A), the metal plate stage 16 has a plurality of through holes 17, and the through holes 17 are formed so as to be shifted to the right on the lower surface with respect to the upper surface of the stage 16. ), the etching mask 19 provided on the top surface of the stage 16 is formed so as to be shifted to the right with respect to the etching mask 18 provided on the top surface of the stage 16, and etching is performed using the masks 18 and 19. .

前述の貫通穴13に相当する貫通穴17は、ステージ1
6に半導体チップを搭載し樹脂外装を形成したとき該樹
脂外装の一部が充填され、そのごとによってステージ1
6と樹脂外装とは強固に結合され、その結合力は前述の
金属板ステージ12を使用したものと同等になる。
A through hole 17 corresponding to the aforementioned through hole 13 is provided in stage 1.
When a semiconductor chip is mounted on 6 and a resin casing is formed, a part of the resin casing is filled.
6 and the resin exterior are firmly bonded, and the bonding strength is equivalent to that using the metal plate stage 12 described above.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、半導体チップを搭
載するステージとそれらを封止する樹脂外装との結合力
を強化したことにより、はんだによる半導体装置の実装
に際して樹脂外装にはクラックが発生しないようになり
、実装時の加熱による半導体チップの性能低下および、
寿命低下を除去し得た効果が顕著である。
As explained above, according to the present invention, by strengthening the bonding force between the stage on which a semiconductor chip is mounted and the resin sheath that seals them, cracks do not occur in the resin sheath when semiconductor devices are mounted with solder. As a result, the performance of semiconductor chips deteriorates due to heating during mounting, and
The effect of eliminating the reduction in lifespan is remarkable.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例による半導体装置の模式断面
図、 第2図は第1図に示すステージ、 第3図は本発明に係わるステージにあけた貫通孔の実施
例を示す断面図、 第4図はステージと樹脂体との結合力測定用試料の側面
図、 第5図は本発明に係わる結合力測定用試料の結合力測定
後における要部の断面図、 第6図は本発明の他の実施例による半導体装置に係わる
ステージ、 第7図は従来の半導体装置を示す模式断面図、第8図は
従来の半導体装置における樹脂外装の熱膨張を示す模式
図、 第9図は従来の他の半導体装置におけるステージ、 である。 図中において、 2は半導体チップ、 4は封止樹脂(樹脂外装)、 11は半導体装置、 12、16はステージ、 13、17は透孔、 頑べ1面図 第 1 図 第1図に示すステージめ平面図 (イ) (口〕 晃+図 要部のめ面図 (イ) c口) 本発明のイ已の突施イテ]による半導体装置におjテる
ステー5゛第 6 図 従来の半導体装置を示す挨戊吋面図 辷=   9  「η
FIG. 1 is a schematic sectional view of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a stage shown in FIG. 1, and FIG. 3 is a sectional view showing an embodiment of a through hole formed in a stage according to the present invention. , Fig. 4 is a side view of a sample for measuring the bonding force between the stage and the resin body, Fig. 5 is a cross-sectional view of the main part of the sample for measuring the bonding force according to the present invention after measuring the bonding force, and Fig. 6 is a side view of the sample for measuring the bonding force between the stage and the resin body. A stage related to a semiconductor device according to another embodiment of the invention, FIG. 7 is a schematic sectional view showing a conventional semiconductor device, FIG. 8 is a schematic diagram showing thermal expansion of a resin exterior in a conventional semiconductor device, and FIG. This is a stage in another conventional semiconductor device. In the figure, 2 is a semiconductor chip, 4 is a sealing resin (resin exterior), 11 is a semiconductor device, 12 and 16 are stages, 13 and 17 are through holes, as shown in Figure 1. Planar view of the stage (A) (Opening) + Front view of main parts of the figure (A) (Opening) Fig. 6 Conventional method A front view of the semiconductor device = 9 "η

Claims (2)

【特許請求の範囲】[Claims] (1)半導体チップ搭載用の金属板ステージ(12)が
、該ステージ(12)の下面より上面で大きく開口する
複数個の貫通孔(13)を具え、 該ステージ(12)およびその上面に搭載した半導体チ
ップ(2)を樹脂封止してなることを特徴とする半導体
装置。
(1) A metal plate stage (12) for mounting a semiconductor chip is provided with a plurality of through holes (13) that open larger on the upper surface than the lower surface of the stage (12), and is mounted on the stage (12) and its upper surface. A semiconductor device comprising a semiconductor chip (2) sealed with resin.
(2)半導体チップ搭載用の金属板ステージ(16)が
、該ステージ(16)の下面の開口より上面の開口が該
ステージ(16)の側方にずれた複数個の貫通孔(17
)を具え、 該ステージ(16)およびその上面に搭載した半導体チ
ップを樹脂封止してなることを特徴とする半導体装置。
(2) A metal plate stage (16) for mounting a semiconductor chip has a plurality of through holes (17
), and the stage (16) and the semiconductor chip mounted on the upper surface thereof are sealed with resin.
JP1068363A 1989-03-20 1989-03-20 Semiconductor device Pending JPH02246359A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1068363A JPH02246359A (en) 1989-03-20 1989-03-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1068363A JPH02246359A (en) 1989-03-20 1989-03-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH02246359A true JPH02246359A (en) 1990-10-02

Family

ID=13371633

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1068363A Pending JPH02246359A (en) 1989-03-20 1989-03-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH02246359A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH036851A (en) * 1989-06-03 1991-01-14 Shinko Electric Ind Co Ltd Lead frame
JPH04324667A (en) * 1991-04-24 1992-11-13 Mitsui High Tec Inc Lead frame and its manufacture
JPH04324668A (en) * 1991-04-24 1992-11-13 Mitsui High Tec Inc Lead frame
US5367191A (en) * 1991-09-18 1994-11-22 Fujitsu Limited Leadframe and resin-sealed semiconductor device
JPH0710939U (en) * 1993-07-28 1995-02-14 サンケン電気株式会社 Semiconductor device having circuit board
US5659199A (en) * 1995-10-30 1997-08-19 Mitsubishi Denki Kabushiki Kaisha Resin sealed semiconductor device
EP1073116A3 (en) * 1999-07-09 2002-03-27 Shinko Electric Industries Co. Ltd. Lead frame and semiconductor device
JP2009302209A (en) * 2008-06-11 2009-12-24 Nec Electronics Corp Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device
EP4141926A1 (en) * 2021-08-31 2023-03-01 NXP USA, Inc. Packaged semiconductor device, leadframe and method for improved bonding

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH036851A (en) * 1989-06-03 1991-01-14 Shinko Electric Ind Co Ltd Lead frame
JPH04324667A (en) * 1991-04-24 1992-11-13 Mitsui High Tec Inc Lead frame and its manufacture
JPH04324668A (en) * 1991-04-24 1992-11-13 Mitsui High Tec Inc Lead frame
US5367191A (en) * 1991-09-18 1994-11-22 Fujitsu Limited Leadframe and resin-sealed semiconductor device
US5753535A (en) * 1991-09-18 1998-05-19 Fujitsu Limited Leadframe and resin-sealed semiconductor device
JPH0710939U (en) * 1993-07-28 1995-02-14 サンケン電気株式会社 Semiconductor device having circuit board
US5659199A (en) * 1995-10-30 1997-08-19 Mitsubishi Denki Kabushiki Kaisha Resin sealed semiconductor device
DE19618976C2 (en) * 1995-10-30 2002-06-27 Mitsubishi Electric Corp Resin sealed semiconductor device
EP1073116A3 (en) * 1999-07-09 2002-03-27 Shinko Electric Industries Co. Ltd. Lead frame and semiconductor device
JP2009302209A (en) * 2008-06-11 2009-12-24 Nec Electronics Corp Lead frame, semiconductor device, manufacturing method of lead frame, and manufacturing method of semiconductor device
EP4141926A1 (en) * 2021-08-31 2023-03-01 NXP USA, Inc. Packaged semiconductor device, leadframe and method for improved bonding

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