JPH0224643U - - Google Patents

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Publication number
JPH0224643U
JPH0224643U JP10174188U JP10174188U JPH0224643U JP H0224643 U JPH0224643 U JP H0224643U JP 10174188 U JP10174188 U JP 10174188U JP 10174188 U JP10174188 U JP 10174188U JP H0224643 U JPH0224643 U JP H0224643U
Authority
JP
Japan
Prior art keywords
digital signal
converter
resistors
switch
operational amplifier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10174188U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10174188U priority Critical patent/JPH0224643U/ja
Publication of JPH0224643U publication Critical patent/JPH0224643U/ja
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本考案にかかる加算形D/A変換装
置の一実施例を示す回路図、第2図は、同加算形
D/A変換装置の他の実施例を示す回路図、第3
図は、同加算形D/A変換装置の他の実施例を示
す回路図、第4図は、同加算形D/A変換装置の
他の実施例を示す回路図、第5図は、同加算形D
/A変換装置の他の実施例を示す回路図、第6図
は、同実施例の一部詳細回路図、第7図は、同実
施例の動作を示すフローチヤート、第8図は、従
来の加算形D/A変換装置を示す回路図である。 10…デイジタル信号発生手段、13…抵抗、
14…オペアンプ、15…フイードバツク抵抗、
16…補正用抵抗、17…スイツチ、19…A/
D変換器、20…判断指令手段、21…表示部、
30…判断制御手段。
FIG. 1 is a circuit diagram showing one embodiment of the additive D/A converter according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the additive D/A converter, and FIG.
FIG. 4 is a circuit diagram showing another embodiment of the additive D/A converter, FIG. 5 is a circuit diagram showing another embodiment of the additive D/A converter, and FIG. Additive form D
6 is a partially detailed circuit diagram of the same embodiment, FIG. 7 is a flowchart showing the operation of the same embodiment, and FIG. 8 is a circuit diagram showing another embodiment of the A/A converter. FIG. 2 is a circuit diagram showing an additive type D/A converter of FIG. 10... Digital signal generating means, 13... Resistor,
14... operational amplifier, 15... feedback resistor,
16...Correction resistor, 17...Switch, 19...A/
D converter, 20...judgment command means, 21...display section,
30...Judgment control means.

Claims (1)

【実用新案登録請求の範囲】 (1) デイジタル信号を発生するデイジタル信号
発生手段と、そのデイジタル信号を各入力する、
所定比率の値を有する複数個の抵抗と、その抵抗
に接続された、フイードバツク抵抗を有するオペ
アンプとを備えた加算形D/A変換装置において
、スイツチを有する補正用抵抗が複数個前記フイ
ードバツク抵抗に接続され、前記オペアンプの出
力端がA/D変換器へ接続され、そのA/D変換
器によりデイジタル信号化された信号と前記デイ
ジタル信号発生手段の発生デイジタル信号値とを
比較し、その両デイジタル信号が等しくなる様な
前記補正用抵抗のスイツチの適正オンオフ状態を
指示する判断指令手段と、その判断指令手段の出
力を表示する表示部とが備えられたことを特徴と
する加算形D/A変換装置。 (2) デイジタル信号を発生するデイジタル信号
発生手段と、そのデイジタル信号を各入力する、
所定比率の値を有する複数個の抵抗と、その抵抗
に接続された、フイードバツク抵抗を有するオペ
アンプとを備えた加算形D/A変換装置において
、スイツチを有する補正用抵抗が複数個前記フイ
ードバツク抵抗に接続され、前記オペアンプの出
力端がA/D変換器へ接続され、そのA/D変換
器によりデイジタル信号化された信号と前記デイ
ジタル信号発生手段の発生デイジタル信号値とを
比較し、その両デイジタル信号値が等しくなる様
に、前記補正用抵抗のスイツチをオンオフさせる
判断制御手段が備えられていることを特徴とする
加算形D/A変換装置。 (3) 前記スイツチと前記補正用抵抗は直列に接
続され、その直列接続回路が互いに並列状態で接
続され、その並列状態回路が前記フイードバツク
抵抗に直列又は並列接続されていることを特徴と
する請求項1又は2記載の加算形D/A変換装置
。 (4) 前記スイツチと前記補正用抵抗は並列に接
続され、その並列接続回路が互いに直列状態で接
続され、その直列状態回路が前記フイードバツク
抵抗に直列又は並列接続されていることを特徴と
する請求項1又は2記載の加算形D/A変換装置
。
[Scope of Claim for Utility Model Registration] (1) A digital signal generating means for generating a digital signal, and each input of the digital signal;
In an additive D/A converter including a plurality of resistors having a value at a predetermined ratio and an operational amplifier having a feedback resistor connected to the resistors, a plurality of correction resistors each having a switch are connected to the feedback resistor. The output terminal of the operational amplifier is connected to an A/D converter, and the signal converted into a digital signal by the A/D converter is compared with the digital signal value generated by the digital signal generating means, and the output terminal of the operational amplifier is connected to an A/D converter. An additive type D/A, characterized in that it is provided with judgment command means for instructing the proper on/off state of the switch of the correction resistor so that the signals become equal, and a display section for displaying the output of the judgment command means. conversion device. (2) a digital signal generating means for generating a digital signal and inputting each of the digital signals;
In an additive D/A converter including a plurality of resistors having a value at a predetermined ratio and an operational amplifier having a feedback resistor connected to the resistors, a plurality of correction resistors each having a switch are connected to the feedback resistor. The output terminal of the operational amplifier is connected to an A/D converter, and the signal converted into a digital signal by the A/D converter is compared with the digital signal value generated by the digital signal generating means, and the output terminal of the operational amplifier is connected to an A/D converter. An additive type D/A converter, characterized in that it is provided with judgment control means for turning on and off the switch of the correction resistor so that the signal values become equal. (3) A claim characterized in that the switch and the correction resistor are connected in series, the series connection circuits thereof are connected in parallel with each other, and the parallel state circuit is connected in series or in parallel with the feedback resistor. Item 2. Additive D/A converter according to item 1 or 2. (4) A claim characterized in that the switch and the correction resistor are connected in parallel, their parallel connection circuits are connected in series with each other, and the series state circuit is connected in series or in parallel with the feedback resistor. Item 2. Additive D/A converter according to item 1 or 2.
JP10174188U 1988-07-29 1988-07-29 Pending JPH0224643U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10174188U JPH0224643U (en) 1988-07-29 1988-07-29

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10174188U JPH0224643U (en) 1988-07-29 1988-07-29

Publications (1)

Publication Number Publication Date
JPH0224643U true JPH0224643U (en) 1990-02-19

Family

ID=31331015

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10174188U Pending JPH0224643U (en) 1988-07-29 1988-07-29

Country Status (1)

Country Link
JP (1) JPH0224643U (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53124053A (en) * 1977-04-06 1978-10-30 Hitachi Ltd D/a converter with correction circuit
JPS5854727A (en) * 1981-09-29 1983-03-31 Toshiba Corp Analog output device
JPS5864812A (en) * 1981-10-15 1983-04-18 Victor Co Of Japan Ltd Level controller
JPS60111511A (en) * 1983-11-19 1985-06-18 Nec Corp Agc amplifier
JPS60237811A (en) * 1984-05-09 1985-11-26 日本電信電話株式会社 Cable conduit wire passing device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53124053A (en) * 1977-04-06 1978-10-30 Hitachi Ltd D/a converter with correction circuit
JPS5854727A (en) * 1981-09-29 1983-03-31 Toshiba Corp Analog output device
JPS5864812A (en) * 1981-10-15 1983-04-18 Victor Co Of Japan Ltd Level controller
JPS60111511A (en) * 1983-11-19 1985-06-18 Nec Corp Agc amplifier
JPS60237811A (en) * 1984-05-09 1985-11-26 日本電信電話株式会社 Cable conduit wire passing device

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