JPH0224678U - - Google Patents

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Publication number
JPH0224678U
JPH0224678U JP10267088U JP10267088U JPH0224678U JP H0224678 U JPH0224678 U JP H0224678U JP 10267088 U JP10267088 U JP 10267088U JP 10267088 U JP10267088 U JP 10267088U JP H0224678 U JPH0224678 U JP H0224678U
Authority
JP
Japan
Prior art keywords
video signal
circuit
level
fade
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10267088U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10267088U priority Critical patent/JPH0224678U/ja
Publication of JPH0224678U publication Critical patent/JPH0224678U/ja
Pending legal-status Critical Current

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  • Studio Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例のビデオ信号フエード
アウト・フエードイン回路のブロツク図、第2図
は第1図の回路図、第3図は第1図および第2図
の動作を説明するための波形図、第4図は従来例
のブロツク図、第5図は第4図の1部を説明する
ための回路図である。 1……直流レベル可変回路、2……電流制御回
路、3……ペデスタルレベルスライス回路、4…
…ブランキング信号、5……フエード制御信号、
6……ビデオ信号フエードアウト・フエードイン
回路、8……ビデオ信号、15……水平ブランキ
ング期間、16……映像期間、17……ペデスタ
ルレベル。
Fig. 1 is a block diagram of a video signal fade-out/fade-in circuit according to an embodiment of the present invention, Fig. 2 is a circuit diagram of Fig. 1, and Fig. 3 is a waveform for explaining the operation of Figs. 1 and 2. 4 is a block diagram of a conventional example, and FIG. 5 is a circuit diagram for explaining a part of FIG. 4. 1... DC level variable circuit, 2... Current control circuit, 3... Pedestal level slice circuit, 4...
...Blanking signal, 5...Fade control signal,
6...Video signal fade-out/fade-in circuit, 8...Video signal, 15...Horizontal blanking period, 16...Video period, 17...Pedestal level.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 制御信号に応じてビデオ信号のレベルを制御す
るビデオ信号フエードアウト・フエードイン回路
において、前記ビデオ信号から検出したブランキ
ング信号に応答してブランキング期間以外の映像
期間には前記制御信号に応じて任意の電流値に制
御した電流を得る電流制御手段と、前記ビデオ信
号に応答し前記電流制御手段の前記制御した電流
に応じて前記ビデオ信号の直流電位を変化させる
直流レベル変化回路と、前記直流レベル変化回路
を介して送出された前記ビデオ信号の映像信号領
域中、ペデスタルレベルに対して白レベルと反対
側に位置するレベルの部分を前記ペデスタルレベ
ルに制限するリミツタ回路とを設けたことを特徴
とするビデオ信号フエードアウト・フエードイン
回路。
In a video signal fade-out/fade-in circuit that controls the level of a video signal according to a control signal, in response to a blanking signal detected from the video signal, any video period other than the blanking period is controlled according to the control signal. current control means for obtaining a current controlled to a current value; a DC level change circuit that responds to the video signal and changes the DC potential of the video signal in accordance with the controlled current of the current control means; and the DC level change circuit. A limiter circuit is provided for limiting a portion of a level located on the opposite side of the white level to the pedestal level to the pedestal level in the video signal area of the video signal sent through the circuit. Video signal fade-out/fade-in circuit.
JP10267088U 1988-08-02 1988-08-02 Pending JPH0224678U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10267088U JPH0224678U (en) 1988-08-02 1988-08-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10267088U JPH0224678U (en) 1988-08-02 1988-08-02

Publications (1)

Publication Number Publication Date
JPH0224678U true JPH0224678U (en) 1990-02-19

Family

ID=31332792

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10267088U Pending JPH0224678U (en) 1988-08-02 1988-08-02

Country Status (1)

Country Link
JP (1) JPH0224678U (en)

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