JPH0225113A - Frequency synthesizer - Google Patents

Frequency synthesizer

Info

Publication number
JPH0225113A
JPH0225113A JP63175384A JP17538488A JPH0225113A JP H0225113 A JPH0225113 A JP H0225113A JP 63175384 A JP63175384 A JP 63175384A JP 17538488 A JP17538488 A JP 17538488A JP H0225113 A JPH0225113 A JP H0225113A
Authority
JP
Japan
Prior art keywords
frequency
control signal
frequency division
loop gain
synthesizer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63175384A
Other languages
Japanese (ja)
Inventor
Tetsushi Murai
村井 哲史
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63175384A priority Critical patent/JPH0225113A/en
Publication of JPH0225113A publication Critical patent/JPH0225113A/en
Pending legal-status Critical Current

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  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain an open loop gain characteristic stable over a broad band by controlling the open loop gain of a loop filter of a frequency synthesizer by an open loop gain control signal in response to a frequency division control signal. CONSTITUTION:A phase locked loop controls a divided frequency N by using a frequency division control signal 8 from a frequency control circuit 7 and acts like a frequency synthesizer. In this case, switches S1A-S1D switching resistors R1A-R1D in an active filter 6a by using an open loop gain control signal 9 of the active loop filter from an external frequency control circuit 7 are controlled according to a frequency division control signal. That is, when a parallel combined resistance R1(N) of the resistors R1A-R1D switched on according to the frequency division number N of a frequency divider 3 is set in multi-stage according to the frequency division number N, even if the frequency division number N is fluctuated into 2XN, 3XN-, the fluctuation of the open loop gain KS of the synthesizer is suppressed by controlling the resistance R1(N) to be 1/2,1/3-.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、マイクロ波帯域で使用される周波数シンセ
サイザに関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a frequency synthesizer used in the microwave band.

〔従来の技術〕[Conventional technology]

第2図は従来のマイクa波帯周波数シンセサイザを示し
たもので、図において、1はシンセサイズ周波数信号、
2は電圧制御発振器、3は分周器、4は位相比較器、5
は基準周波数信号、6は抵抗R,,R,、コンデンサC
3等により構成される能動型ループフィルタ、7は外部
の周波数制御回路、8は分周数制御信号である。
Figure 2 shows a conventional microphone A-wave frequency synthesizer. In the figure, 1 is a synthesized frequency signal;
2 is a voltage controlled oscillator, 3 is a frequency divider, 4 is a phase comparator, 5
is the reference frequency signal, 6 is the resistor R,,R,, capacitor C
3, etc., 7 is an external frequency control circuit, and 8 is a frequency division number control signal.

次に動作について説明する。電圧制御発振器2より発振
された信号は、外部の周波数制御回路7からの分周数制
御信号8により分周数が可変できる分周器3にて分周さ
れ、基準周波数信号5と位相比較器4にて比較される。
Next, the operation will be explained. The signal oscillated by the voltage controlled oscillator 2 is frequency-divided by a frequency divider 3 whose frequency can be varied by a frequency division number control signal 8 from an external frequency control circuit 7. 4 for comparison.

この2つの周波数の差により位相比較器4は交流電圧を
発生し、この交流電圧は能動型ループフィルタ6を通っ
て誤差電圧となり、電圧制御発振器2は該誤差電圧に応
じた周波数で発振を行ない、本シンセサイザを同期状態
に引込む、この同期した信号をシンセサイズ周波数信号
lとして使用する。この際、電圧制御発振器2の変調感
度2位相比較器4の検波感度および分周器の分周数をそ
れぞれK1.KtおよびNとすると、本装置全体の開ル
ープ利得に、は(1)式で与えられる。
Due to the difference between these two frequencies, the phase comparator 4 generates an AC voltage, which passes through the active loop filter 6 and becomes an error voltage, and the voltage controlled oscillator 2 oscillates at a frequency corresponding to the error voltage. , which pulls the synthesizer into a synchronized state and uses this synchronized signal as the synthesized frequency signal l. At this time, the modulation sensitivity of the voltage controlled oscillator 2, the detection sensitivity of the phase comparator 4, and the frequency division number of the frequency divider are set to K1. Assuming Kt and N, the open loop gain of the entire device is given by equation (1).

Ka=に+  ・K2 ・ (R2/R1)/N・・・
(11ここでRt / Rl は能動型ループフィルタ
の開ループ利得である。
Ka=ni+ ・K2 ・(R2/R1)/N...
(11 where Rt/Rl is the open-loop gain of the active loop filter.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

従来のマイクロ波帯周波数シンセサイザは、以上のよう
に構成されているので、分周器3の分周数Nを、2XN
、3XN、・・・とした際に、本装置の開ループ利得K
AがKa / 2 、  KA / 3 、・・・とな
り、分周数Nの可変範囲に制限があるなどの問題点があ
った。
Since the conventional microwave band frequency synthesizer is configured as described above, the frequency division number N of the frequency divider 3 is set to 2XN.
, 3XN,..., the open loop gain K of this device is
There were problems such as A being Ka/2, KA/3, . . . , and that there was a limit to the variable range of the frequency division number N.

この発明は、上記のような従来のものの問題点を解消す
るためになされたもので、分周器の分周数Nを変化させ
た場合でも、本装置全体の開ループ利得KAの変動を抑
えることができるマイクロ波帯周波数シンセサイザを得
ることを目的としている。
This invention was made to solve the problems of the conventional devices as described above, and even when the frequency division number N of the frequency divider is changed, fluctuations in the open loop gain KA of the entire device can be suppressed. The purpose is to obtain a microwave band frequency synthesizer that can perform the following steps.

〔課題を解決するための手段〕[Means to solve the problem]

この発明に係るマイクロ波帯周波数シンセサイザは、能
動型ループフィルタの開ループ利得を決定する要因の1
つである抵抗R1値を外部の周波数制御回路より、分周
数Nと同時に変化させるようにしたものである。
The microwave band frequency synthesizer according to the present invention is one of the factors that determines the open loop gain of the active loop filter.
The value of the resistor R1 is changed simultaneously with the frequency division number N by an external frequency control circuit.

即ち、能動型ループフィルタ6の間ループ利得を決定す
る要因の1つである、位相比較器と演算増幅器との間に
ある抵抗を相互に並列接続された複数の抵抗に替え、か
つそれらの抵抗に、分周数制御信号に応じて変化する開
ループ利得制御信号により開閉するスイッチをそれぞれ
直列に接続し、該スイッチを、周波数制御と共に制御し
て、総合の抵抗値を可変できるようにしたものである。
That is, the resistance between the phase comparator and the operational amplifier, which is one of the factors that determines the loop gain between the active loop filter 6, is replaced with a plurality of resistances connected in parallel with each other, and those resistances are In this case, switches are connected in series that are opened and closed by an open-loop gain control signal that changes according to the frequency division control signal, and the switches are controlled together with the frequency control so that the overall resistance value can be varied. It is.

〔作用〕[Effect]

この発明においては、上述のように構成することにより
、分周器の分周数とともに能動ループフィルタの開ルー
プ利得を制御できるようにしたので、本装置の開ループ
利得KAの変動が抑えられ、広い帯域にわたって安定な
マイクロ波帯の周波数シンセサイザを構成することがで
きる。
In this invention, by configuring as described above, it is possible to control the frequency division number of the frequency divider as well as the open loop gain of the active loop filter, so that fluctuations in the open loop gain KA of the device can be suppressed. It is possible to construct a microwave band frequency synthesizer that is stable over a wide band.

〔実施例〕〔Example〕

以下、この発明の一実施例を図について説明する。第1
図は本発明の一実施例による周波数シンセサイザを示し
、図において、1はシンセサイズ周波数信号、2は電圧
制御発振器、3は分周器、4は位相比較器、5は基準周
波数信号、7は外部の周波数制御回路、8は分周制御信
号であり、これらは従来と同様のものである。9は能動
型ループフィルタの間ループ利得制御信号、6aはこの
間ループ利得制御信号9により開閉するスイッチに各々
直列に接続された抵抗Rla−RID+ 能動型ループ
フィルタのフィードバック抵抗R1+およびフィードバ
ックコンデンサ01等からなる能動型ループフィルタで
ある。
An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a frequency synthesizer according to an embodiment of the present invention, in which 1 is a synthesized frequency signal, 2 is a voltage controlled oscillator, 3 is a frequency divider, 4 is a phase comparator, 5 is a reference frequency signal, and 7 is a frequency synthesizer. The external frequency control circuit 8 is a frequency division control signal, which is the same as the conventional one. 9 is a loop gain control signal between the active loop filters, 6a is a resistor Rla-RID+ connected in series with a switch that is opened and closed by the loop gain control signal 9 during this period, a feedback resistor R1+ of the active loop filter, a feedback capacitor 01, etc. This is an active loop filter.

次に動作について説明する。従来のものと同様、電圧制
御発振器2.外部の周波数制御回路7からの分周数制御
信号8により分周数が可変できる分周器35位相比較器
4および能動型ループフィルタ6aによって構成された
位相同期ループは、周波数制御回路7からの分周数制御
信号8により分周数Nを制御し、周波数シンセサイザと
して動作する。この際、能動型ループフィルタ6a内の
抵抗R,,”−R,Dを外部の周波数制御回路7がらの
能動型ループフィルタの開ループ利得制御信号9により
開閉するスイッチsea”’sinを、分周数制御信号
に従って制御すると、本装置の開ループ利得に8は K m = K I−K z  ・ (R2/R,。、
)/Nとなる。
Next, the operation will be explained. Similar to the conventional one, a voltage controlled oscillator2. A phase-locked loop constituted by a frequency divider 35 whose frequency division number can be varied by a frequency division number control signal 8 from an external frequency control circuit 7, a phase comparator 4, and an active loop filter 6a is connected to a frequency division number control signal 8 from an external frequency control circuit 7. The frequency division number N is controlled by the frequency division number control signal 8, and it operates as a frequency synthesizer. At this time, a switch sea"'sin that opens and closes the resistors R, , "-R, and D in the active loop filter 6a in accordance with the open loop gain control signal 9 of the active loop filter from the external frequency control circuit 7 is switched on and off. When controlled according to the frequency control signal, the open loop gain of the device is 8, which is K m = K I - Kz ・ (R2/R,.
)/N.

但し、K、:ii電圧制御発振器の変調感度に、二位相
比較器4の検波感度 R目、)二分周数Nに従いスイッチがオンされた抵抗R
IA’−’−R10の並列和N :分周器3の分周数 に2 :本装置の開ループ利得 Rt :能動型ループフィルタ6aのフィードバック抵
抗 である。
However, K: ii: the modulation sensitivity of the voltage controlled oscillator, the detection sensitivity R of the two-phase comparator 4,) the resistor R that is switched on according to the frequency division number N;
Parallel sum N of IA'-'-R10: 2 for the frequency division number of the frequency divider 3: Open loop gain Rt of this device: Feedback resistance of the active loop filter 6a.

従って、R+ onを分周数Nにより多段に分けて設定
すれば、Nの値が2XN、3XN、・・・に変動しても
、RIIN)を、1/2倍、173倍、・・・となるよ
うに制御することで、本装置の間ループ利得に、の変動
を抑えることができ、広帯域にわたって安定した開ルー
プ利得特性を有するマイクロ波帯の周波数シンセサイザ
を得ることができる。
Therefore, if R+on is set in multiple stages according to the frequency division number N, even if the value of N changes to 2XN, 3XN, etc., RIIN) can be set by 1/2, 173 times, etc. By controlling it so that it is possible to suppress fluctuations in the loop gain of this device, it is possible to obtain a frequency synthesizer in the microwave band that has stable open-loop gain characteristics over a wide band.

なお、上記実施例では、演算増幅器とその前段の位相比
較器との間の抵抗として、相互に並列接続された複数の
抵抗を用いる場合についてのみ説明したが、本発明はこ
の場合に限定されるものではなく、分周数の変化に応じ
た開ループ利得の変動を、演算増幅器とその前段の位相
比較器との間の抵抗値を変化されることにより相殺する
構成であればよいことは言うまでもない。
Note that in the above embodiment, only the case where a plurality of resistors connected in parallel are used as the resistor between the operational amplifier and the phase comparator at the preceding stage thereof is described, but the present invention is limited to this case. Needless to say, it is sufficient to have a configuration in which the fluctuations in open loop gain due to changes in the frequency division number are canceled out by changing the resistance value between the operational amplifier and the phase comparator in the preceding stage. stomach.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、周波数シンセサイザ
のループフィルタの開ループ利得を、分周数制御信号に
応じた開ループ利得制御信号により制御するようにした
ので、広い帯域にわたって安定した開ループ利得特性を
有するマイクロ波帯の周波数シンセサイザを得ることが
できる効果がある。
As described above, according to the present invention, the open-loop gain of the loop filter of the frequency synthesizer is controlled by the open-loop gain control signal corresponding to the frequency division number control signal, so that the open-loop gain is stable over a wide band. There is an effect that a microwave band frequency synthesizer having gain characteristics can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例によるマイクロ波帯周波数
シンセサイザを示すブロック図、第2図は従来のマイク
ロ波帯周波数シンセサイザを示すブロック図である。 図において、1はシンセサイザ周波数信号、2は電圧制
御発振器、3は分周器、4は位相比較器、5は基準周波
数信号、7は周波数制御回路、8は分周制御信号、9は
開ループ利得制御信号、6゜6aは能動型ループフィル
タ、61は演算増幅器、R、、”−R、塾は抵抗、84
〜5ltlはスイッチ、R。 はフィードバック抵抗、C1はフィードバックコンデン
サである。 第1図
FIG. 1 is a block diagram showing a microwave band frequency synthesizer according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional microwave band frequency synthesizer. In the figure, 1 is a synthesizer frequency signal, 2 is a voltage controlled oscillator, 3 is a frequency divider, 4 is a phase comparator, 5 is a reference frequency signal, 7 is a frequency control circuit, 8 is a frequency division control signal, and 9 is an open loop Gain control signal, 6°6a is active loop filter, 61 is operational amplifier, R, ”-R, cram is resistor, 84
~5ltl is a switch, R. is a feedback resistor, and C1 is a feedback capacitor. Figure 1

Claims (1)

【特許請求の範囲】[Claims] (1)出力信号を発振する電圧制御発振器と、該電圧制
御発振器の出力を分周する分周器と、該分周器の出力と
基準周波数信号とを位相比較する位相比較器と、 該位相比較器の出力を濾波して上記電圧制御発振器の制
御信号を作成する能動型ループフィルタと、 上記分周器の分周数を制御する分周器制御信号を作成し
出力信号の発振周波数を制御する周波数制御回路と、 上記位相比較器と上記ループフィルタ内の演算増幅器と
の間に設けられた、上記ループフィルタの開ループ利得
を決定する抵抗と、 上記分周器制御信号に応じた開ループ利得制御信号に応
じて上記抵抗の抵抗値を変化させる可変抵抗手段とを備
え、 本シンセサイザの周波数制御と開ループ利得制御とを同
時に実行できることを特徴と する周波数シンセサイザ。
(1) A voltage controlled oscillator that oscillates an output signal, a frequency divider that divides the output of the voltage controlled oscillator, a phase comparator that compares the phase of the output of the frequency divider and a reference frequency signal, and the phase An active loop filter that filters the output of the comparator to create a control signal for the voltage controlled oscillator, and a divider control signal that controls the frequency division number of the frequency divider to control the oscillation frequency of the output signal. a frequency control circuit that determines the open loop gain of the loop filter, the resistor being provided between the phase comparator and the operational amplifier in the loop filter, and an open loop responsive to the frequency divider control signal. A frequency synthesizer comprising variable resistance means for changing the resistance value of the resistor according to a gain control signal, and capable of simultaneously performing frequency control and open-loop gain control of the synthesizer.
JP63175384A 1988-07-14 1988-07-14 Frequency synthesizer Pending JPH0225113A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63175384A JPH0225113A (en) 1988-07-14 1988-07-14 Frequency synthesizer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63175384A JPH0225113A (en) 1988-07-14 1988-07-14 Frequency synthesizer

Publications (1)

Publication Number Publication Date
JPH0225113A true JPH0225113A (en) 1990-01-26

Family

ID=15995168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63175384A Pending JPH0225113A (en) 1988-07-14 1988-07-14 Frequency synthesizer

Country Status (1)

Country Link
JP (1) JPH0225113A (en)

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