JPH0225189A - Television receiver - Google Patents

Abstract

PURPOSE:To improve the resolution by stopping a time division operation of an input slave pattern video signal when a color killer signal to the input slave pattern video signal is detected in the picture-in-picture system. CONSTITUTION:When a color killer signal is obtained from a color killer circuit 7 of a color signal reproducing circuit 5 of the system of the slave pattern video signal, it is fed to a memory controller/synchronizing conversion circuit/ pattern reduction circuit 15 to stop the time division of an input/output pattern video signal. When a color killer signal is outputted from the color killer circuit 7, a digital continuous luminance signal DA-DATA read out of a memory 18 and subjected to pattern reduction processing is fed in common to D/A conversion circuits 19-21. Then a luminance signal in a D/A conversion circuit 19 while being D/A-converted in the timing of the leading of a clock signal Y-CLK is fed to a matrix 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a picture-in-picture television receiver.

[Summary of the invention]

The present invention A/D converts the luminance signal and color difference signal of the input sub-screen video signal in a time-division manner to obtain a digital sub-screen time-division video signal, and stores the digital sub-screen time-division video signal in a memory. Write, synchronize with the main screen video signal, read out the digital sub-screen time-division video signal from the memory, perform D/A conversion to obtain the output sub-screen video signal, and output the sub-screen video signal. In a picture-in-picture television receiver that combines the input sub-screen video signal with the main screen video signal, when a color killer signal is detected from the color killer circuit for the input sub-screen video signal, the input sub-screen video signal is By stopping the time division operation of the signal, when a color killer signal is detected from the color killer circuit for the input sub-screen video signal, the band of the output sub-screen video signal is expanded and its resolution is increased. It is designed to improve the

[Conventional technology]

Referring to FIG. 4, a conventional picture-in-picture television receiver disclosed in Japanese Patent Application Laid-Open No. 56-23079 will be described. First, the system of the main screen video signal will be explained. (24) is a TV receiving antenna, and the received signal is transmitted through a tuner circuit (high frequency amplification circuit, frequency conversion circuit, video intermediate frequency amplification circuit,
(25) equipped with a video detection circuit, etc. The composite color video signal from this tuner circuit (25) is supplied to a luminance/chromaticity separation circuit (26) and is separated into a luminance signal Y and a carrier color signal C. This luminance signal Y
and the carrier color signal C are supplied to a luminance and carrier color signal processing circuit/synchronization deflection circuit (27), where a horizontal synchronization signal and a vertical synchronization signal are separated from the luminance signal and sent to a memory controller/synchronization conversion circuit to be described later. / Screen reduction circuit (15
). Further, in this circuit (27), red (R), green (G) and blue (B) signals are demodulated from the carrier color signal and supplied to a switch circuit (23) to be described later.

Next, the system of the child screen video signal will be explained. (1
) is the input terminal to which the composite color video signal for the sub screen (playback signal from the VTR, reception signal from the VTR tuner, video signal from the microcomputer, etc.) is supplied.The composite color video signal from this is input to the amplifier. After being amplified in step (2), the signal is supplied to a low-pass filter (3) and a band-pass filter (4) to extract a luminance signal Y and a carrier color signal C, respectively. Of these, the luminance signal Y is supplied to the on/off switch (10). Further, the carrier color signal C is supplied to a color signal reproducing circuit (5) and demodulated into a red difference signal RY and a blue difference signal B-Y.

Next, this color signal reproducing circuit (5) will be explained. The carrier color signal C from the bandpass filter (4) is ACC
The signal is supplied to a color killer circuit (7), an APC (automatic phase control) circuit (8), and a demodulation circuit (9) through the (automatic saturation control) circuit (6). 9 from APC circuit (8)
A two-phase reference subcarrier signal having a phase difference of 0 degrees is supplied to a demodulation circuit (9), and the carrier color signal from the above-mentioned ACC circuit (6) is converted into a red difference signal RY and a blue difference signal. BY
is demodulated. These red difference signal RY and blue difference signal B-Y are supplied to on/off switches (11) and (12), respectively. Furthermore, when the color killer signal from the color killer circuit (7) is supplied to the fj[1 circuit (9), neither of the color difference signals can be obtained from the demodulation circuit (9).

And the switches (10), (11) and (12) are
Separate control signals Y-SW, (RY
)-Sll, (B-Y)-S-, as described later, these switches (1
At the common connection point of 0), (11) and (12), time-division video signals of a luminance signal and both color difference signals are obtained. This time-division video signal is supplied to the A/D conversion circuit (13), and the memory controller/synchronization conversion circuit/screen reduction circuit (15) is supplied to the A/D conversion circuit (13).
) is converted into a digital time-division video signal An-DATA. This digital time-division video signal An-DATA is then supplied to the memory controller/synchronization conversion circuit/screen reduction circuit (15), so that the vertical and horizontal lengths of the child screen are the same as the vertical and horizontal lengths of the main screen, respectively. After the screen is reduced (thinned) to, for example, 1/3 of the length, the memory (video RAM)
(18) and written.

On the other hand, the luminance signal Y from the low-pass filter (3) is supplied to the synchronization deflection circuit (14), from which the horizontal synchronization signal HD and vertical synchronization signal VD are separated and sent to the memory controller/synchronization conversion circuit/screen reduction circuit. (15), and the burst signal handling gate signal BGP obtained based on the separated horizontal synchronizing signal HD is used as a pedestal clamp signal to the A/D converter circuit (15).
3). The horizontal synchronization signal HD and vertical synchronization signal VD from the synchronization deflection circuit (14) are sent to the memory controller/synchronization conversion circuit/screen reduction circuit (15) from the luminance and carrier color signal processing circuit/synchronization deflection circuit (27). Synchronization conversion is performed so that it can be synchronized with the horizontal and vertical synchronization signals.

(16) is a write clock generation circuit, which generates a frequency that is, for example, three times the color subcarrier frequency (=3.58MHz x 3) based on the horizontal synchronization signal HD from the synchronization deflection circuit (14).
A write clock signal of 10.74 MHz) is generated and supplied to the memory controller/synchronization conversion circuit/screen reduction circuit (15). Further, (17) is a readout clock generation circuit, which generates a frequency three times the color subcarrier frequency (-10.7MHz) based on the horizontal synchronization signal from the luminance and carrier color signal processing circuit/synchronization deflection circuit (27). ) read clock signal is formed and output to the memory controller/
It is supplied to the synchronous conversion circuit/screen reduction circuit (15).

Memory controller/synchronous conversion circuit/double-sided reduction circuit (1
5), the screen-reduced digital time-division video signal DA-D is read out from the memory (18).
ATA is commonly supplied to the D/A conversion circuits (19), (20) and (21) through this circuit (15). In addition, each separate clock signal Y-C generated by this memory controller/synchronous conversion circuit/screen reduction circuit (15)
L.K.

(RY)-CLK and (B-Y)-CLK are each D
/A conversion circuits (19), (20) and (21).

These D/A conversion circuits (19), (20), and (2) convert the luminance signals and red and blue difference signals obtained by D/A conversion separately to the matrix circuit (
22) and matrixed, and the red, green and blue signals obtained therefrom are supplied to a switch circuit (23).

Furthermore, the color killer circuit (
When a color killer signal is obtained from 7), it is supplied as a muting signal to the D/A conversion circuits (20) and (21), and color noise mixed into the black and white screen due to only the luminance signal is generated. We are trying to prevent this.

The switch circuit (23) has its switching controlled by the memory controller/synchronization conversion circuit/screen reduction circuit (15), and the red for the main screen from the luminance and carrier color signal processing circuit/synchronization deflection circuit (27). , green and blue signals and red, green and blue signals for the sub-screen from the matrix circuit (22) are switched and combined, and the combined signal is supplied to the color cathode ray tube of the monitor receiver (28). Then, the main screen B is displayed on the screen of the monitor receiver (28).
P, and a child screen SP having vertical and horizontal lengths that are 1/3 of the vertical and horizontal lengths of the main screen, respectively, and located at the lower left corner of the main screen.
is displayed.

Next, on/off switches (10) and (1) in FIG.
The switching timing of 1) and (12) and the operation of the A/D conversion circuit (13) will be explained with reference to FIG. 6 as well. Memory controller/synchronous conversion circuit/screen reduction circuit (15
) is synchronized with the write clock signal (its frequency is 10.74 MHz as mentioned above) supplied from the write clock generation circuit (16), and its frequency is 1/2 of the frequency of the write clock signal, that is, 5 .37MH
A signal CLK (Fig. 6A) is generated and supplied to the A/D conversion circuit (13). Based on this clock signal CLK, an on/off switch (
10), (11) and (12) control signal Y-
SW, (RY)-SW, (B-Y)-needle (Fig. 6B,
C, D) are formed. The control signal ys- for controlling the switch (10) is synchronized with the clock signal CLK, and its first
A square wave signal having a frequency of /2 and a duty of 50% turns on the switch (10) when this signal is at a high level. Control signal (1?-Y) to control switch (11)
-5kl is synchronized with the clock signal CLK and is 1/4 of the clock signal CLK.
A square wave signal with a duty of 25% and a frequency of
When this is at a high level, the switch (10) is turned on.

Control signal (B-Y)-S- for controlling the switch (12)
is a rectangular wave signal with a duty of 25% that is synchronized with the clock signal CLK, has a frequency of 1/4, and has a phase difference of 180 degrees with respect to the above control signal (RY) -S-. , when this is at a high level, the switch (12) is turned on. and control signals Y-SW, (RY)-SW.

The high level periods of (BY)-5W are made non-overlapping with each other.

Thus, these switches (10), (11) and (1
The time-division video signal from 2) is sent to the A/D conversion circuit (13).
By performing A/D conversion at the rising timing of the clock signal CLK, a digital time-division video signal A D-DATA as shown in FIG. It is supplied to the reduction circuit (15). This digital time-division video signal A
D-DATA is configured such that t digital red difference signal parts RY and digital blue difference signal parts B-Y are arranged alternately between every other digital luminance signal parts Y. There is.

Next, with reference to FIGS. 5 and 6, the D
Clock signals Y-CLK, (R-Y)-CLK supplied to /A conversion circuits (19), (20) and (2),
The (BY)-CLK generation circuit will be explained. Fifth
In the figure, the read clock signal with a frequency of 10.74 MHz from the read clock generation circuit (17) is
172 is supplied to the frequency divider (31) and divided into 1/2,
The frequency divided output is supplied to another 1/2 frequency divider (32). The non-inverted output of the 1/2 frequency divider (32) is then supplied to the D/A conversion circuit (19) as the clock signal Y-CLK (FIG. 6G). Also, 1/2 frequency divider (32)
The inverted output of is supplied to AND gates (34) and (35), and further supplied to another 1/2 frequency divider (33), where the frequency is divided into 1/2. The non-inverting output and the inverting output of this frequency divider (33) are connected to an AND gate (34), (
35). The output of the AND gate (34) is then supplied to the D/A conversion circuit (20) as a clock signal (RY)-CLK (H in FIG. 6). Also, the output of the AND gate (35) is the clock signal (B-
Y) -CLK (Fig. 6 ■), the D/A conversion circuit (
21). And these D/A conversion circuits (
19), (20) and (21) are commonly supplied with the digital time-division video signal DA-DATA (FIG. 6F) read out from the memory (18) and subjected to screen reduction processing, respectively. Clock signal Y-CLK, (RY)-CL
At the rising timing of K, (B-Y)-CLK, the luminance signal and both color difference signals obtained by D/A conversion are supplied to the matrix circuit (22).

[Problem to be solved by the invention]

In such a conventional television receiver, a color killer circuit (7) of a color signal reproducing circuit (5) for a video signal for a small screen is used.
), when a oyster-killer signal is generated, the demodulation circuit (9) does not output a color difference signal, and therefore the A
Only the discrete luminance signal Y is supplied to the /D conversion circuit (13).

In consideration of this point, the present invention provides a method of expanding the band of the output sub-screen video signal and improving its resolution when a color killer signal is detected from the color killer circuit for the input sub-screen video signal. This is an attempt to propose a television receiver that can.

[Means to solve the problem]

The present invention performs time-division A/D conversion of the luminance signal and color difference signal of the input sub-screen video signal to obtain a digital sub-screen time-division video signal, and stores the digital sub-screen time-division video signal in a memory ( 18), and in synchronization with the main screen video signal, read out the digital sub-screen time-division video signal from the memory (18), perform D/A conversion, obtain the output sub-screen video signal, and output it. In a picture-in-picture television receiver configured by combining a sub-screen video signal with a main-screen video signal, a color killer signal was detected from the color killer circuit (7) for the input sub-screen video signal. In this case, the time-division operation of the input sub-screen video signal is stopped.

[Effect]

According to the present invention described above, when a color killer signal is detected from the color killer circuit (7) for the input sub-screen video signal, the time-sharing operation of the input sub-screen video signal is stopped, and thereby the parent The output small screen video signal that is combined with the picture video signal becomes a continuous luminance signal, and the band of the luminance signal is expanded and its resolution is improved.

〔Example〕

Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. 1. In FIG. 1, parts corresponding to those of the conventional example in FIG. is omitted. That is, when a color killer signal is obtained from the color killer circuit (7) of the color signal reproducing circuit (5) of the sub-screen video signal system, it is transmitted to the memory controller/synchronization conversion circuit/
The signal is supplied to the screen reduction circuit (15) to stop the time-division operation of the input sub-screen video signal.

Next, on/off switches (10) and (1) in FIG.
The switching timing of 1) and (12) and the operation of the A/D conversion circuit (13) will be explained with reference to FIG. 3 as well. Memory controller/synchronous conversion circuit/screen reduction circuit (15
) is synchronized with the write clock signal (its frequency is 10.74 MHz as mentioned above) supplied from the write clock generation circuit (16), and its frequency is 1/2 of the frequency of the write clock signal, that is, 5 .3'1M
generate a Hz clock signal CLX (Figure 3A);
This is supplied to the A/D conversion circuit (13). When the color killer circuit (7) does not output the color killer signal, this clock signal CLK is used as in the conventional example.
control signals Y-SW, (R-Y)-5 that control the on-off switches (10), (11) and (12) based on
W, (B-Y)-S-, the above-mentioned Figure 6 B, C,
A signal with the waveform shown in FIG. 3D is generated, and when the color killer signal is output, a control signal Y-SW that is always at a high level as shown in FIG. 3B is supplied to the on-off switch (10), The on-off switch (10) is always on, and the on-off switches (11) and (12) are supplied with a control signal (R) that is always at a low level as shown in FIG. 3C and D.
-Y)-SW and (B-Y)-SW are supplied to keep the on-off switch (II) and (Step 2) off at all times. Therefore, when the color killer signal is output from the color killer circuit (7), the continuous luminance signal from the switch (10) is supplied to the A/D conversion circuit (13) and converted into the clock signal CL. By performing A/D conversion at the rising timing of , a digital luminance signal AD-DATA as shown in FIG. 3E is obtained, which is sent to the memory controller/
It is supplied to the synchronous conversion circuit/screen reduction circuit (15).

Next, with reference to FIGS. 2 and 3, the D
Clock signal Y-CLK supplied to the /A conversion circuits (19), (20) and (21).

The (RY)-CLX and (B-Y)-CLK generation circuits will be described below, but in FIG. 2, parts corresponding to those in FIG. 5 are denoted by the same reference numerals and redundant explanation will be omitted. That is, a changeover switch (36) for switching the divided outputs of the 1/2 frequency dividers (31) and (32), and an AND gate (34).
), and an on/off switch (37) connecting the output side of (35) and ground.

The other configurations are the same as in FIG. 5. When the color killer signal is not detected from the color killer circuit (7), the selector switch (36) is switched to the 1/2 frequency divider (32).
) side and turn off the on/off switch (37), and when a color killer signal is detected, switch the selector switch (36) to 1/2 frequency divider (31) III and turn off the on/off switch (37). ) on.

When the color killer signal is not detected from the color killer circuit (7), the frequency divider (32
) is supplied to the D/A conversion circuit (19) as the clock signal Y-CL (Fig. 6G).
When the color killer signal is output, the non-inverting output of the frequency divider (31) [2 of the frequency of the non-inverting output of the frequency divider (32)]
clock signal Y-CLK] has twice the frequency
(FIG. 3G) is supplied to the D/A conversion circuit (19).

Also, when the color killer signal is not output from the color killer circuit (7), the AND gate (34
) is the clock signal (RY)-CLK (Fig. 6H
), but when the color killer signal is output, the clock signal (R
-Y)-CLK is always at a low level as shown in FIG. 3H. Also, when the color killer signal is not output from the color killer circuit (7), the AND gate (
35) output is the clock signal (B-Y)-CLK
(Fig. 6 I) is supplied to the D/A conversion circuit (21), but when the color killer signal is output, the clock signal (RY) - CLK is always supplied as shown in Fig. 3 ■. Becomes a low level.

When the color killer circuit (7) does not output a color killer signal, these D/A conversion circuits (19)
, (20) and (21) are commonly supplied with the digital time-division video signal 0A-DATA (FIG. 6F) read out from the memory (18) and subjected to screen reduction processing.
Clock signals Y-CLK, (RY)-CLK, respectively.
At the rising timing of (B-Y)-CLK (GSHSI in FIG. 6), the D/A conversion is performed and the obtained luminance signal and both color difference signals are supplied to the matrix (22).

Also, when the color killer signal is output, the D/A conversion circuits (19), (20) and (21) are
), the screen-reduced digital continuous luminance signal DA-DATA (FIG. 3F) is commonly supplied, and the clock signal Y-CLK (FIG. The luminance signal obtained by D/A conversion is supplied to the matrix (22) at the rising timing of FIG. G). In this case, no output is obtained from the D/A conversion circuits (20) and (21).

In the case of this embodiment, when a color killer signal is output from the color killer circuit (7) for the small screen video signal, the band of the luminance signal is expanded to twice that of the conventional example.

〔Effect of the invention〕

According to the present invention described above, the luminance signal and the color difference signal of the input sub-screen video signal are time-divisionally A/D converted to obtain the digital sub-screen time-division video signal, and the digital sub-screen time-division video signal is converted into digital sub-screen time-division video signals. Write the signal to the memory, synchronize with the main screen video signal, read out the digital sub-screen time-division video signal from the memory, perform D/A conversion, obtain the output sub-screen video signal, and output the sub-screen video signal. A picture-in-picture television receiver that combines the screen video signal with the main screen video signal! In the machine, when a color killer signal is detected from a color killer circuit for an input sub-screen video signal, the band of the output sub-screen video signal is expanded and its resolution is improved.

[Brief explanation of the drawing]

FIG. 1 is a professional/two-line diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a part of the circuit of the embodiment, FIG. 3 is a timing chart for explaining the operation of the embodiment, and FIG. FIG. 4 is a block diagram showing a conventional example, FIG. 5 is a block diagram showing some circuits of the conventional example, and FIG. 6 is a timing chart for explaining the operation of the conventional example. (7) is a color killer circuit, (13) is an A/D conversion circuit, (15) is a memory controller/synchronous conversion circuit/screen reduction circuit, (18) is a memory, and (19) to (21) are D
/A conversion circuit, (23) a switch circuit, and (28) a monitor receiver. Hidemori Matsukuma

Claims (1)

[Scope of Claims] The luminance signal and the color difference signal of the input sub-screen video signal are time-divisionally A/D converted to obtain a digital sub-screen time-division video signal; The time-division video signal for the digital sub-screen is read out from the memory in synchronization with the video signal for the main screen, and the D/
In a picture-in-picture television receiver, the input sub-screen is converted into a picture-in-picture television receiver in which an output sub-screen video signal is obtained by A conversion, and the output sub-screen video signal is combined with the main screen video signal. 1. A television receiver characterized in that when a color killer signal is detected from a color killer circuit for a video signal for a sub-screen, the time-division operation of the input sub-screen video signal is stopped.