JPH02258690A - Method of forming semiconductor thin film - Google Patents

Method of forming semiconductor thin film

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Publication number
JPH02258690A
JPH02258690A JP1081102A JP8110289A JPH02258690A JP H02258690 A JPH02258690 A JP H02258690A JP 1081102 A JP1081102 A JP 1081102A JP 8110289 A JP8110289 A JP 8110289A JP H02258690 A JPH02258690 A JP H02258690A
Authority
JP
Japan
Prior art keywords
amorphous
film
thin film
region
semiconductor thin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1081102A
Other languages
Japanese (ja)
Inventor
Takao Yonehara
隆夫 米原
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Canon Inc
Original Assignee
Canon Inc
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Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Priority to JP1081102A priority Critical patent/JPH02258690A/en
Publication of JPH02258690A publication Critical patent/JPH02258690A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To improve controllability of grain boundary positions by providing a region with a high Si atom density at a desired position of an amorphous Si film, heat- treating the region at a specific temperature and growing a crystal from an amorphous Si film in the solid phase based on the crystal substance thereof. CONSTITUTION:A polycrystal Si thin film having about 1000Angstrom thickness is deposited on a ground material of glass using thermal decomposition of SiH4 by vacuum CVD. Si ions are then implanted into the whole surface of the polycrystal Si thin film at about 110keV implantation energy to provide an amorphous thin film and form the amorphous Si film. A resist is then applied onto the amorphous Si film and a pattern in which holes having about 1mum diameter are arranged at a prescribed interval in the form of lattice points is formed. The resultant resist part is then masked to carry out the second Si ion implantation at about 40keV implantation energy and form a substrate having a region with a high Si atomic density. The resist mask is finally shaved and separated and the film is heat-treated at about 600 deg.C for about 100hr in N2 atmosphere to afford the objective Si crystal thin film having crystal grain boundaries arranged in the form of lattice at a prescribed interval with hardly any grain diameter distribution.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は、半導体薄膜の形成方法に係り、より詳細には
、たとえばTPT(薄膜トランジスタ)等の半導体装置
を高性能に作り得る、大粒径かつ粒騨位置の制御された
半導体薄膜の形成方法に関する。
Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a method of forming a semiconductor thin film, and more particularly, to a method for forming a semiconductor thin film, and more particularly, a method for forming a semiconductor thin film, and more specifically, a method for forming a semiconductor thin film with a large particle size that enables high performance production of semiconductor devices such as TPT (thin film transistor). The present invention also relates to a method for forming a semiconductor thin film in which grain anchor positions are controlled.

[従来の技術] 従来、大粒径の多結晶Si半導体薄膜形成に関する技術
としては、非晶質St薄膜を固相成長させ、大粒径の多
結晶St薄膜を形成し、薄膜トランジスタに供する技術
が報告されている(TNoguchi、 T、Ohsh
ima & T、Hayashi ; Polysil
iconFilms and Interfaces、
 Boston、 1987. Mater。
[Prior Art] Conventionally, as a technology for forming a polycrystalline Si semiconductor thin film with a large grain size, there is a technology in which an amorphous St thin film is grown in a solid phase to form a polycrystalline St thin film with a large grain size and used for a thin film transistor. It has been reported (TNoguchi, T., Ohsh
ima&T, Hayashi; Polysil
iconFilms and Interfaces,
Boston, 1987. Mater.

Res、 Sac、 5yllIip、 Proc、 
Vol、 IOJ p、293(Elsecier 5
cience Publfshing、 New Yo
rk。
Res, Sac, 5yllIip, Proc,
Vol, IOJ p, 293 (Elsecier 5
Science Publfshing, New Yo
rk.

19811 ))、  その詳細を以下に述べる。19811)), the details of which are described below.

この技術においては、まず、基板上に非晶質Si膜を形
成する。なお、非晶質St層の形成技術としては、多結
晶Si層にSiイオンを注入して非晶質化する方法、化
学気相法でS i H4を熱分解して非晶質Si[を形
成する方法、あるいは、電子ビーム蒸着法でStを室温
に保った基板上に堆積する方法等が知られている。
In this technique, first, an amorphous Si film is formed on a substrate. Note that the formation technology for the amorphous St layer includes a method of implanting Si ions into a polycrystalline Si layer to make it amorphous, and a method of thermally decomposing SiH4 using a chemical vapor method to form amorphous Si. A method of forming St, or a method of depositing St on a substrate kept at room temperature by electron beam evaporation is known.

その後、該非晶質St層をN2$囲気中、600℃で数
時間から数十時間熱処理を施すと、非晶質Si層中に結
晶核が発生し、熱処理時間とともにその大きさが増大し
、結晶粒が互いに衝突するまで成長し、そこに粒騨が形
成される。例えば、1000人はどのSiイオン注入に
よって作成された非晶質Si層は、600℃、100時
間のN2霊囲気中の熱処理によってその粒径は5μm程
にも成長する。
Thereafter, when the amorphous St layer is heat-treated at 600° C. for several hours to several tens of hours in an N2 atmosphere, crystal nuclei are generated in the amorphous Si layer, and their size increases with the heat treatment time. The grains grow until they collide with each other, forming grain anchors. For example, an amorphous Si layer created by implanting 1,000 Si ions grows to a grain size of about 5 μm by heat treatment in a N2 atmosphere at 600° C. for 100 hours.

かかる大きな粒径の多結晶Si層上に作成された薄膜ト
ランジスタのキャリア穆勤度は100clI12/■S
eCを越えるものが観測され、素子作成上きわめて有用
な粒径拡大方法である。
The carrier efficiency of a thin film transistor fabricated on a polycrystalline Si layer with such a large grain size is 100clI12/■S.
It has been observed that the particle size exceeds eC, and is an extremely useful method for increasing the particle size in device production.

〔発明が解決しようとする課題] しかし、前記従来例を実際に追試し、つぶさに検討する
と、以下の問題点が存在することを本発明者は解明した
[Problems to be Solved by the Invention] However, when the above-mentioned conventional example was actually repeated and examined in detail, the present inventors discovered that the following problems existed.

非晶質Si中の核形成はランダムな位置に発生し、核の
成長の後に粒同士が衝突して粒界が生ずるが、その粒界
位置も当然のことながらランダムな位置となり制御され
るものではない。事実、Siイオンの注入を行い、多結
晶Si層を非晶質化したのち600℃程度の熱処理を行
うと、最大5μmもの大粒径の多結晶層が得られるが、
その粒径分布は広く1μm〜5μmに分布しており、素
子作製上この分布は、素子特性のバラツキとなって表出
することになり、実用上多大の困難となる。たとえば、
チャンネル長10μmの電界効果型トランジスターを4
インチ基板の該大粒径多結晶Si層に作製した際には、
電子易動度は110cm’/v−secに対して±10
cm’/v−secのバラツキがあり、更にそのしきい
値は±0,5V以上のバラツキとなり、単結晶Si基板
上に作製したものに比べて著しく大きく、集積化して回
路を構成する上で大きな障害となる。
Nucleation in amorphous Si occurs at random positions, and after the growth of the nuclei, grains collide with each other to form grain boundaries, but the positions of these grain boundaries are naturally random and can be controlled. isn't it. In fact, if Si ions are implanted to make the polycrystalline Si layer amorphous and then heat treated at about 600°C, a polycrystalline layer with large grain sizes of up to 5 μm can be obtained.
The particle size distribution is broadly distributed in the range of 1 μm to 5 μm, and this distribution manifests itself as variations in device characteristics during device fabrication, which poses a great deal of practical difficulty. for example,
4 field effect transistors with a channel length of 10 μm
When fabricated on the large-grain polycrystalline Si layer of an inch substrate,
Electron mobility is ±10 for 110 cm'/v-sec
cm'/v-sec, and the threshold value has a variation of more than ±0.5V, which is significantly larger than that produced on a single crystal Si substrate, making it difficult to integrate and form a circuit. It becomes a big obstacle.

本発明は上記従来例の有する3つの問題点を解決するも
のであり、本発明の目的は固相再結晶化後の粒径分布を
低減させるために、固相中における核発生位置を制御し
、その結果、粒界位置が決定された、非晶質の下地材料
上へのSi結晶の半導体薄膜の形成方法を提供すること
にある。
The present invention solves the above three problems of the conventional example, and the purpose of the present invention is to control the position of nucleation in the solid phase in order to reduce the particle size distribution after solid phase recrystallization. As a result, it is an object of the present invention to provide a method for forming a semiconductor thin film of Si crystal on an amorphous base material in which grain boundary positions are determined.

[課題を解決するための手段] 本発明の半導体薄膜の形成方法は、非晶質Si膜の所望
の位置に、単一の核より結晶成長するに充分微小な領域
であって、該領域とは異る該非晶質Si膜におけるSt
原子密度よりもSt原子密度の高い領域を設け、 前記領域には単一の核より成長した結晶体が形成され該
領域とは異なる前記非晶質Si膜では核が発生しない温
度で熱処理を行い、 前記結晶体を基に前記非晶質Si膜を固相にて結晶成長
させることを特徴とする。
[Means for Solving the Problems] The method for forming a semiconductor thin film of the present invention provides a method for forming a semiconductor thin film in a desired position of an amorphous Si film, which is a sufficiently minute region for crystal growth from a single nucleus; is different from St in the amorphous Si film.
A region is provided where the St atom density is higher than the St atom density, and a crystalline substance grown from a single nucleus is formed in the region, and heat treatment is performed at a temperature at which no nuclei are generated in the amorphous Si film, which is different from the region. , characterized in that the amorphous Si film is crystal-grown in a solid phase based on the crystalline substance.

〔作用〕[Effect]

以下に本発明の作用・構成の詳細を本発明をなすに際し
得た知見とともに説明する。
The details of the operation and structure of the present invention will be explained below along with the knowledge obtained in making the present invention.

本発明のポイントは如何に固相中で結晶体の成長する位
置を制御するかにある。すなわち、非晶質Si膜におい
て、核を特定位置に優先的に発生させ、他の領域の核発
生を抑制するかにある。
The key point of the present invention is how to control the growing position of crystals in the solid phase. That is, in an amorphous Si film, nuclei are generated preferentially in a specific position, and generation of nuclei in other areas is suppressed.

本発明者は、たとえば5iftからなる下地材料上に多
結晶Si膜を堆積させ、その後Siイオンを注入し多結
晶St層を非晶質化した後、熱処理する際に、その結晶
核発生温度(結晶化温度)がそのイオン注入エネルギー
に依存するという現象を発見した。
The present inventor deposited a polycrystalline Si film on a base material made of, for example, 5ift, and then implanted Si ions to make the polycrystalline St layer amorphous. We discovered a phenomenon in which the crystallization temperature (crystallization temperature) depends on the ion implantation energy.

そこで、結晶核発生温度が何故にイオン注入エネルギー
に依存するかの解明を行フたとこる次の事項が判明した
。以下にその詳細を述べる。
Therefore, we investigated why the crystal nucleation temperature depends on the ion implantation energy and discovered the following. The details are described below.

注入エネルギーを変化させると、非晶質化した後のSi
層(非晶賀りt層)中において、注入されたSiイオン
の分布は変化し、また、その空孔子の分布もそれによっ
て変化することがまずわかった。
By changing the implantation energy, the Si after becoming amorphous
It was first found that the distribution of implanted Si ions changes in the layer (amorphous t-layer), and that the distribution of vacancies also changes accordingly.

核発生の催構はSi原子の非晶質相から結晶相への相転
移、あるいは結晶質相/非晶質相界面の移動速度によっ
て律速さねる。その結晶質相/非晶質相界面の移動速度
は、Si原子の界面を移動する移動速度によって決定さ
れ、移動速度は空孔子密度とSi原子密度に強く依存し
、現象的には結晶核発生温度(結晶化温度)が変化する
The mechanism of nucleation is determined by the phase transition of Si atoms from an amorphous phase to a crystalline phase, or the rate of movement of the crystalline phase/amorphous phase interface. The movement speed of the crystalline phase/amorphous phase interface is determined by the movement speed of Si atoms across the interface, and the movement speed strongly depends on the vacancy density and the Si atom density. The temperature (crystallization temperature) changes.

第1図に、Siイオンの注入エネルギーと結晶化温度の
相関を示す。この時の条件は以下のとおりである。
FIG. 1 shows the correlation between Si ion implantation energy and crystallization temperature. The conditions at this time are as follows.

Stイオンの注入量:臨界注入量(約1015cm−2
)を越えて一定 注入層:1000人の多結晶St層 熱処理時間=20時間 St”イオンの投影飛程(注入エネルギーで制御): ■注入エネルギー40kev ;注入層中央部■注入エ
ネルギー70kev;注入層と下地材料との界面 40kevで注入した場合、注入イオンおよび生成空孔
子は、全て注入層中に存在するが、70kevの場合に
はほとんど全ての空孔子は注入層内に分布しはするもの
の注入されたSi原子は約半分しか注入層にはなく、S
i原子密度は前者の方が高く、より密な非晶質構造とな
る。
St ion implantation amount: Critical implantation amount (approximately 1015 cm-2
) Constant implantation layer: Polycrystalline St layer of 1000 people Heat treatment time = 20 hours Projected range of St" ions (controlled by implantation energy): ■Implantation energy 40kev; center of implantation layer ■Implementation energy 70kev; implantation layer When the implantation is performed at the interface between the base material and the base material at 40 keV, all of the implanted ions and generated vacancies are present in the implanted layer, but when the implantation is at 70 keV, almost all the vacancies are distributed within the implanted layer. Only about half of the Si atoms are in the injection layer, and S
The i-atom density is higher in the former, resulting in a denser amorphous structure.

一般にSi原子の非晶質相から結晶質相の穆勤は空孔子
息を介して移動する。したがって、移動すべきSi原子
の密度の差は、その結晶化温度に影響し、膜中央に投影
飛程をもつ40kevの注入層の方が50℃程結晶化温
度が低くなる。
In general, Si atoms from the amorphous phase to the crystalline phase migrate via vacancy sons. Therefore, the difference in the density of the Si atoms to be moved affects the crystallization temperature, and the crystallization temperature is about 50° C. lower for the 40 keV implanted layer with the projected range at the center of the film.

結局、注入イオンのエネルギーの差は空孔子密度とSi
原子密度の差としてあられれ、SL原子の密度差がある
と結晶化温度に変化が生ずることを本発明者は解明した
のである。
In the end, the difference in the energy of the implanted ions is the vacancy density and the Si
The present inventors have discovered that crystallization temperature changes when there is a difference in the density of SL atoms, which occurs as a difference in atomic density.

以上の現象を利用し核発生位置の制御を行う。The above phenomena are used to control the location of nuclear generation.

第2図に示すように、非晶質Si膜中にSi原子密度の
高く、かつ、充分空孔子濃度の高い領域を局所的に形成
する(A)。
As shown in FIG. 2, regions with a high Si atom density and a sufficiently high vacancy concentration are locally formed in the amorphous Si film (A).

非晶質5iFAの形成は、たとえば下地材料上の多結晶
Si膜にイオンを注入することにより行えばよい。さら
に、このイオン注入は下地材料と多結晶Si層との界面
に投影飛程が来るように高エネルギーで行えば、層全体
を容易に非晶質Si層にすることができる。
The amorphous 5iFA may be formed, for example, by implanting ions into a polycrystalline Si film on a base material. Furthermore, if this ion implantation is performed with high energy so that the projected range is at the interface between the underlying material and the polycrystalline Si layer, the entire layer can be easily made into an amorphous Si layer.

非晶質5tliへSi原子密度の領域を形成するために
は、たとえば、マスキング技術等を用いてそのSi原子
密度の高い領域となるべき領域のみにイオン注入を行え
ばよい。この際の注入エネルギーは、膜厚方向中央部に
投影飛程が来るように低エネルギーで行えば非晶質Si
層のSi原子密度の高い領域の表面をさらに高Si原子
密度とすることができるので結晶化温度を低くすること
ができる。
In order to form a region with a high Si atom density in the amorphous 5tli, ions may be implanted only into the region that is to become a region with a high Si atom density using, for example, a masking technique. At this time, if the implantation energy is low so that the projected range is at the center in the film thickness direction, the amorphous Si
Since the surface of the region of the layer having a high Si atom density can be made to have an even higher Si atom density, the crystallization temperature can be lowered.

この薄膜を、Si原子密度の低い領域には核発生せず、
Sii子密度の高い領域にのみ核発生する温度で熱処理
する。その温度が何度であるかはあらかじめ実験等によ
り求めておけばよい。たとえは、第1図に示すように、
80KeVでSiイオン注入を行い、さらに、部分的に
40KeVで非晶質化した場合は、620℃、10時間
、N2雰囲気中で熱処理すればよい。
This thin film does not generate nuclei in areas with low Si atom density,
Heat treatment is performed at a temperature that allows nucleation to occur only in regions with high Sii ion density. The temperature may be determined in advance through experiments or the like. For example, as shown in Figure 1,
When Si ion implantation is performed at 80 KeV and further amorphousization is performed partially at 40 KeV, heat treatment may be performed at 620° C. for 10 hours in an N2 atmosphere.

Siの結晶核は、Si原子密度が高い領域より発生し、
Si原子密度が低い領域まで結晶は単一のドメインを維
持して成長する。これは、−塵発生した―晶核が成長す
る活性化エネルギーは、表面エネルギーを乗り越えて核
発生するための活性化エネルギーより低いためである。
Si crystal nuclei are generated from regions with high Si atom density,
The crystal grows while maintaining a single domain up to a region where the Si atom density is low. This is because the activation energy for the growth of dust-generated crystal nuclei is lower than the activation energy for overcoming the surface energy to generate nuclei.

成長が継続され、最終的には隣接するSi原子密度が高
い領域より核発生し、成長した結晶と中開位置で衝突し
、そこに粒界が形成される。
The growth continues, and eventually nuclei are generated from adjacent regions with a high Si atom density, collide with the grown crystal at an open position, and a grain boundary is formed there.

以上のようにして、非晶質Si中の核発生位置を制御し
て粒界位置の指定されたSt結晶薄膜が形成される(B
)。
As described above, an St crystal thin film with specified grain boundary positions is formed by controlling the nucleation position in amorphous Si (B
).

この時結晶粒径は、Si原子密度の高い領域の間隔に等
しくなり、任意に決めることができ、その粒径のバラツ
キ極めて少ない。
At this time, the crystal grain size is equal to the interval between regions with high Si atom density, and can be arbitrarily determined, and the variation in the grain size is extremely small.

[実施例] 4インチのガラスからなる下地材料上に減圧化学気相法
(CVD)によりS i H,の熱分解で多結晶Si薄
膜を1000人堆積した。形成温度は620℃とした。
[Example] 1000 polycrystalline Si thin films were deposited by thermal decomposition of SiH by low pressure chemical vapor deposition (CVD) on a base material made of 4-inch glass. The formation temperature was 620°C.

堆積した多結晶Si薄膜の粒径は500Å以下であった
The grain size of the deposited polycrystalline Si thin film was less than 500 Å.

次に、Siイオン注入を2回行った。まず、多結晶Si
薄膜の全面に31イオンを、注入量5×101Sc m
−’、注入エネルギー110keyで注入し、多結晶S
t薄膜全体を非晶質化し、非晶質Si膜を形成した。
Next, Si ion implantation was performed twice. First, polycrystalline Si
31 ions were implanted on the entire surface of the thin film at an implantation dose of 5×101Sc m
-', implanted with an implantation energy of 110 keys, polycrystalline S
The entire thin film was made amorphous to form an amorphous Si film.

更に非晶XSi膜上にレジストを塗付し、通常のりソグ
ラフイを用いて1μm径の穴を、5μm、10μm間隔
に格子点状に配した2種類のパターンを形成した。該バ
ターニングされたレジストをマスクにして2回目のSi
イオン注入を行った。注入量は1回目と同じ<5X10
15am−”、注入エネルギーは一40keyとし、S
t原子密度の高い領域を有する基体を形成した。
Further, a resist was applied onto the amorphous XSi film, and two types of patterns were formed using ordinary glue lithography, in which holes with a diameter of 1 μm were arranged in the form of lattice points at intervals of 5 μm and 10 μm. A second Si film is applied using the patterned resist as a mask.
Ion implantation was performed. The injection volume is the same as the first time <5X10
15 am-'', the injection energy is -40 key, and S
A substrate having a region with high t-atom density was formed.

レジストマスクを剥離した後、N、雰囲気中において6
00℃で100時間の熱処理を行ったところ、1000
人の平坦な膜のまま、結晶粒界がほぼ5μm110μm
間隔の格子状に整列し、粒径の分布は平均5μm、10
μmに対して、±1μmであることが透過電子顕1敗鏡
観察によって判明した。
After peeling off the resist mask, 6
When heat treated at 00℃ for 100 hours, 1000
Grain boundaries are approximately 5μm to 110μm, as is the flat human film.
They are arranged in a lattice shape with intervals, and the particle size distribution is an average of 5 μm and 10
It was found by observation using a transmission electron microscope that the difference was ±1 μm with respect to μm.

以上のようにして作製した、5μm±1μmの粒径分布
をもつSt薄膜に、通常のICプロセスを用いてチャン
ネル長3μmの電界効果トランジスターを100個作製
したところ、電子易動度200±5cm2/v−sec
、 しきい値のバラツキは±0.2Vであった。トラン
ジスタのチャネル部分には、粒界が存在しないように配
置することが可能なため(あらかじめ粒界位置が判って
いる)素子特性の高性能化、狭分布が実現された。
When 100 field effect transistors with a channel length of 3 μm were fabricated using a normal IC process on the St thin film with a particle size distribution of 5 μm±1 μm prepared as described above, the electron mobility was 200±5 cm2/ v-sec
, The variation in threshold value was ±0.2V. Since it is possible to arrange the channel portion of the transistor so that no grain boundaries exist (grain boundary positions are known in advance), high performance and narrow distribution of device characteristics have been achieved.

なお、以上の説明では多結晶Si膜を非晶質化した非晶
質Si@の場合を例としてあげたが、たとえば、減圧C
VD法により550℃で、あるいはグロー放電法による
水素を含んだ非晶質Si膜を出発材料としても同等の効
果がある。この場合、全体を深くイオン注入して非晶質
化する必要がない。また、堆積ままの非晶質Si膜は7
00℃まで結晶化しないことを確認した。イオン注入は
集束イオン注入法を用いマスクレスにて行っても良い。
In addition, in the above explanation, the case of amorphous Si@, which is amorphous polycrystalline Si film, was given as an example.
The same effect can be obtained by using an amorphous Si film containing hydrogen at 550° C. by VD method or by glow discharge method as a starting material. In this case, there is no need to deeply implant ions into the entire structure to make it amorphous. In addition, the as-deposited amorphous Si film is 7
It was confirmed that crystallization did not occur up to 00°C. Ion implantation may be performed without a mask using a focused ion implantation method.

[発明の効果] 局所的に非晶質Si中にSi注入エネルギーを変化させ
空孔子濃度とSL原子高濃度領域を形成することによっ
て、平坦、薄膜のまま粒界位置制御され、粒径分布の少
ないSt結晶薄膜が形成された。あらかじめ粒界位置を
設定できるため、デバイスの性能に悪影響を与える粒界
を回避してデバイスを作製できるため、素子特性の高性
能化、バラツキの狭小化が可能となった。
[Effect of the invention] By locally changing the Si implantation energy in amorphous Si to form a region with high vacancy concentration and SL atoms, the grain boundary position can be controlled while maintaining a flat and thin film, and the grain size distribution can be changed. A small amount of St crystal thin film was formed. Since grain boundary positions can be set in advance, devices can be fabricated while avoiding grain boundaries that adversely affect device performance, making it possible to improve the performance of device characteristics and narrow variations.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はイオン注入エネルギと結晶化温度との関係を示
すグラフである。第2図は本発明の実施態様例を示す概
念図である。
FIG. 1 is a graph showing the relationship between ion implantation energy and crystallization temperature. FIG. 2 is a conceptual diagram showing an embodiment of the present invention.

Claims (5)

【特許請求の範囲】[Claims] (1)非晶質Si膜の所望の位置に、単一の核より結晶
成長するに充分微小な領域であって、該領域とは異る該
非晶質Si膜におけるSi原子密度よりもSi原子密度
の高い領域を設け、 前記領域には単一の核より成長した結晶体が形成され該
領域とは異なる前記非晶質Si膜では核が発生しない温
度で熱処理を行い、 前記結晶体を基に前記非晶質Si膜を固相にて結晶成長
させることを特徴とする半導体薄膜の形成方法。
(1) A region at a desired position of the amorphous Si film that is sufficiently small to allow crystal growth from a single nucleus, and which is smaller than the Si atom density in the amorphous Si film that is different from the region. A high-density region is provided, and a crystalline material grown from a single nucleus is formed in the region, and heat treatment is performed at a temperature at which no nuclei are generated in the amorphous Si film, which is different from the region, and the crystalline material is formed as a base. A method for forming a semiconductor thin film, characterized in that the amorphous Si film is crystal-grown in a solid phase.
(2)前記Si原子密度の高い領域を有する前記非晶質
Si膜は、多結晶Si膜全面にイオン注入を行うことに
より多結晶Si膜を非晶質化し、次いで前記のみにイオ
ン注入を行って形成することを特徴とする請求項1記載
の半導体薄膜の形成方法。
(2) The amorphous Si film having the region with high Si atom density is made by implanting ions into the entire surface of the polycrystalline Si film to make the polycrystalline Si film amorphous, and then implanting ions only into the above region. 2. The method of forming a semiconductor thin film according to claim 1, wherein the semiconductor thin film is formed by using a method of forming a semiconductor thin film.
(3)非晶質Si膜が基体上に形成され、1回目のイオ
ン注入は、基体と非晶質Si膜との界面に打込イオン濃
度が極大となる投影飛程が来るように高エネルギーで行
い、2回目のイオン注入は局所的に非晶質Si膜の膜厚
方向中央部に投影飛程が来るように低エネルギーで行う
ことを特徴とする請求項2記載の半導体薄膜の形成方法
(3) An amorphous Si film is formed on the substrate, and the first ion implantation is performed with high energy so that the projected range where the implanted ion concentration is maximum is at the interface between the substrate and the amorphous Si film. 3. The method of forming a semiconductor thin film according to claim 2, wherein the second ion implantation is performed at low energy so that the projected range is locally in the center of the amorphous Si film in the film thickness direction. .
(4)前記Si原子密度の高い領域を単数設ける請求項
1乃至請求項3のいずれか1項に記載の半導体薄膜の形
成方法。
(4) The method for forming a semiconductor thin film according to any one of claims 1 to 3, wherein a single region having a high Si atom density is provided.
(5)前記Si原子密度の高い領域を複数設ける請求項
1乃至請求項3のいずれか1項に記載の半導体薄膜の形
成方法。
(5) The method for forming a semiconductor thin film according to any one of claims 1 to 3, wherein a plurality of regions having a high Si atom density are provided.
JP1081102A 1989-03-31 1989-03-31 Method of forming semiconductor thin film Pending JPH02258690A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1081102A JPH02258690A (en) 1989-03-31 1989-03-31 Method of forming semiconductor thin film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1081102A JPH02258690A (en) 1989-03-31 1989-03-31 Method of forming semiconductor thin film

Publications (1)

Publication Number Publication Date
JPH02258690A true JPH02258690A (en) 1990-10-19

Family

ID=13737023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1081102A Pending JPH02258690A (en) 1989-03-31 1989-03-31 Method of forming semiconductor thin film

Country Status (1)

Country Link
JP (1) JPH02258690A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL9301811A (en) * 1992-10-28 1994-05-16 Ryoden Semiconductor Syst Eng Thin film field effect transistor and method of manufacturing it, as well as a semiconductor element provided therewith.
US5658381A (en) * 1995-05-11 1997-08-19 Micron Technology, Inc. Method to form hemispherical grain (HSG) silicon by implant seeding followed by vacuum anneal

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL9301811A (en) * 1992-10-28 1994-05-16 Ryoden Semiconductor Syst Eng Thin film field effect transistor and method of manufacturing it, as well as a semiconductor element provided therewith.
US5514880A (en) * 1992-10-28 1996-05-07 Mitsubishi Denki Kabushiki Kaisha Field effect thin-film transistor for an SRAM with reduced standby current
US5736438A (en) * 1992-10-28 1998-04-07 Mitsubishi Denki Kabushiki Kaisha Field effect thin-film transistor and method of manufacturing the same as well as semiconductor device provided with the same
US5658381A (en) * 1995-05-11 1997-08-19 Micron Technology, Inc. Method to form hemispherical grain (HSG) silicon by implant seeding followed by vacuum anneal

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