JPH02260633A - Dry etching of amorhous silicon device - Google Patents

Abstract

PURPOSE:To recover the characteristics by a method wherein an amorphous Si device bearing deteriorated electrical characteristics is annealed at 80-300 deg.C for 10-60 minutes. CONSTITUTION:During the manufacturing process of a thin film electronic device comprising amorphous Si as a material, dryetching process is performed for the process taking fine shape. The said device is exposed to etching plasma, etching beams, etc., and dangling bond (free bond of Si) is increased to deteriorate the electrical characteristics thereof. This deteriorated amorphous Si device is low-temperature annealed at 80-300 deg.C in the atmospheric air at least for 10-60 minutes. Through these procedures, the increased dangling bond can be removed without destructing the Si-H coupling so that the electrical characteristics of the defective channel part of the amorphous Si may be enhanced so effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for dry etching amorphous silicon. To be more specific, the present invention relates to a dry etching process for the purpose of microfabrication in the production of thin film electronic devices such as diodes and transistors made of amorphous silicon. This invention relates to a dry etching method for amorphous silicon, which restores the characteristics of the aforementioned diodes and transistors whose electrical characteristics have deteriorated due to etching, and which does not impair the electrical characteristics even after microfabrication, which is essential for device fabrication, is performed. It is something.

(Prior art) In semiconductor electronic materials represented by single crystal silicon,
The process of forming elements with electrical functions, such as diodes and transistors, is called the device fabrication process.

In this device fabrication process, the process of processing the shape of a semiconductor portion such as single crystal silicon or a wiring metal portion such as A, Q, Cr, etc. is generally referred to as micro-shape processing.

In this micro-shape processing, the means for removing the material under the portion not covered by the patterned photoresist can be roughly divided into two methods: (1) Wet etching method and (2) Dry etching method.

Wet etching is a method that uses a liquid etching agent such as acid or alkali to corrode and remove the underlying material in the area where the photoresist is removed, that is, the area where the photoresist is not attached, and has been widely used in the past. Generally, corrosion caused by such etching agents is isodirectional (etching progresses at the same speed in all directions).
However, this method is inappropriate when the pattern is very fine or when the cut edge of the patterning section is desired to be vertical.

On the other hand, the dry etching method is a new process for solving the problems of the wet etching method as described above. In a typical method, a corrosive gas such as CF4 or CCΩ4 is placed in a container under low pressure, and a high-frequency discharge is generated between these voltages, usually using parallel plate electrodes, to generate plasma. let Since this plasma contains a large amount of fluorine active species, chlorine active species, etc. that actively react with the underlying material, the underlying material is etched in the photoresist removed area. It is known that anisotropic etching is possible by appropriately selecting the bias between the electrodes, the type of gas, the gas pressure, etc.
In particular, this anisotropic etching is called RIE (reactive ion etching). Other anisotropic dry etching methods include ion beam etching, in which ions or atoms of an inert gas are physically or mechanically knocked out of the substrate, and reactive gas etching. Methods such as reactive ion beam etching, in which a substrate is irradiated with ions or atoms, are also known.

According to dry etching such as RIE, the underlying material can be removed finely and vertically only in the photoresist removed portion, and there is no problem of "undercut" as seen in wet etching. Therefore, it becomes possible to process extremely fine or complicated patterns.

Figures 3a-3c show typical single crystal silicon patterning shapes by wet etching and dry etching leg methods. In the dry etching patterning shown in FIG. 3b, the single crystal silicon 2 directly under the photoresist 1 shown in FIG. 3a is vertically patterned, whereas the wet etching patterning shown in FIG. 3C is patterning. It can be seen that the single crystal silicon 2 is etched in the same direction, and that an undercut 4 is observed in the portion of the single crystal silicon 2 directly below the photoresist 1.

Furthermore, since the dry etching method does not use a liquid etching agent such as acid or alkali, it is a clean and compact process and is easy to maintain. In addition,
Materials that are difficult to use with wet etching (e.g. 5L3N)
Etching 4) can also be achieved by using a dry etching method. For this reason, dry etching is widely used in today's semiconductor processes, including single crystal silicon.

However, since this dry etching method uses highly active active species as mentioned above, the number of dangling bonds (dangling bonds in silicon) on the etched surface increases, resulting in a decrease in the number of dangling bonds (unbonded bonds in silicon) on the etching surface, resulting in a decrease in the number of dangling bonds (dangling bonds in silicon) on the etching surface. The deterioration of the electrical properties of these materials has become a major problem. This is because the increased number of dangling bonds on the etched surface makes the etched surface appear more like a conductive channel. This situation is shown in Section 4a.
As shown in the figure. Here, metal 3-p-type amorphous silicon 7-i-type amorphous silicon 6-n-type amorphous silicon 5
- An amorphous silicon diode formed in the order of metal 3 is explained as an example, and it is illustrated that a defective (conductive) channel portion 9 is formed on the etched surface of the diode by the dry etching method.

As a result, off-state current increases in electronic devices such as diodes and transistors, resulting in so-called "leaky" devices, which poses a major problem in device fabrication.

In order to solve these problems in the dry etching method, two methods have been proposed at present. One method is to anneal the deteriorated device in a N2 atmosphere or a vacuum atmosphere at a temperature of 500° C. or higher. This annealing typically takes place in a furnace for several hours. It is widely known that annealing reduces the dangling bonds in the defective channel region as described above, reduces the off-current of leaky devices, and improves electrical characteristics. It is often used in device manufacturing processes using

Another method is to remove the channel portion, which has deteriorated due to an increase in dangling bonds, by wet etching or dry etching. This channel part has naturally been degraded by the etching process, and is naturally exposed after being degraded, so following the normal etching process (that is, the etching process that causes deterioration), Isotropic etching is performed to remove portions. The shape of the amorphous silicon diode with the defective channel portion 9 removed in this way is shown in FIG. 4b.

However, when the material is amorphous silicon, these methods are difficult to apply because of the following fatal problems.

First, there is the annealing method, and as is well known, amorphous silicon is formed into a low-temperature non-equilibrium film, which allows a large amount of hydrogen to be deposited at 5i.
-H, and this bond significantly improves the electrical properties of amorphous silicon (for example, reduces the localized level density).

However, this 5t-H bond is sensitive to heat and is
When annealing with hydrogen, the bonds are usually destroyed and hydrogen is released, which causes a problem of significant deterioration of the electrical characteristics.

Next, the deteriorated channel portion of the device is removed by etching, but this method also involves some difficult problems. First of all, since the deteriorated channel portion was originally generated during the dry etching process, no matter how much etching method is selected that causes less damage, it is necessary to cleanly remove only the damaged channel portion and use the new device etching surface that remains. ``Ideal isotropic etching'' that leaves no damage is actually extremely difficult. Furthermore, since this isotropic etching process is very delicate, it is difficult to control and has poor reproducibility. Therefore, the yield is low and
Even within the same substrate, if the sizes of the etched areas become uneven, variations in characteristics will occur between devices. In addition, because a part of the device that was originally supposed to be driven is removed as a defective channel part, the dimensions of the device planned at the time of design are reduced, causing problems such as a reduction in on-state current in the case of a diode, for example. .

For the above reasons, in devices using amorphous silicon, no effective method has yet been found to improve the amorphous silicon channel formed by dry etching. Freedom in design and manufacturing processes is severely restricted.

[1] Taking the inverted staggered amorphous silicon thin film transistor shown in FIG. 5a as an example, after forming the gate electrode 15 on the substrate 8, the insulating layer 14-n-amorphous silicon 13-n+ amorphous silicon 12-source electrode 10 and drain electrode 11 are formed, and then,
The source electrode 10, the drain electrode 11, and the n+ amorphous silicon 12 are etched and patterned from above, but if the n+ amorphous silicon 12 is dry etched, the n- amorphous silicon 13 below is etched. A defective channel is formed on the surface of the transistor, and as a result, the off-state current of the transistor increases. On the substrate 8, a semiconductor layer (in this example, n+ amorphous silicon 12-n-amorphous silicon 13-n+amorphous silicon 1
2) is sandwiched between the layers, an insulating layer 14 is placed in contact with the side surface of the layered structure, and a gate electrode 15 is placed outside of the insulating layer 14, and the channel portion is vertical, that is, in the film thickness direction. It has been proposed and prototype production has begun, but even though vertical patterning by dry etching is essential for this device, the problem of defective channels cannot be avoided, so even if a design can be made, it is extremely difficult to realize it. The current situation is that it is delayed.

(Problems to be Solved by the Invention) Therefore, an object of the present invention is to provide a novel dry etching method that solves the above-mentioned problems. The present invention also provides a dry etching process for the purpose of microfabrication in the manufacture of thin film electronic devices made of amorphous silicon. It is an object of the present invention to provide a dry etching method for amorphous silicon in which the characteristics are restored again and the electrical characteristics are not impaired even after microfabrication, which is essential for device fabrication, is performed. The present invention further provides annealing treatment to eliminate dangling bonds that occur when thin-film electronic devices such as diodes and transistors made of amorphous silicon are manufactured using a dry etching process, without destroying 5i-H bonds. The purpose is to remove it.

(Means for Solving the Problems) The present invention is directed to a dry etching process for the purpose of microfabrication in the production of thin film electronic devices made of amorphous silicon. The amorphous silicon device dry-etched by the activated species is subjected to a low-temperature annealing treatment at 80 to 300° C. for at least 10 to 60 minutes in the atmosphere.

(Function) The dry etching method of the present invention simply etches amorphous silicon devices with deteriorated electrical characteristics at 80 to 300°C for 1 time.
It is characterized in that the characteristics can be recovered by annealing treatment at a very low temperature and for a short time of 0 to 60 minutes, and it is very simple because it can be annealed in the atmosphere.

The reason why the temperature is limited to the range of 80 to 300°C as mentioned above is that at temperatures below 80°C, the annealing process takes place.
Even if it is maintained for a long period of time, there is hardly any effect of property recovery.On the other hand, at temperatures exceeding 300°C, the 5i-H bonds in amorphous silicon are destroyed and dangling bonds are formed. This is because it will increase. In addition, the annealing time may be shorter as the annealing temperature is higher in the shell, and the lower the annealing temperature is, the longer the annealing time is required.
Even at a temperature of 30 minutes, the properties can be sufficiently recovered. Of course, it is of course possible to carry out annealing treatment for longer than the time mentioned here.

In addition, in the present invention, since the annealing process is performed at low temperature for a short time, compared to the conventional method of removing defective channel portions by isodirectional wet etching process,
It is very simple and has good reproducibility. In addition, the present invention has the advantage of not changing the shape of devices formed by dry etching.

As described above, the present invention applies a low-temperature, short-time annealing treatment in the atmosphere, which has not been attempted before, to improve the electrical characteristics of a defective amorphous silicon channel region, and has fully demonstrated its effectiveness. It has great significance.

(Example) Examples of the present invention will be described below.

FIG. 1 shows the increase in dangling bonds on the etched surface of amorphous silicon due to dry etching, based on ESR (electron spin resonance) measurement results. In the figure, the size of the waveform peak on the sine wave appearing at 3.31 [kOel on the horizontal axis] corresponds to the number of dangling bonds. In addition, in this experiment, 20 mm x 20
I-type amorphous silicon is deposited on a quartz glass substrate of 80 mm.
008 deposited material is used as a sample.

As is clear from FIG. 1, the signal representing the dangling bonds for the deposited sample (upper part of the diagram) is very small and is not detected as an ESR waveform peak.

This is the detection limit of the ESR device used.
This means that the number of dangling bonds is much smaller than that of Cm-3.

Next, this sample surface was dry etched with CF4 (
E of the sample after etching about 300OA with RI E)
The SR signal is shown in the middle part of FIG. It can be seen here that the number of dangling bonds increased dramatically due to dry etching. Furthermore, when this sample is annealed in the air at 90°C for 20 minutes as in one embodiment of the method of the present invention, the number of dangling bonds decreases again, as shown in the lower part of Fig. It can be seen that the defective channel portion has been improved to the same extent as the sample.

Next, an example will be shown in which the present invention is applied to the formation of an actual amorphous silicon diode having a structure as shown in FIG. 4a.

First, as shown in FIG. 4a, the diode is made by placing 2,000 layers of metal 3 (Cr), 300 layers of p-type amorphous silicon 7, and 600 layers of i-type amorphous silicon 6 on a glass substrate 8 from the bottom.
0A, n-type amorphous silicon 5 3008, metal 3 (IT
100 μm x 125
Dry etching (RI) with CF4 to a size of μm
It was formed by patterning in E).

The voltage-current characteristics of this diode are shown in FIG. Second
In the figure, the forward characteristics of the diode are shown by black circles (.), and the reverse characteristics of the diode after dry etching are shown by squares (b). As is clear from this figure, the reverse direction characteristics are "leaky" due to dry etching, so the rectification ratio is 106, which is not good.

On the other hand, when this diode is subjected to low-temperature annealing in the air at 90°C for 20 minutes as in one embodiment of the present invention, the reverse characteristics are significantly improved, as shown by the white circle (0) in Figure 2. Ta. This means that the rectification ratio has also been improved to about 108.

(Effects of the Invention) As described above, the present invention solves the problem of formation of defective channels on the etched surface of amorphous silicon in the dry etching process, which has been a problem in conventional amorphous silicon devices. The present invention is a very simple method of short-time annealing treatment at a low temperature in the atmosphere, so it can be applied to any amorphous silicon device, and the necessary equipment is a low-temperature atmospheric annealing furnace. and low cost. Moreover, according to the present invention, the electrical characteristics before dry etching can be restored without changing the shape of the defective channel portion at all, so there is greater freedom in the structural design and manufacturing process of future amorphous silicon devices. The result is a marked improvement.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the increase in dangling bonds on the amorphous silicon dry etching surface and the effect of reducing dangling bonds by the present invention using ESR measurement results. Figures 3a to 3c show typical single-crystal silicon bettering obtained by conventional wet etching and dry etching. FIG. 4a-b is a schematic cross-sectional view showing the shape of a defective channel in an amorphous silicon diode formed by a conventional dry etching method and how the channel is removed by isotropic etching. FIG. 1B is a cross-sectional view showing typical structures of an inverted staggered amorphous silicon thin film transistor and an amorphous silicon vertical transistor. 1... Photoresist, 2... Single crystal silicon,
3...metal, 4...undercut, 5...n
type amorphous silicon, 6... i-type amorphous silicon, 7... p-type amorphous silicon, 8... substrate, 9...
・Defective (conductive) channel part, 10... Source, 1
DESCRIPTION OF SYMBOLS 1... Drain, 12... n+ amorphous silicon, 13... n- amorphous silicon, 14... insulating layer, 15... gate. Figure 2 - Cell [V Figure 3 (b) (C Figure 4 Figure 5 (a) (a) (b) (b)

Claims (1)

[Claims] In a dry etching process for the purpose of microfabrication in the production of thin film electronic devices made of amorphous silicon, the amorphous silicon is dry etched using active species generated in a gas phase after patterning a photoresist. The device was placed in the atmosphere for 80-3
1. A dry etching method for an amorphous silicon device, comprising performing a low-temperature annealing treatment at 00° C. for at least 10 minutes to 60 minutes.