JPH02260845A - ATM cell multiplexer - Google Patents
ATM cell multiplexerInfo
- Publication number
- JPH02260845A JPH02260845A JP1078471A JP7847189A JPH02260845A JP H02260845 A JPH02260845 A JP H02260845A JP 1078471 A JP1078471 A JP 1078471A JP 7847189 A JP7847189 A JP 7847189A JP H02260845 A JPH02260845 A JP H02260845A
- Authority
- JP
- Japan
- Prior art keywords
- cell
- circuit
- storage circuit
- priority
- cell storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Time-Division Multiplex Systems (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、非同期伝送モード(以下、ATM)の送信装
置を複数台収容し、各送信装置からのセル状とし次デー
タを多重化のうえ送信するATMセル多重化装置に関す
るものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention accommodates a plurality of asynchronous transmission mode (hereinafter referred to as ATM) transmitting devices, and multiplexes the next data in a cell form from each transmitting device. This relates to an ATM cell multiplexing device for transmission.
従来においては、パケット状としたデータを多重化する
パケット多重化装置が用いられており、これには、マイ
クロプロセッサにより構成したパケット処理制御装置が
設けてアリ、ソフトウェア処理によって各パケットの優
先度を判定し、この判定に基づいて各パケットの多重化
処理を行なうものとなっている。Conventionally, a packet multiplexing device has been used to multiplex data in the form of packets, and this device is equipped with a packet processing control device composed of a microprocessor, and the priority of each packet is determined by software processing. Based on this determination, each packet is multiplexed.
しかし、マイクロプロセッサを用いるパケット処理制御
装置では、これの処理速度がマイクロプロセッサの処理
能力により制約され、より高速のATM方式においては
、マイクロプロセッサの処理能力が不足し、ATMセル
多重化装置を実現することのできない問題を生じている
。However, in a packet processing control device using a microprocessor, the processing speed is limited by the processing capacity of the microprocessor, and in higher-speed ATM systems, the processing capacity of the microprocessor is insufficient, and an ATM cell multiplexing device is realized. This is causing a problem that cannot be resolved.
前述の課題を解決する几め、本発明はりぎの手段により
構成するものとなっている。In order to solve the above-mentioned problems, the present invention is constructed by the following means.
す々わち、セルの多重化を行々う多重化装置において、
収容する各送信装置と対応して設けたセル蓄積回路と、
このセル蓄積回路毎に設けられ対応するセル蓄積回路に
蓄積し次セルの種別を識別するセル識別回路と、これら
各セル識別回路の識別出力に応じて優先度を判断し最優
先のセルを蓄積したセル蓄積回路に対して蓄積内容の送
出を指令する優先制御回路とを備え友ものである。In other words, in a multiplexer that multiplexes cells,
a cell storage circuit provided corresponding to each transmitting device to be accommodated;
A cell identification circuit is provided for each cell storage circuit to identify the type of the next cell that accumulates in the corresponding cell storage circuit, and a cell identification circuit that determines the priority according to the identification output of each of these cell identification circuits and stores the highest priority cell. The cell storage circuit is equipped with a priority control circuit that instructs the stored cell storage circuit to send out the stored contents.
し九がって、優先制御回路の指令に応じ、高優先度のセ
ルから送出がなされ、これの反復によりセルの多重化送
信が行なわれる。Then, in accordance with the command from the priority control circuit, the cells with higher priority are transmitted, and by repeating this, multiplexed transmission of cells is performed.
以下、実施例を示すブロック図によって本発明の詳細な
説明する。Hereinafter, the present invention will be described in detail with reference to block diagrams showing embodiments.
同図においては、ATMセル多重化装置(以下、MPX
) 1が複数のATM送信装置(以下、TX)2−1.
2−2 を収容しており、MPXlには、TX2−1
.2−2と対応してセル蓄積回路(以下、STR)3−
1.3−2が設けであると共に、8TR3−1,3−2
毎にセル識別回路(以下、DIS)4−1.4−2.お
よび、入出力制御回路(以下、l0C)5−1.5−2
が設けてあり、このほか、共通の優先制御回路(以下
、FOR) 8も設けである。In the figure, an ATM cell multiplexer (hereinafter referred to as MPX
) 1 is a plurality of ATM transmitting devices (hereinafter referred to as TX) 2-1.
2-2, and MPXl accommodates TX2-1.
.. Corresponding to 2-2, a cell storage circuit (hereinafter referred to as STR) 3-
1.3-2 is provided, and 8TR3-1, 3-2
Each cell identification circuit (hereinafter referred to as DIS) 4-1.4-2. and input/output control circuit (hereinafter referred to as l0C) 5-1.5-2
In addition, a common priority control circuit (hereinafter referred to as FOR) 8 is also provided.
こ\において、l0C5−1、5−2は、5TR3−1
゜3−2 の内容をチエツクのうえ、りぎの送信セル送
出要求をTX2−1.2−2 へ各個に行なうものと
表ってお夕、これに応するTX2−1 、2−2からの
セルは各々対応する5TR3−1,3−2へ各個に蓄積
されると共に、このセルは同時にDIS4−1.4−2
にも与えられ、こ\において、対応する5TR3−1。In this\, l0C5-1, 5-2 are 5TR3-1
゜After checking the contents of 3-2, it appears that the next transmission cell transmission request is made to TX2-1, 2-2 individually, and the corresponding requests from TX2-1 and 2-2 are made. The cells are individually stored in the corresponding 5TR3-1, 3-2, and the cells are simultaneously stored in the DIS4-1.4-2.
is also given, in which the corresponding 5TR3-1.
3−2により蓄積し次セルの種別が識別され、この各識
別出力がFOR6へ与えられるものとなっている。3-2, the type of the next cell is identified, and each identification output is given to FOR6.
FOR6は、DIS4−1.4−2からの識別出力に応
じ、各セルの優先度を判断し、セルの蓄積状況にし九が
ってl0C5−1,5−2から与えられる送信要求に応
じ、かつ、最優先度のセルを蓄積し7’j 5TR3と
対応する!OC5に対して送信指令を送出する。FOR6 determines the priority of each cell according to the identification output from DIS4-1.4-2, and responds to the transmission request given from L0C5-1, 5-2 depending on the cell accumulation status. And, the highest priority cell is accumulated and corresponds to 7'j 5TR3! Sends a transmission command to OC5.
なお、FOR8は、送信停止要求Tが与えられていない
ときに送信指令の送出を行なう。Note that FOR8 sends out a transmission command when the transmission stop request T is not given.
し7九がって、例えば、5TR3−1に蓄積されたセル
の優先度が最高位、5TR3−2に蓄積されたセルの優
先度が次位であれば、まず、l0C5−1の制御によ、
!75TR3−1の蓄積内容が出力8として送出されて
から、l0C5−2の制御によ55TR3−2の蓄積内
容が出力8として送出される。Therefore, for example, if the priority of the cell stored in 5TR3-1 is the highest and the priority of the cell stored in 5TR3-2 is the second, first, the control of 10C5-1 is performed. Yo,
! After the stored contents of 75TR3-1 are sent out as output 8, the stored contents of 55TR3-2 are sent out as output 8 under the control of l0C5-2.
また、l0C5−1,5−2は、対応する5TR3−1
、3−2の蓄積内容送出後、TX2−1.2−2に対し
てつぎの送信セル送出要求を与えるため、以上の動作が
反復されるものとなシ、最優先度のセルから順次に出力
8として送出される。In addition, l0C5-1, 5-2 are the corresponding 5TR3-1
, 3-2, the above operations will be repeated in order to issue the next transmission cell transmission request to TX2-1.2-2, sequentially starting from the highest priority cell. Sent as output 8.
なお、TX2−1.2−2の台数は条件に応じて任意に
定めることができる。Note that the number of TX2-1.2-2 can be arbitrarily determined depending on conditions.
以上の説明により明らかなとおり本発明によれば、送信
装置と対応してセル蓄積回路を設けると共に、各セル蓄
積回路毎にセルの種別を識別するセル識別回路を設け、
これらの識別出力に応じて優先制御回路により優先度を
判断し、最優先のセルを蓄積したセル蓄積回路に対して
蓄積内容の送出を指令するものとし危ことにより、高速
によるセルの多重化が実現し、ATM方式のセル多重化
において顕著な効果が得られる。As is clear from the above description, according to the present invention, a cell storage circuit is provided corresponding to the transmitting device, and a cell identification circuit is provided for each cell storage circuit to identify the type of cell.
The priority control circuit determines the priority according to these identification outputs and instructs the cell storage circuit that has stored the highest priority cell to send out the stored contents. This method can be realized and a remarkable effect can be obtained in cell multiplexing of the ATM system.
図は本発明の実施例を示すブロック図である。
1・・・・ATMセル多重化装置、2−1.2−2・・
・・ATM送信装置、 3−1.3−2 ・・・・セル
蓄積回路、4−1.4−2・・・・セル識別回路、6・
・・・優先制御回路、8・・・・出力。The figure is a block diagram showing an embodiment of the present invention. 1...ATM cell multiplexer, 2-1.2-2...
...ATM transmission device, 3-1.3-2 ...Cell storage circuit, 4-1.4-2 ...Cell identification circuit, 6.
...priority control circuit, 8...output.
Claims (1)
装置からのセルを多重化のうえ送信する多重化装置にお
いて、前記各送信装置と対応して設けたセル蓄積回路と
、該セル蓄積回路毎に設けられ対応するセル蓄積回路に
蓄積されたセルの種別を識別するセル識別回路と、該各
セル識別回路の識別出力に応じて優先度を判断し最優先
のセルを蓄積した前記セル蓄積回路に対して蓄積内容の
送出を指令する優先制御回路とを備えたことを特徴とす
るATMセル多重化装置。A multiplexing device that accommodates a plurality of transmitting devices in an asynchronous transmission mode and multiplexes and transmits cells from each of the transmitting devices, a cell storage circuit provided corresponding to each of the transmitting devices, and the cell storage circuit. a cell identification circuit provided for each cell storage circuit for identifying the type of cells stored in the corresponding cell storage circuit; and the cell storage circuit that determines the priority according to the identification output of each cell identification circuit and stores the cells with the highest priority. An ATM cell multiplexing device comprising: a priority control circuit that instructs a circuit to send out stored contents.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1078471A JPH02260845A (en) | 1989-03-31 | 1989-03-31 | ATM cell multiplexer |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1078471A JPH02260845A (en) | 1989-03-31 | 1989-03-31 | ATM cell multiplexer |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02260845A true JPH02260845A (en) | 1990-10-23 |
Family
ID=13662930
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1078471A Pending JPH02260845A (en) | 1989-03-31 | 1989-03-31 | ATM cell multiplexer |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02260845A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04138732A (en) * | 1990-09-28 | 1992-05-13 | Nec Corp | Cell multiplex system in atm exchange |
| WO1997017779A1 (en) * | 1995-11-06 | 1997-05-15 | Ntt Mobile Communications Network Inc. | System for transmission between base station and exchange of mobile communication using fixed-length cell |
| KR19980013823A (en) * | 1996-08-03 | 1998-05-15 | 구자홍 | Multiplexing method using adaptive priority scheme |
| JPH10224361A (en) * | 1997-02-07 | 1998-08-21 | Oki Electric Ind Co Ltd | Cell assembler |
-
1989
- 1989-03-31 JP JP1078471A patent/JPH02260845A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04138732A (en) * | 1990-09-28 | 1992-05-13 | Nec Corp | Cell multiplex system in atm exchange |
| WO1997017779A1 (en) * | 1995-11-06 | 1997-05-15 | Ntt Mobile Communications Network Inc. | System for transmission between base station and exchange of mobile communication using fixed-length cell |
| US6442149B1 (en) | 1995-11-06 | 2002-08-27 | Ntt Mobile Communications Network Inc. | Transmission system between base station and switching center of mobile communications using fixed length cell |
| US6639903B2 (en) | 1995-11-06 | 2003-10-28 | Ntt Mobile Communications Network Inc. | Transmission system between base station and switching center of mobile communications using fixed length cell |
| KR19980013823A (en) * | 1996-08-03 | 1998-05-15 | 구자홍 | Multiplexing method using adaptive priority scheme |
| JPH10224361A (en) * | 1997-02-07 | 1998-08-21 | Oki Electric Ind Co Ltd | Cell assembler |
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