JPH0226376B2 - - Google Patents

Info

Publication number
JPH0226376B2
JPH0226376B2 JP58066340A JP6634083A JPH0226376B2 JP H0226376 B2 JPH0226376 B2 JP H0226376B2 JP 58066340 A JP58066340 A JP 58066340A JP 6634083 A JP6634083 A JP 6634083A JP H0226376 B2 JPH0226376 B2 JP H0226376B2
Authority
JP
Japan
Prior art keywords
tin
semiconductor chip
copper alloy
semiconductor device
copper
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP58066340A
Other languages
Japanese (ja)
Other versions
JPS59193036A (en
Inventor
Toshio Tetsuya
Hiroyuki Baba
Osamu Usuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP58066340A priority Critical patent/JPS59193036A/en
Priority to GB08409512A priority patent/GB2138633B/en
Priority to DE19843413885 priority patent/DE3413885A1/en
Publication of JPS59193036A publication Critical patent/JPS59193036A/en
Publication of JPH0226376B2 publication Critical patent/JPH0226376B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/20—Conductive package substrates serving as an interconnection, e.g. metal plates
    • H10W70/24—Conductive package substrates serving as an interconnection, e.g. metal plates characterised by materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/411—Chip-supporting parts, e.g. die pads
    • H10W70/417—Bonding materials between chips and die pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)

Description

【発明の詳細な説明】 ［発明の技術分野］ この発明は半導体装置の製造方法に関し、さら
に詳しくは、スズ−銅合金から成るろう材によつ
て半導体チツプを配設台上に固定する方法に係る
ものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of fixing a semiconductor chip on a mounting table using a brazing material made of a tin-copper alloy. This is related.

［発明の技術的背景］ 従来、半導体チツプを配設台に接合する場合、
予め半導体チツプの底面にバナジウム層を被着さ
せ、更に該バナジウム層に積層させてニツケル層
を形成した後、配設台表面と該ニツケル層とを
金・ゲルマニウム（Au−Ge）合金からなるろう
材で接合している（特願昭53−91415号、特願昭
53−91416号）。[Technical Background of the Invention] Conventionally, when bonding a semiconductor chip to a mounting base,
After depositing a vanadium layer on the bottom surface of the semiconductor chip in advance and then laminating it on top of the vanadium layer to form a nickel layer, the surface of the mounting table and the nickel layer are covered with a wax made of a gold-germanium (Au-Ge) alloy. (Patent Application No. 53-91415,
53-91416).

しかしながら、このような接合部を有する従来
の半導体装置には次のような欠点があつた。 However, conventional semiconductor devices having such junctions have the following drawbacks.

［背景技術の問題点］ 前記のごとき接合部を有する従来の半導体装置
においては、該半導体装置がたとえば高湿度の雰
囲気中で使用された場合、ニツケル層とAu−Ge
合金中の金との間に局部電池が形成されてニツケ
ル層が電食され、その結果、該半導体装置の電気
的特性が悪化したり、あるいは半導体チツプが配
設台から剥離する等の事故を発生する重大な欠点
があつた。また、ろう材として用いられている
Au−Ge合金は主成分が金であるため極めて高価
であり、Au−Ge合金をろう材として用いること
は半導体装置のコスト低減化を阻む一要因にもな
つていた。[Problems in the Background Art] In a conventional semiconductor device having the above-mentioned junction, when the semiconductor device is used in a high humidity atmosphere, the nickel layer and the Au-Ge
A local battery is formed between the gold in the alloy and the nickel layer is electrolytically corroded, resulting in deterioration of the electrical characteristics of the semiconductor device or accidents such as the semiconductor chip peeling off from the mounting base. There were serious shortcomings that occurred. It is also used as a brazing filler metal.
Since the Au-Ge alloy has gold as its main component, it is extremely expensive, and the use of the Au-Ge alloy as a brazing material has been one of the factors that prevents cost reduction of semiconductor devices.

［発明の目的］ 従つて、この発明の目的は電食を生ずるおそれ
がなく、且つ従来よりも低コストで製造すること
のできる改良された半導体装置の製造方法を提供
することである。[Object of the Invention] Accordingly, an object of the present invention is to provide an improved method of manufacturing a semiconductor device that is free from electrolytic corrosion and can be manufactured at a lower cost than conventional methods.

［発明の概要］ 本発明者は、スズ−銅合金においてスズと銅は
それぞれ同一蒸気圧下での温度がほぼ同一であり
（因みに、0.1Torrにおいてスズは1685〓、銅は
1690〓である）従つて、蒸着させたスズ−銅合金
組成が蒸着源合金組成と全く等しくなるように形
成させることが可能であること、またスズ−銅合
金は比較的低温で溶融する（スズ38〜92.4％で残
部が銅から成るスズ−銅合金の場合、混融点は
415℃）うえ、高湿度雰囲気中でもニツケルとの
間に局部電池を形成しないこと及びAu−Ge合金
にくらべてはるかに安価であること等の条件を備
えていることに着目し、スズ−銅合金を蒸発源と
してチツプ底面に蒸着して、蒸発源とほぼ同一組
成のスズ−銅合金蒸着膜を形成し、この蒸着膜を
スズ−銅合金から成るろう材として半導体チツプ
を配設台上に固定するという半導体装置の製造方
法を構成したものである。[Summary of the Invention] The present inventor discovered that in a tin-copper alloy, tin and copper have almost the same temperature under the same vapor pressure (by the way, at 0.1 Torr, tin has a temperature of 1685〓, and copper has a temperature of 1685
1690〓) Therefore, it is possible to form a deposited tin-copper alloy having exactly the same composition as the source alloy composition, and also that the tin-copper alloy melts at a relatively low temperature (tin In the case of a tin-copper alloy consisting of 38 to 92.4% copper with the remainder being copper, the melting point is
415℃) Furthermore, focusing on the fact that it does not form local batteries with nickel even in a high humidity atmosphere and is much cheaper than Au-Ge alloy, we developed a tin-copper alloy. is used as an evaporation source to deposit on the bottom surface of the chip to form a tin-copper alloy deposited film having almost the same composition as the evaporation source, and this deposited film is used as a brazing material made of tin-copper alloy to fix the semiconductor chip on the mounting table. This is a method for manufacturing a semiconductor device.

［発明の実施例］ 以下に添付図面を参照して本発明の一実施例を
説明する。[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the accompanying drawings.

第１図において１は半導体チツプ、５は配設
台、２はバナジウム層、３はニツケル層、４はろ
う材としてのスズ−銅合金層である。このような
構造の半導体装置をたとえば以下のごとき工程及
び条件で製作した。 In FIG. 1, 1 is a semiconductor chip, 5 is a mounting base, 2 is a vanadium layer, 3 is a nickel layer, and 4 is a tin-copper alloy layer as a brazing material. A semiconductor device having such a structure was manufactured using the following steps and conditions, for example.

まず、半導体チツプとして分割する前の半導体
ウエハの裏面にバナジウム層２を、300Å〜700Å
の厚さに被着させた後、該バナジウム層２の表面
にニツケル層３を1000Å〜3000Åの厚さで形成さ
せる。更に該ニツケル層３の表面に、スズ38〜
92.4％で残分が銅からなるスズ−銅合金層４を蒸
着法により5000Å〜3μｍ厚さに被着させる。そ
して前記三層の金属層を裏面に形成した半導体ウ
エハをスクライブして個々の半導体チツプ毎に分
割すると、前記三層の金属層２〜４を裏面に備え
た半導体チツプ１が得られる。 First, a vanadium layer 2 of 300 Å to 700 Å is coated on the back side of the semiconductor wafer before it is divided into semiconductor chips.
After depositing the vanadium layer 2 to a thickness of 1000 Å to 3000 Å, a nickel layer 3 is formed on the surface of the vanadium layer 2 to a thickness of 1000 Å to 3000 Å. Further, on the surface of the nickel layer 3, tin 38~
A tin-copper alloy layer 4 consisting of 92.4% copper and the balance is deposited by vapor deposition to a thickness of 5000 Å to 3 μm. When the semiconductor wafer having the three metal layers formed on the back surface is scribed and divided into individual semiconductor chips, a semiconductor chip 1 having the three metal layers 2 to 4 on the back surface is obtained.

一方、配設台５を415℃以上の温度に加熱して
おき、該配設台５上に前記半導体チツプ１のスズ
−銅合金層４を押圧することにより、スズ−銅合
金層４が融解し、冷却後には再び固化して半導体
チツプ１と配設台５とが相互に固着される。 On the other hand, by heating the mounting table 5 to a temperature of 415°C or higher and pressing the tin-copper alloy layer 4 of the semiconductor chip 1 onto the mounting table 5, the tin-copper alloy layer 4 is melted. However, after cooling, it solidifies again, and the semiconductor chip 1 and the mounting base 5 are fixed to each other.

［発明の効果］ 前記のごとき本発明製造方法によつて得られた
半導体装置に対して、２気圧の圧力下で約300時
間のプレツシヤークツカーテストを行つたとこ
ろ、電気的特性の低下は全く現れず、また半導体
チツプの剥離も全く生じなかつた。因みに、従来
の半導体装置に対して上記と同一条件でプレツシ
ヤークツカーテストを実施した場合、ニツケル層
が電食されて半導体チツプが配設台５上から剥離
し、また半導体チツプの電気的特性が悪化するの
が普通であつた。[Effects of the Invention] When the semiconductor device obtained by the manufacturing method of the present invention as described above was subjected to a pressure vacuum test for about 300 hours under a pressure of 2 atmospheres, there was no decrease in electrical characteristics. There was no appearance at all, and no peeling of the semiconductor chip occurred at all. Incidentally, when a pressure vacuum test is performed on a conventional semiconductor device under the same conditions as above, the nickel layer is electrolytically corroded and the semiconductor chip peels off from the mounting table 5, and the electrical conductivity of the semiconductor chip is It was normal for the characteristics to deteriorate.

以上のように、この発明によれば、 () 電食による電気的特性の悪化や電食による
半導体チツプの剥離等を生ずる恐れがなく、 () 製造コストを著しく低減することができる
（因みに、スズ−銅合金は従来使用されている
Au−Ge合金の価格の1/10以下であり、また最
終的歩留りを考慮すれば更にコスト低下にな
る）、等の長所を備えた半導体装置が提供され
る。 As described above, according to the present invention, () there is no risk of deterioration of electrical characteristics due to electrolytic corrosion or peeling of semiconductor chips due to electrolytic corrosion, and () manufacturing costs can be significantly reduced (incidentally, Tin-copper alloys are traditionally used
A semiconductor device is provided which has advantages such as being less than 1/10th the price of Au-Ge alloy, and further reducing the cost if the final yield is taken into account.

() ろう材の組成が蒸発源の組成とほぼ同一に
蒸着できるから、ろう材組成が安定的に形成で
きるとともに、Sn−Cu2成分からなるろう材が
１工程の蒸着で簡単に形成できる。() Since the composition of the brazing filler metal can be deposited with almost the same composition as that of the evaporation source, the composition of the brazing filler metal can be stably formed, and a brazing filler metal consisting of Sn-Cu2 components can be easily formed in one step of vapor deposition.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の製造方法による半導体装置の
断面図である。 １……半導体チツプ、２……バナジウム層、３
……ニツケル層、４……スズ−銅合金層、５……
配設台。 FIG. 1 is a sectional view of a semiconductor device manufactured by the manufacturing method of the present invention. 1... Semiconductor chip, 2... Vanadium layer, 3
...Nickel layer, 4...Tin-copper alloy layer, 5...
Installation stand.

Claims (1)

【特許請求の範囲】 １ 半導体チツプを配設台に固定するにあたり、
該半導体チツプの底面に、スズ38〜92.4重量％そ
して残分が銅の組成をもつスズ−銅合金を蒸発源
としたスズ−銅合金蒸着膜を形成した後、加熱し
た配設台上に該蒸着膜面を接触させ、該蒸着膜を
スズ−銅合金からなるろう材として溶融固化させ
半導体チツプを固定することを特徴とする半導体
装置の製造方法。 ２ 半導体チツプが、該チツプ底面にバナジウム
層を被着させ、さらに該バナジウム層に積層させ
てニツケル層を被着させたものである特許請求の
範囲第１項記載の半導体装置の製造方法。[Claims] 1. In fixing the semiconductor chip to the mounting base,
After forming a tin-copper alloy vapor deposition film on the bottom surface of the semiconductor chip using a tin-copper alloy as an evaporation source having a composition of 38 to 92.4% by weight tin and the balance being copper, the film was deposited on a heated mounting table. 1. A method of manufacturing a semiconductor device, which comprises bringing the vapor deposited film surfaces into contact with each other, and fixing the semiconductor chip by melting and solidifying the vapor deposited film as a brazing material made of a tin-copper alloy. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor chip has a vanadium layer deposited on the bottom surface of the chip, and a nickel layer laminated on the vanadium layer.
JP58066340A 1983-04-16 1983-04-16 Semiconductor device Granted JPS59193036A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP58066340A JPS59193036A (en) 1983-04-16 1983-04-16 Semiconductor device
GB08409512A GB2138633B (en) 1983-04-16 1984-04-12 Bonding semiconductor chips to a lead frame
DE19843413885 DE3413885A1 (en) 1983-04-16 1984-04-12 SEMICONDUCTOR DEVICE

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58066340A JPS59193036A (en) 1983-04-16 1983-04-16 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS59193036A JPS59193036A (en) 1984-11-01
JPH0226376B2 true JPH0226376B2 (en) 1990-06-08

Family

ID=13313027

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58066340A Granted JPS59193036A (en) 1983-04-16 1983-04-16 Semiconductor device

Country Status (3)

Country Link
JP (1) JPS59193036A (en)
DE (1) DE3413885A1 (en)
GB (1) GB2138633B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008221290A (en) * 2007-03-14 2008-09-25 Toshiba Corp Bonded body and bonding method
JP2013099790A (en) * 2013-02-04 2013-05-23 Toshiba Corp Junction

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3446780A1 (en) * 1984-12-21 1986-07-03 Brown, Boveri & Cie Ag, 6800 Mannheim METHOD AND JOINING MATERIAL FOR METALLICALLY CONNECTING COMPONENTS
US4954870A (en) * 1984-12-28 1990-09-04 Kabushiki Kaisha Toshiba Semiconductor device
JPS61156823A (en) * 1984-12-28 1986-07-16 Toshiba Corp Semiconductor device
JPH0783034B2 (en) * 1986-03-29 1995-09-06 株式会社東芝 Semiconductor device
JPS63110765A (en) * 1986-10-29 1988-05-16 Sumitomo Metal Mining Co Ltd Lead frame for ic
WO2006016479A1 (en) * 2004-08-10 2006-02-16 Neomax Materials Co., Ltd. Heat sink member and method for manufacture thereof
CN100459109C (en) 2005-05-23 2009-02-04 株式会社新王材料 Cu-Mo substrate and its manufacturing method
WO2008041350A1 (en) 2006-09-29 2008-04-10 Kabushiki Kaisha Toshiba Joint with first and second members with a joining layer located therebetween containing sn metal and another metallic material; methods for forming the same joint
JP5253794B2 (en) * 2006-12-25 2013-07-31 山陽特殊製鋼株式会社 Lead-free bonding material and manufacturing method thereof
JP5758242B2 (en) * 2011-09-06 2015-08-05 山陽特殊製鋼株式会社 Lead-free bonding material
JP2015056646A (en) * 2013-09-13 2015-03-23 株式会社東芝 Semiconductor device and semiconductor module

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB907734A (en) * 1959-06-06 1962-10-10 Teizo Takikawa Method of soldering silicon or silicon alloy
DE1298387C2 (en) * 1964-02-06 1973-07-26 Semikron Gleichrichterbau Semiconductor arrangement
GB1389542A (en) * 1971-06-17 1975-04-03 Mullard Ltd Methods of securing a semiconductor body to a support
US3821785A (en) * 1972-03-27 1974-06-28 Signetics Corp Semiconductor structure with bumps
DE2514922C2 (en) * 1975-04-05 1983-01-27 SEMIKRON Gesellschaft für Gleichrichterbau u. Elektronik mbH, 8500 Nürnberg Semiconductor component resistant to alternating thermal loads
DE2930789C2 (en) * 1978-07-28 1983-08-04 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Semiconductor device
JPS592174B2 (en) * 1978-07-28 1984-01-17 株式会社東芝 semiconductor equipment
JPS592175B2 (en) * 1978-07-28 1984-01-17 株式会社東芝 semiconductor equipment
JPS5521106A (en) * 1978-07-31 1980-02-15 Nec Home Electronics Ltd Method of forming ohmic electrode
JPS55107238A (en) * 1979-02-09 1980-08-16 Hitachi Ltd Semiconductor device and method of manufacturing the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008221290A (en) * 2007-03-14 2008-09-25 Toshiba Corp Bonded body and bonding method
JP2013099790A (en) * 2013-02-04 2013-05-23 Toshiba Corp Junction

Also Published As

Publication number Publication date
DE3413885C2 (en) 1990-02-22
JPS59193036A (en) 1984-11-01
GB2138633A (en) 1984-10-24
GB2138633B (en) 1986-10-01
DE3413885A1 (en) 1984-10-25

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