JPH02264370A - Picture processor - Google Patents

Abstract

PURPOSE:To improve the arithmetic efficiency of a processor by dividing respective frame memories into plural memory units, and allowing the all processors to access the respective divided memories. CONSTITUTION:The subject processor is provided with a control part 1, which controls the encoding/decoding of a picture, plural frame memories 3, which are individually expanded by the control part 1 whose connection can be altered and whose inside is divided into plural memories M1 to M4, and plural processors 2 which are individually connected to said control part 1 so as to access the respective memory units M1 to M4 in the frame memories 3 and whose connection is alterable. Further processing priority is applied to the frame memories M1 to M4 whose processing is delayed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image processing device, and particularly to an image processing device that performs image encoding and decoding and is capable of expanding and reducing the device.

[Prior Art] As a conventional image processing device, for example, IEEEGLOB
COM-87, pages 453 to 457, “A Realtime Video Signal Processor Suitable for Video Coding Applications”
Processor 5uitable ror M
otion Picture C.

dlng Applications”) J.

FIG. 5 is a block diagram showing an example of the configuration of a multiprocessor used in this conventional image processing apparatus.

In the same figure, a plurality of processors (2) for digital signal processing are arranged in parallel, and input data (7) of a data transfer controller (17) is transferred and distributed to the processors (2). 18) is input, and the processor (2) outputs processed data (19). That is, input data (7) is data transfer control 2SS (17
) is distributed and transferred to each processor (2) and processed within each processor (2), then the processed data (19) that is the output of the processor (2) moves to the next processing step. . The assigned areas of each processor (2) at this time are shown in FIG. 6(a). FIG. 6(a) shows an example of division when image data is processed in parallel by three processors, and the processing target area is equally distributed to each processor (2).

In addition, in interframe image encoding methods, it is recommended to encode only a portion of a certain size that has a difference between the input frame and the previous frame, and perform conditional pixel replenishment processing using the previous frame data for the rest. Common. Therefore, even if the number of pixels in the processing target area is the same, if the effective pixel rate is different, the amount of calculation required for processing will be different, and the required amount of calculation or the required calculation time is proportional to the effective pixel rate.

FIG. 6(b) shows the fifth
In the example of the effective pixel number distribution in each processor (2) when executed in the parallel configuration of processors (2) shown in the figure, the required calculation time per block in the parallel configuration of processor (2) is Among 2), it depends on the processing time of the processor (2) which processes the largest number of pixels. Therefore, the other processors (2) enter a waiting state and do not perform any processing.

[Problems to be Solved by the Invention] Conventional image processing devices have the above-described configuration, and therefore, there is a bias in the effective pixel distribution area within the image frame, and furthermore, when the distribution fluctuates over time. , the overall processing time is equal to the processing time of the processor that requires the longest processing time among all processors. In this case, the processing efficiency per processor decreases, so there is a problem that it is unsuitable for image signal processing in which a large amount of data is processed at high speed.

Another problem is that in order to change the number of processors or memory capacity, the configuration of the device must be changed.

This invention was made to solve these problems, and it is possible to control each processor so as to maximize the processing efficiency of a multiprocessor parallel configuration, and to limit the number of processors and memory capacity. A further object of the present invention is to obtain an image processing device whose configuration can be expanded and reduced.

[Means for Solving the Problems] In order to achieve the above object, an image processing device according to the present invention includes a control unit that controls encoding and decoding of images, and a control unit that is individually extended to the control unit, and a control unit that controls image encoding and decoding. The connection is changeable and
a plurality of frame memories each of which is internally divided into a plurality of memory units; each of the frame memories is individually connected to the control unit so as to be able to access each of the memory units in the frame memories;
the connection has a plurality of processors that are changeable;
The present invention is characterized in that processing efficiency can be increased by assigning processing priority to frame memories whose processing is delayed.

[Operation] According to the image processing device according to the present invention, since each processor can access each memory unit in each frame memory, the processing of each processor can be equalized, and the overall processing time can be reduced. is shortened.

Furthermore, since each processor and frame memory are detachable from the control unit, it is possible to expand or reduce the processor and frame memory.

[Embodiment] Next, an image processing apparatus according to an embodiment of the present invention will be described based on FIGS. 1 to 4.

FIG. 1 is a block diagram of the configuration of an image processing apparatus according to the present invention that performs image encoding and decoding.

In FIG. 1, a control unit (1) that performs encoding and decoding
A plurality of processors (2) (m of Pi to Pm) and a frame memory (3) that stores four image frames of M1 to M4 are detachably connected to the , and a transmission unit (
4) is connected to the human power section (5) on the input side. Each frame memory (3) has Ml, 1 to M1 . n,
M2゜1~M2. n, M3.1 to M3. n, M4.1~
M4. Each of n is divided into n pieces.

Next, the operation as a video encoding device will be explained. The description of the video decoding device and the still image encoding/decoding device will be omitted since they are similar to this. Input signal from camera (6)
is converted into input data (7) in the input section (5),
One frame of the image is written into the frame memory M1 through the encoding control unit (1). In frame memory M2,
The current image frame data written one time before is stored and is in a read state.

The frame memory M4 stores the decoded data of the previous image frame immediately before the current image frame of the frame memory M2, and is in a read state.

The frame data of the previous image stored in the frame memory M4 and the current image frame data stored in the frame memory M2 are controlled by the processor (2) by issuing a single control signal (10) through the encoding control unit (1). The accessed data is further encoded by the processor (2) and the encoded data is output to the transmission section (4). In the transmission section (4), data for one image frame is rearranged and output to the line (11).

Furthermore, in the processor (2), the encoded data is decoded and written as decoded data into the frame memory M3 through the encoding control unit (1).

Regarding the encoding of the next image frame, the frame memory M1 and frame memory M2 are exchanged, and the frame memory M3 and frame memory M4 are exchanged, so that the encoding process of the moving image is continuously performed.

FIG. 2 is a diagram showing the division of one image frame. 1
An image frame is divided into blocks of, for example, 16 x 16 pixels vertically and horizontally, and for each block, motion compensation processing is performed to find out which position of the previous image frame the block of the current image frame is close to, and the previous image is processed. DPCM (differential pulse code modulation) processing that takes the difference from the frame, D of the difference signal
CT (discrete cosine transform) processing, vector quantization processing,
Encoding is performed by calculations such as local decoding processing and filter processing. Here, for example, as shown in the figure, one image frame is allocated to one frame memory every three block lines, and further, n divided memory units (Mi, 1 to Mi) are allocated to each frame memory.

01 (referred to as L-1, 2, 3, 4 in the following explanation) is configured, and m processors (2) (P, 1 to Pm) are configured.
Parallel processing is performed in (here, n>m). Each divided memory unit has one port if it is a general-purpose RAM, and can be accessed by only one processor (2), so by setting n>m, parallel processing can be performed (2 When using point RAM, 2n>m).

One of the processors, P,1, besides encoding, controls the correspondence between the other processors (2) and the divided memory units. Next, this control method will be described.

The above encoding is performed sequentially from the first block at the top left of each divided memory unit, and ends when all blocks of three block lines are encoded.

At the start of encoding, processor P,1 has processor P,2 and memory units Mi,1, P,3 and ML.

2, ..., P, m and ML, m-1, and themselves P
, 1 and ML, m can be accessed respectively. Each processor then encodes the first block at the top left of each divided memory unit. Further, the processor (2) that has completed the first block is the processor P, 1
give an interrupt. Processor P.

1 interrupts encoding when an interrupt is received, and instructs the processor that is terminating the divided memory unit that is least accessed in encoding at that time,
The next block of the divided memory unit is processed.

After this interrupt processing is completed, the processor P,1 continues the original encoding. The processor,P,1,stores these states in a separate memory and makes them,accessible at any time. When n is set larger than m, the processing for each divided memory unit is equalized, and the efficiency of encoding one entire image increases.

When motion compensation is used in encoding, for example, when data needs to be read from a certain block of the previous image frame and its surrounding eight blocks, the topmost block of the three-block line in each divided memory unit is encoded. During processing, the processor (2) has access rights to both the divided memory unit to which the block belongs and the divided memory unit above it,
The other processor (2) controls the two divided memory units so that they cannot be accessed. Similarly, when encoding the lowest block of the three-block line, only the processor (2) has access rights to the lower divided memory unit. In this case, it is sufficient if n>2m, but the top or bottom block is accessed with priority over the middle block so that the access rights of the divided memory units do not overlap.

In this method, the number of processors (2), the number of memories, and the capacity can be made variable. For example, in the image shown in Figure 2, the number of divided memory units is n-8, and the number of processors (2) is m-.
4 has the encoding capability of 30 image frames per second, if 15 image frames per second is sufficient, the number of processors (2) may be m-2, or if 7.5 image frames per second is sufficient. is the number of processors (2) am-1
That's fine. Also, if you want to quadruple the screen area with 7.5 image frames per second, increase the capacity of each divided memory unit by 4 times.
The number of processors (2) may be doubled to m-4. In each case, processing can be performed with the same configuration and operation.

3 and 4 are configuration diagrams of the encoding/decoding control section (1). Control signals (10) such as address write pulses and chip select signals from processor P, 1 to P, m (2) are respectively designated as PA, 1 to PA, m, and input/output data are designated as PD, 1 to PD, m. do. Also, memory units M3.1 to M3. n and memory units M4.1 to M4.
A control signal to n.

1 to A, n input/output data is 1 to D, n, then processors P and j (hereinafter values of j-1 to m) divide memory units M3. In, M4. k (11 below)
~n) is accessed, the selector S
, k (12) selects PA, j, and the bidirectional buffer B, j, k (13) turns ON, and PD,
Take j and connect k.

These controls are performed by the processor P,1. The direction into the bidirectional buffer B,j, is from right to left in FIG. 2 when reading from the memory, and from left to right when writing from the memory, and is controlled by the processor P,j. The encoded data is stored in the buffer BT,j (1
4) and output to the transmission section (4).

Divided memory units M 1 , 1 to M 1 , n and M
2.1~M2. control signals to l0IA and 1, respectively.
~l0IA, n, 102A, 1 ~ l02A, n and 1.
The data are 10 ID, 1 to I 01 D, respectively.

n, l02D, 1~102D, n, to write the input data (7), control signals A, 1~102D, as shown in FIG.
A, n and the input control signal 10A are switched by the selector (15), so that one of them is 101A, 1 to 10IA.
, n, and the other is 102A, 1=I02D, n. Also, input/output data D, 1 to D, n and input data l0D
(7) is switched by the buffer (16) accordingly.

For example, divided memory units M1.1 to n and input data IO
DC? ), M2.1-n and input/output data D.

When connecting 1 to D, n, buffer B, a
Turn on B and d. Conversely, the divided memory unit Ml.

1 to n, 1 to D, n, M2. 1 to n and input data I
When connecting OD, use buffer B, b and B.

Turn on C.

From the above, processor P,j has memory unit M1,
k or M2. on the read side (current image frame) and memory unit M3. kSM4. It becomes possible to access k (previous image frame and image frame for decoding and writing),
Block processing is possible because the same processor accesses the same block of the image.

The encoding control unit (1) shown in Figs. 3 and 4 can change the number of memories by preparing the number of processors (m) and the number of memory divisions (n) up to the maximum number in advance, and expand the number of memories depending on the purpose. , reduction can be performed.

Moreover, if the encoding control unit (1) is made of LSI etc., m%n
can be made quite large.

According to an embodiment of the invention, therefore, a control unit for encoding or decoding an image is formed from a plurality of memory units and individually connected to said control unit, said connection being changeable; a plurality of frame memories for storing frames; and a plurality of processors that are individually connected to the control unit, each of which is accessible to each memory unit within the plurality of frame memories, and the connection is changeable. An image processing device is configured.

[Effects of the Invention] As explained above, this invention has a configuration in which each frame memory is divided into a plurality of memory units and each divided memory can be accessed by all processors, so that the calculation efficiency of the processor is high and the transmission frame A device can be obtained in which the processor and memory units can be easily expanded and reduced according to the number of pixels, the number of transmitted pixels, and the like.

[Brief explanation of drawings]

FIG. 1 is a configuration block diagram of an image processing device showing an embodiment of the present invention, FIG. 2 is an explanatory diagram of one image frame according to the present invention, and FIG. 3 is a partial configuration explanatory diagram of a control section of the present invention. FIG. 4 is a partial configuration explanatory diagram of the control section according to the present invention;
FIG. 5 is a block diagram showing a multiprocessor arrangement of a conventional device, FIG. 6(a) is an explanatory diagram showing memory area division,
FIG. 6(b) is an explanatory diagram of effective pixel distribution by region. In the figure, (1) is a control unit, (2) is a processor, (
3) is frame memory, (4) is transmission section, (5) is input section, (6) is input signal, (7) is input data, (8) is input/output memory signal, (9) is encoding/decoding (lO) is a control signal, (11) is a line, (12) is a selector, (13) is a bidirectional buffer, (14) is a buffer, (15) is a selector, (16) is a buffer , (17
) is the data transfer controller, (18) is the distribution data, (19
) is processed data. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Agent: Patent Attorney Masuo Oiwa (2 others) Block diagram of screen horizontal pixel embodiment Figure 1 Explanatory diagram of image frame of embodiment Figure 2 14: Configuration diagram of control unit of barafuchi embodiment 19: Processing Completed data Conventional multiprocessor arrangement Figure 5 Procedural amendment (voluntary) 8/2018 2. Name of the invention Image processing device (a) Memory area division 3. Person making the amendment Representative Moriya Shiki 4. Agent area (b) Effective pixel distribution by area 6 FIG. 5: Column for detailed description of the invention and brief description of drawings in the specification to be corrected. 6. Details of amendments and above

Claims (1)

[Claims] It is composed of a control unit that controls image encoding and decoding, and a plurality of memory units, each of which is individually connected to the control unit,
The connection is changeable and can access any of a plurality of frame memories storing image frame data and each memory unit within the plurality of frame memories, and is individually connected to the control unit, An image processing apparatus comprising: a plurality of processors in which the connection is changeable.