JPH02265251A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH02265251A
JPH02265251A JP8582789A JP8582789A JPH02265251A JP H02265251 A JPH02265251 A JP H02265251A JP 8582789 A JP8582789 A JP 8582789A JP 8582789 A JP8582789 A JP 8582789A JP H02265251 A JPH02265251 A JP H02265251A
Authority
JP
Japan
Prior art keywords
layer
inas
threshold voltage
alsb
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8582789A
Other languages
Japanese (ja)
Other versions
JPH0812914B2 (en
Inventor
Masashi Mizuta
正志 水田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8582789A priority Critical patent/JPH0812914B2/en
Publication of JPH02265251A publication Critical patent/JPH02265251A/en
Publication of JPH0812914B2 publication Critical patent/JPH0812914B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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  • Junction Field-Effect Transistors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To control a threshold voltage of a transistor by controlling a thickness of an InAs layer in the middle of a four-layer structure. CONSTITUTION:The following are provided: a p<+> GaAs substrate 1 as a III-V compound semiconductor substrate; a four-layer structure which is composed of an AlSb layer, and InAs layer, an AlSb layer and an InAs layer 2 to 5 which have been formed on the substrate 1 and whose energy level of an electron channel is generated by a quantum effect. Then, a thickness of the InAs layer 3 in the middle of the four-layer structure is controlled. That is to say, while the AlSb/Sb/InAs/AlSb quantum well structure 2 to 4 are used as a channel and the InAs semiconductor 5 on the surface is used as a gate electrode, the thickness of the quantum well layer is controlled. Thereby it is possible to obtain a field-effect transistor whose threshold voltage can be controlled.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は■−V族化合物半導体装置に関し、更に詳しく
はトランジスタの閾値電圧を任意に設計。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a ■-V group compound semiconductor device, and more specifically, to arbitrarily design the threshold voltage of a transistor.

制御可能なIII −V族化合物半導体装置に関する。The present invention relates to a controllable III-V compound semiconductor device.

〔従来の技術〕[Conventional technology]

従来の■−V族化合物半導体を用いたベテロ接合を含む
電界効果トランジスタは、AJ2GaAs/ G a 
A sを用いて作られるヘテロ接合電界効果トランジス
タ或5ま高電子移動度トランジスタがよく知られている
。これらの構造では、AfGaAs / G a A 
s接合に2次元電子ガスが溜まり伝導チャネルとなり、
AffiGaAs表面に設けた金属ゲート電極の電位を
制御して2次元電子ガス濃度、従ってソース・ドレイン
間の抵抗を制御している。
A field effect transistor including a betero junction using a conventional ■-V group compound semiconductor is AJ2GaAs/Ga
Heterojunction field effect transistors or high electron mobility transistors made using As are well known. In these structures, AfGaAs/G a A
Two-dimensional electron gas accumulates at the s-junction and becomes a conduction channel,
By controlling the potential of a metal gate electrode provided on the AffiGaAs surface, the two-dimensional electron gas concentration and, therefore, the resistance between the source and drain are controlled.

〔発明が解決しようとする課題] 上述のような従来の半導体装置におけるトランジスタの
閾値電圧はAI!、GaAs層のドーピング。
[Problem to be Solved by the Invention] The threshold voltage of the transistor in the conventional semiconductor device as described above is AI! , doping of the GaAs layer.

厚み、ゲート金属の種類等によって決められるが、実際
に使用できる金属の種類が限られることや、F−ピング
の変化によって実際上はチャネル抵抗が変化してしまう
こと等の問題があって、可変できる閾値電圧の大きさは
あまりない。
It is determined by the thickness, type of gate metal, etc., but there are problems such as the types of metals that can actually be used are limited and the channel resistance actually changes due to changes in the F-ping. There are not many threshold voltages that can be achieved.

更に、AfGaAs上に作られるショットキー障壁高さ
はプロセスに敏感であり、この点からも閾値電圧を制御
するのは困難である。
Furthermore, the height of the Schottky barrier formed on AfGaAs is process sensitive, and from this point of view as well, it is difficult to control the threshold voltage.

また、集積回路を考えた際に、特に閾値電圧0■のトラ
ンジスタが必要で閾値電圧の正確な制御が望まれている
Furthermore, when considering integrated circuits, a transistor with a threshold voltage of 0 is particularly required, and accurate control of the threshold voltage is desired.

本発明の目的は、トランジスタの閾値電圧の制御可能な
半導体装置を提供することにある。
An object of the present invention is to provide a semiconductor device in which the threshold voltage of a transistor can be controlled.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置は、 m−v族化合物半導体基板p”−GaSbと、前記半導
体基板上に形成された。1esb/InAs / A 
l S b / I n A sからなり電子チャネル
のエネルギー準位が量子効果によって生じる4層構造と
を含んでなり、前記4層構造中の真ん中のInAsの厚
みを制御することによりトランジスタの閾値電圧の制御
が可能なことを特徴とする。
The semiconductor device of the present invention includes an m-v group compound semiconductor substrate p"-GaSb, and is formed on the semiconductor substrate.1esb/InAs/A
It includes a four-layer structure consisting of L S b / I n A s in which the energy level of the electron channel is generated by a quantum effect, and the threshold voltage of the transistor can be adjusted by controlling the thickness of InAs in the middle of the four-layer structure. It is characterized by being able to control.

〔作用〕[Effect]

■−■族化合物半導体基板上に成長させた禁制帯幅の大
きな第1の半導体の間に禁制帯幅の小さな第2の半導体
を挾むと、第2の半導体の許容されるエネルギーは量子
効果により元の第2の半導体の禁制帯幅よりも大きくな
ることはよく知られている。また、この量子井戸構造の
外側に高濃度ドープした井戸層と同じ第2の半導体をゲ
ートとして成長させれば、この半導体のフェルミレベル
と井戸中の許容エネルギーとの関係は井戸層の幅によっ
て制御することができる。
When a second semiconductor with a small forbidden band width is sandwiched between a first semiconductor with a large forbidden band width grown on a ■-■ group compound semiconductor substrate, the allowable energy of the second semiconductor increases due to quantum effects. It is well known that the forbidden band width is larger than that of the original second semiconductor. Furthermore, if a second semiconductor, which is the same as the heavily doped well layer, is grown outside this quantum well structure as a gate, the relationship between the Fermi level of this semiconductor and the allowable energy in the well can be controlled by the width of the well layer. can do.

実際には半導体の組合せによってはチャネルに溜まる電
子の濃度や伝導帯不連続性等によって必ずしも所望の特
性が得られるとは限らない。本発明では第1の半導体と
して/lsbを、第2の半導体としてInAsを選んだ
場合に上で考えられる条件がよく成立することに着目し
た。
In reality, depending on the combination of semiconductors, desired characteristics may not always be obtained due to the concentration of electrons accumulated in the channel, conduction band discontinuity, etc. In the present invention, we focused on the fact that the above conditions are well established when /lsb is selected as the first semiconductor and InAs is selected as the second semiconductor.

■−■族化合物半導体であるGaAs基板上にはAl2
Sb及びInAsがほぼ格子整合して成長でき、したが
って高品質のエピタキシャル層が得られる。このうちA
l2SbとInAsは伝導帯の不連続値が非常に太きく
(1,3ev程度と言われている)、シたがってn型に
ドーピングしたA/2Sbから放出されたキャリアは、
TnAsの厚みによらずほぼ全てがA I S b /
 T n A s界面に溜まり伝導電子として寄与する
On the GaAs substrate, which is a ■-■ group compound semiconductor, Al2
Sb and InAs can be grown with near lattice matching, thus resulting in high quality epitaxial layers. Of these, A
l2Sb and InAs have a very large conduction band discontinuity (approximately 1.3 ev), so the carriers emitted from n-type doped A/2Sb are
Regardless of the thickness of TnAs, almost all of it is A I S b /
They accumulate at the T n As interface and contribute as conduction electrons.

一方、ゲート電極としてInAs単体を成長した場合に
は、InAsと空気或は真空との界面はn型に反転し、
ドーピングを特に行わなくてもよいゲート電極として働
く。
On the other hand, when InAs alone is grown as a gate electrode, the interface between InAs and air or vacuum is inverted to n-type.
It functions as a gate electrode that does not require special doping.

また、表面側のInAs/AffiSb接合は通常の成
長によって作製されており、微細プロセスによるダメー
ジや表面安定化のための絶縁膜堆積等にも影響されにく
い。
Furthermore, the InAs/AffiSb junction on the surface side is produced by normal growth, and is not easily affected by damage caused by microprocessing or deposition of an insulating film for surface stabilization.

また、ゲート電極としてInAsを用いた場合にはAl
Sbに対するバンド不連続はゲート電極と2次元電子で
ほぼ等しく、したがって井戸層であるInAsの厚みが
大きい場合には閾値電圧のほぼ0■のトランジスタを作
る°ことができ、一方、A I!、 S b / I 
n A s / A I S bによる量子井戸準位形
成を利用すればトランジスタの閾値電圧を任意に設計す
ることができる。
Furthermore, when InAs is used as the gate electrode, Al
The band discontinuity for Sb is almost equal between the gate electrode and the two-dimensional electrons, so if the thickness of the InAs well layer is large, it is possible to create a transistor with a threshold voltage of almost 0. , Sb/I
By using quantum well level formation by n A s / A I S b, the threshold voltage of a transistor can be arbitrarily designed.

以上のように本発明によれば、■−■族化合物半導体基
板p”−GaAs上に作製されたAffiSb / I
 n A s / A I S b量子井戸構造をチャ
ネルとし、表面のInAs半導体をゲート電極とし、量
子井戸層の厚みを制御することにより閾値電圧の制御可
能な電界効果トランジスタを提供できる。
As described above, according to the present invention, AffiSb/I fabricated on the ■-■ group compound semiconductor substrate p"-GaAs
By using the nA s / A I S b quantum well structure as a channel and the InAs semiconductor on the surface as a gate electrode, it is possible to provide a field effect transistor whose threshold voltage can be controlled by controlling the thickness of the quantum well layer.

〔実施例〕〔Example〕

以下、分子線エビクキシー法を用いて作製したI n 
A s / A Q S b / I n A s /
 A I S b / G asb基板の積層構造の実
施例について説明する。
Hereinafter, In
A s / A Q S b / I n A s /
An example of a stacked structure of an AISb/Gasb substrate will be described.

第1図は、この積層構造の断面図である。この積層構造
は、p”−GaAs基板l上に、A285層2、InA
s層3、AffiSb層4、InAs層5が作製されて
成る。
FIG. 1 is a cross-sectional view of this laminated structure. This laminated structure consists of a p''-GaAs substrate 1, an A285 layer 2, an InA
An s layer 3, an AffiSb layer 4, and an InAs layer 5 are fabricated.

各層のドーピング濃度および厚みは次の通りである。The doping concentration and thickness of each layer are as follows.

1!Sb層2;8000人(アンドープ)t nAsq
3 ;  300人(アンドープ)A/!Sb[4i 
 100人(アンドープ)+600人(n−2×101
Bc111−″)+50人(アンドープ) InAs層5 ; 1000人(n = 5 X10X
10l7”)この構造について通常のプロセスによって
電界効果トランジスタを作製した。このトランジスタで
は閾値電圧はほぼO■であった。
1! Sb layer 2; 8000 (undoped) t nAsq
3; 300 people (undoped) A/! Sb[4i
100 people (undoped) + 600 people (n-2 x 101
Bc111-'') + 50 people (undoped) InAs layer 5; 1000 people (n = 5 X10X
10l7'') A field effect transistor was fabricated using this structure by a normal process.The threshold voltage of this transistor was approximately O■.

一方、上記積層構造において、井戸層であるInAsA
sO2みだけを100人にしたInAs/A (2S 
b / I n A s / A Q S b / G
 a A s基板を用い、同様のトランジスタを作製し
たところ、このトランジスタの閾値電圧は前記トランジ
スタに比べて〜70mV変化していることが解った。
On the other hand, in the above laminated structure, the well layer is InAsA
InAs/A (2S
b / I n A s / A Q S b / G
When a similar transistor was fabricated using an aAs substrate, it was found that the threshold voltage of this transistor changed by ~70 mV compared to the previous transistor.

このように本発明の半導体装置は、■−■族化合物半導
体基板p”−GaSbと、この半導体基板上に形成され
たA RS b / I n A s / A I S
 b/ I n A sからなる4層構造とを含んでな
り、この4層構造の電子チャネルのエネルギー準位は量
子効果によって生じ、したがって4層構造中の真ん中の
InAsの厚みを制御してトランジスタの閾値電圧を制
御することができる。
As described above, the semiconductor device of the present invention includes the ■-■ group compound semiconductor substrate p"-GaSb and the ARSb/InAs/AIS formed on this semiconductor substrate.
The energy level of the electron channel of this four-layer structure is generated by a quantum effect, and therefore the thickness of the middle InAs in the four-layer structure can be controlled to form a transistor. threshold voltage can be controlled.

(発明の効果〕 以上説明したように、本発明によれば■−■族化合物半
導体基板上に閾値電圧を任意に制御したトランジスタ構
造が提供され、I−V族化合物半導体デバイスにその活
用が期待される。
(Effects of the Invention) As explained above, according to the present invention, a transistor structure in which the threshold voltage is arbitrarily controlled on a ■-■ group compound semiconductor substrate is provided, and its use is expected in IV group compound semiconductor devices. be done.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、分子線エピタキシー法を用いて作製したT 
n A s / A Q S b / I n A s
 / A 42 S b /GaSb基板の積層構造の
一例を示す断面図である。
Figure 1 shows the T fabricated using molecular beam epitaxy.
n A s / A Q S b / I n A s
FIG. 2 is a cross-sectional view showing an example of a laminated structure of a /A 42 S b /GaSb substrate.

Claims (1)

【特許請求の範囲】[Claims] (1)III−V族化合物半導体基板p^+−GaSbと
、前記半導体基板上に形成されたAlSb/InAs/
AlSb/InAsからなり電子チャネルのエネルギー
準位が量子効果によって生じる4層構造とを含んでなり
、前記4層構造中の真ん中のInAsの厚みを制御する
ことによりトランジスタの閾値電圧の制御が可能なこと
を特徴とする半導体装置。
(1) III-V compound semiconductor substrate p^+-GaSb and AlSb/InAs/
It is composed of AlSb/InAs and includes a four-layer structure in which the energy level of the electron channel is generated by a quantum effect, and the threshold voltage of the transistor can be controlled by controlling the thickness of the InAs layer in the middle of the four-layer structure. A semiconductor device characterized by:
JP8582789A 1989-04-06 1989-04-06 Semiconductor device Expired - Fee Related JPH0812914B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8582789A JPH0812914B2 (en) 1989-04-06 1989-04-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8582789A JPH0812914B2 (en) 1989-04-06 1989-04-06 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02265251A true JPH02265251A (en) 1990-10-30
JPH0812914B2 JPH0812914B2 (en) 1996-02-07

Family

ID=13869684

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8582789A Expired - Fee Related JPH0812914B2 (en) 1989-04-06 1989-04-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0812914B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02266536A (en) * 1989-04-07 1990-10-31 Nec Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02266536A (en) * 1989-04-07 1990-10-31 Nec Corp Semiconductor device

Also Published As

Publication number Publication date
JPH0812914B2 (en) 1996-02-07

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