JPH02267956A - Semiconductor device package - Google Patents
Semiconductor device packageInfo
- Publication number
- JPH02267956A JPH02267956A JP8861689A JP8861689A JPH02267956A JP H02267956 A JPH02267956 A JP H02267956A JP 8861689 A JP8861689 A JP 8861689A JP 8861689 A JP8861689 A JP 8861689A JP H02267956 A JPH02267956 A JP H02267956A
- Authority
- JP
- Japan
- Prior art keywords
- aluminum nitride
- polyimide film
- nitride substrate
- semiconductor device
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Lead Frames For Integrated Circuits (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、半導体装置パッケージに関し、特に集積回路
パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor device packages, and more particularly to integrated circuit packages.
従来の集積回路パッケージは、アルミナ(Aη203)
多層配線基板を用いたものや、プラスチックピングリッ
ドアレイパッケージが一般的であった。Traditional integrated circuit packages are made of alumina (Aη203)
Those using multilayer wiring boards and plastic pin grid array packages were common.
上述した従来のアルミナ基板やプラスチックを用いた集
積回路パッケージでは、これらの材料のもつ熱伝導率が
低く、基板のみからの熱放散が悪いので高出力集積回路
を直接実装することが不可能であった。With the conventional integrated circuit packages using alumina substrates and plastics, these materials have low thermal conductivity and heat dissipates only from the substrate, making it impossible to directly mount high-power integrated circuits. Ta.
本発明の半導体装置パッケージは、窒化アルミニウム基
板の裏面から突き出して設けられた端子ピンと、前記窒
化アルミニウム基板の表面のチップ搭載部を除いて設け
られたポリイミド膜と、前記ポリイミド膜上に設けられ
スルーホールを介して前記端子ピンに接続される導体層
とを有するというものである。The semiconductor device package of the present invention includes a terminal pin provided protruding from the back surface of an aluminum nitride substrate, a polyimide film provided on the front surface of the aluminum nitride substrate except for a chip mounting area, and a through-hole provided on the polyimide film. and a conductor layer connected to the terminal pin via a hole.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第1区は本発明の一実施例の集積回路パッケージの断面
図である。The first section is a cross-sectional view of an integrated circuit package according to an embodiment of the present invention.
まず、窒化アルミニウム焼結体からなる窒化アルミニウ
ム基板1に貫通穴を設は金属製の端子ピン2をそう人す
る6次に窒化アルミニウム基板1の表面にポリイミド膜
3を形成する。ポリイミド膜3の所定の位置には、スル
ーホールがあけてあり、その部分では端子ピン2の1部
が露出している。このようなポリイミド膜は、次のよう
な手順で形成される。まず、東し社製のフォトニースU
R314(商品名)のような 感光性ポリイミド前躯体
フェスを窒化アルミニウム基板1の表面にコーティング
する0次にガラスマスクを用いて感光性ポリイミド前躯
体フェスコーティング膜の所定の部分を露光する。露光
後、アルコールを主成分とする所定の現像液で現像する
と、露光していない部分が現像液に溶解し、他の部分が
残り、スルーホールパターンが得られる。次に加熱する
ことによりポリイミド前駆体をイミド化させ、ポリイミ
ド膜を得る。この加熱時に、感光性成分は揮発し、ポリ
イミド膜中には残らない。こうして所定の位置にスルー
ホールを有するポリイミド膜3が形成される。First, a through hole is formed in an aluminum nitride substrate 1 made of an aluminum nitride sintered body, and a metal terminal pin 2 is inserted thereinto.Next, a polyimide film 3 is formed on the surface of the aluminum nitride substrate 1. A through hole is formed at a predetermined position in the polyimide film 3, and a portion of the terminal pin 2 is exposed at the through hole. Such a polyimide film is formed by the following procedure. First, Photonice U made by Toshisha
A photosensitive polyimide precursor face coating film such as R314 (trade name) is coated on the surface of the aluminum nitride substrate 1. A glass mask is used to expose a predetermined portion of the photosensitive polyimide precursor face coating film. After exposure, when it is developed with a predetermined developer containing alcohol as a main component, the unexposed portion is dissolved in the developer and the other portion remains, resulting in a through-hole pattern. Next, the polyimide precursor is imidized by heating to obtain a polyimide film. During this heating, the photosensitive component evaporates and does not remain in the polyimide film. In this way, a polyimide film 3 having through holes at predetermined positions is formed.
次に金又は銅の導体層4をエツチング法又は、選択メツ
キ法で形成する。以上のような工程により本発明の集積
回路パッケージが製作される。Next, a gold or copper conductor layer 4 is formed by etching or selective plating. The integrated circuit package of the present invention is manufactured through the steps described above.
また、第1図には本発明の集積回路パッケージに半導体
チップ5を実装した状態も図示しである。半導体チップ
5の端子(ポンディングパッド)と導体層4とをワイヤ
ーボンディング法等の工程で接続する。最終的には半導
体チップ、ボンディング線、導体層を覆って合成樹脂で
コーディングし保護する。なお、半導体チップは窒化ア
ルミニウム基板表面のチップ搭載部に例えば銀ペースト
のような良熱伝導性接着剤によりダイボンディングされ
ている。FIG. 1 also shows a state in which a semiconductor chip 5 is mounted on the integrated circuit package of the present invention. The terminals (ponding pads) of the semiconductor chip 5 and the conductor layer 4 are connected by a process such as wire bonding. Finally, the semiconductor chip, bonding wires, and conductor layers are coated and protected with synthetic resin. Note that the semiconductor chip is die-bonded to the chip mounting portion on the surface of the aluminum nitride substrate using a highly thermally conductive adhesive such as silver paste.
窒化アルミニウム基板に直接導体層を設けることは密着
性に問題があり実用的ではないが、ポリイミド膜を間に
設けることにより密着性の悪さは回避できる。又、半導
体チップは熱伝導のよい窒化アルミニウム基板にダイボ
ンディングできるので半導体装置の放熱性が改善される
。Although it is not practical to provide a conductor layer directly on an aluminum nitride substrate because of problems with adhesion, poor adhesion can be avoided by providing a polyimide film therebetween. Furthermore, since the semiconductor chip can be die-bonded to an aluminum nitride substrate with good thermal conductivity, the heat dissipation of the semiconductor device is improved.
以上説明したように本発明は、窒化アルミニウム基板上
にポリイミド膜を介して導体層を設けることにより、放
熱性のよい窒化アルミニウム基板を本体とする半導体装
置パッケージを実現できるので高出力半導体装置を単純
な構造で実現できるといった効果がある。また、絶縁層
にポリイミド膜を使用しているため、高周波用集積回路
の実装にも有利である。As explained above, the present invention makes it possible to realize a semiconductor device package whose main body is an aluminum nitride substrate with good heat dissipation by providing a conductor layer on an aluminum nitride substrate via a polyimide film, thereby simplifying the production of high-power semiconductor devices. It has the advantage that it can be realized with a simple structure. Furthermore, since a polyimide film is used for the insulating layer, it is advantageous for mounting high-frequency integrated circuits.
5キン1aテ・・/フ。5 Kin 1a Te.../F.
第1図は本発明の一実施例の断面図である。
1・・・窒化アルミニウム基板、2・・・端子ピン、3
・・・ポリイミド膜、4・・・導体層、5・・・半導体
チップ、6・・・ボンディング線。
M 1 図FIG. 1 is a sectional view of an embodiment of the present invention. 1... Aluminum nitride substrate, 2... Terminal pin, 3
... Polyimide film, 4... Conductor layer, 5... Semiconductor chip, 6... Bonding wire. M1 figure
Claims (1)
端子ピンと、前記窒化アルミニウム基板の表面のチップ
搭載部を除いて設けられたポリイミド膜と、前記ポリイ
ミド膜上に設けられスルーホールを介して前記端子ピン
に接続される導体層とを有することを特徴とする半導体
装置パッケージ。A terminal pin provided protruding from the back surface of the aluminum nitride substrate, a polyimide film provided on the surface of the aluminum nitride substrate excluding the chip mounting area, and a through hole provided on the polyimide film to the terminal pin. A semiconductor device package characterized by having a conductor layer to be connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8861689A JP2684757B2 (en) | 1989-04-07 | 1989-04-07 | Semiconductor device package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8861689A JP2684757B2 (en) | 1989-04-07 | 1989-04-07 | Semiconductor device package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02267956A true JPH02267956A (en) | 1990-11-01 |
| JP2684757B2 JP2684757B2 (en) | 1997-12-03 |
Family
ID=13947740
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8861689A Expired - Lifetime JP2684757B2 (en) | 1989-04-07 | 1989-04-07 | Semiconductor device package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2684757B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127634A (en) * | 1994-10-11 | 2000-10-03 | Fujitsu Limited | Wiring board with an insulating layer to prevent gap formation during etching |
-
1989
- 1989-04-07 JP JP8861689A patent/JP2684757B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6127634A (en) * | 1994-10-11 | 2000-10-03 | Fujitsu Limited | Wiring board with an insulating layer to prevent gap formation during etching |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2684757B2 (en) | 1997-12-03 |
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