JPH0226816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an analog switch device using a MOS field effect transistor.

[Technical background of the invention]

An analog switch device is one that is turned on (conducting) by a clock signal that controls the device.
state or off (non-conducting) state,
It is a device in which input information, ie, an analog input signal, is transmitted to the output when it is in the on state, and no analog input signal is transmitted when it is in the off state.

FIG. 1 is a circuit diagram of a conventional analog switch device. This device consists of a source electrode S of an N-channel enhancement type MOS field effect transistor (hereinafter abbreviated as MOS transistor) 1 and a P-channel enhancement type MOS field effect transistor (hereinafter referred to as MOS transistor).
The drain electrode D of the transistor 2 is connected, and this connection point is connected to the supply terminal 3 of the analog input signal IN, and the drain electrode D of the MOS transistor 1 and the source electrode S of the MOS transistor 2 are connected.
and connect this connection point to the analog output signal.
Connect to OUT output terminal 4, and then
A clock signal φ is supplied to the gate electrode G of the MOS transistor 1, and a clock signal that is a complementary pair to the clock signal φ is supplied to the gate electrode G of the MOS transistor 2.
The substrate electrode B of the transistor 1 has a voltage V _SS (for example,
0V or negative polarity voltage), P channel MOS
It is constructed by supplying a voltage V _DD (for example, a positive polarity voltage) corresponding to the high potential of the clock signal φ to the substrate electrode B of the transistor 2, respectively.

In such a device, when the clock signal φ is set to the H level (V _DD ) and the clock signal is set to the L level (V _SS ), both the N-channel and P-channel MOS transistors 1 and 2 are turned on. As a result, the resistances R _N and R _P become small, the input signal IN is transmitted through both MOS transistors 1 and 2, and the output signal OUT is taken out from the terminal 4. On the other hand, when the clock signal φ is set to L level and the clock signal is set to H level, both MOS transistors 1 and 2 are turned off, their resistances R _N and R _P become extremely large, and the input signal IN is applied to terminal 4. and the output signal OUT is not taken out.

[Problems with background technology]

By the way, in an analog switch device, the input signal
Even if IN passes through MOS transistors 1 and 2, it is necessary to make the voltage of the output signal OUT equal to or linearly proportional to the voltage of the input signal IN. To do this, when both MOS transistors 1 and 2 are turned on, It is necessary to always keep the resistance value between terminals 3 and 4 constant. However, in conventional analog switch devices, the resistance between terminals 3 and 4 changes according to the voltage at terminals 3 or 4. this is
This is because MOS transistors have a source-substrate bias effect (backgate bias effect), and this effect changes the threshold of the MOS transistor, which affects the on-resistance of the MOS transistor. . That is,
The following proportional equation holds true for the on-resistance R of the MOS transistor.

R∝1/V _GS −V _th (1) V _GS : Bias voltage between the gate electrode and source electrode V _th : Threshold value Furthermore, the threshold value V _th of the MOS transistor is expressed by the following equation.

V _th =V _th0 +t _OX /ε _OX・√2・_.S・・(
√2 _F + _BS −√2 _F )……(2) V _th0 : Intrinsic threshold (when the bias voltage between the source electrode and substrate electrode is 0V) t _OX : Thickness of gate oxide film ε _OX : Dielectric constant of gate oxide film ε _S : Dielectric constant of silicon q: Amount of electron charge N: Substrate impurity concentration V _BS : Bias voltage between source electrode and substrate electrode φ _F : Fermi level Above (2) As is clear from the equation, as V _BS becomes larger, the threshold value V _th also becomes larger, and as V _th becomes larger, R becomes larger according to the above equation (1).

Furthermore, the N-channel MOS transistor 1 of the analog switch device shown in FIG. In addition, the P channel MOS transistor 2 is connected to the substrate 11.
If the impurity concentration of the P well region 12 is naturally higher than that of the substrate 11,
The threshold sensitivity of the N-channel MOS transistor 1 to the source-substrate bias effect is higher than that of the P-channel MOS transistor 2;
It is usually about 3 times more expensive. Therefore both MOS
When the voltage of the input signal IN applied to terminal 3 is changed from V _SS (0V) to V _DD (+5V) when transistors 1 and 2 are on, the MOS transistor The characteristics of resistance R _N of MOS transistor 1 and resistance R _P of MOS transistor 2 are not symmetrical,
As a result, near 1/2V _DD (+2.5V), which is the intermediate voltage of the input signal IN, the resistance R _ON (= _{R N ・ R P /} R _N +R _P ) has a high value.

As described above, the conventional method has a disadvantage in that large distortion occurs in the output signal OUT because the resistance between the input and output terminals is not constant.

[Purpose of the invention]

This invention was made in consideration of the above circumstances, and its purpose is to provide an analog switch device that can maintain a constant resistance value between input and output terminals and obtain an output signal with less distortion. Our goal is to provide the following.

[Summary of the invention]

According to an embodiment of the present invention, a switch is constructed by connecting enhancement type N-channel and P-channel MOS field effect transistors in parallel, and the enhancement type This circuit is designed to supply the output voltage of a voltage buffer circuit that outputs a voltage according to the input analog signal voltage, and is composed of an N-channel MOS field effect transistor and a depletion P-channel MOS field effect transistor. .

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 4 is a circuit configuration diagram of one embodiment of an analog switch device according to the present invention, and parts corresponding to those of the conventional device shown in FIG. 1 are given the same reference numerals and will be explained. First, the source electrodes S and P of the N-channel enhancement type MOS transistor 1.
The channel is connected to the drain electrode D of the enhancement type MOS transistor 2, and this connection point is connected to the supply terminal 3 for the analog input signal IN. The drain electrode D of the MOS transistor 1 and the source electrode S of the MOS transistor 2 are connected, and this connection point is connected to the analog output signal.
Connected to OUT output terminal 4. The above MOS
A clock signal φ is applied to the gate electrode G of the transistor 1, and a clock signal φ is applied to the gate electrode G of the MOS transistor 2.
A clock signal φ complementary to the clock signal φ is supplied to each of the clock signals φ and φ. The substrate electrode B of the MOS transistor 2 is supplied with a power supply voltage V _DD (for example, a positive polarity voltage) corresponding to the high voltage (H level) of the clock signal φ. Further, the input terminal of a voltage buffer circuit (voltage conversion means) 5 that outputs a voltage according to the voltage V _IN of the analog input signal IN is connected to the terminal 3, and the output voltage from this circuit 5 is applied to the substrate of the MOS transistor 1. Supplied to electrode B. That is, the analog switch device shown in FIG. 4 uses the input analog signal voltage output from the voltage buffer circuit 5 instead of constantly supplying the power supply voltage V _SS to the substrate electrode B of the N-channel MOS transistor 1 as in the conventional case. It is designed to supply a voltage according to V _IN .

FIG. 5 is an overall circuit diagram of the analog switch device specifically showing the voltage buffer circuit 5 in FIG. 4. The voltage buffer circuit 5 has a drain electrode D connected to a power supply voltage _VDD application point, a source electrode S connected to the voltage output terminal 6, a gate electrode G connected to the terminal 3, and a substrate electrode B connected to the voltage output terminal 6. Enhancement type with N-channel
A source electrode S is connected to the MOS transistor 7, a source electrode S is connected to the voltage output terminal 6, a drain electrode D is connected to the power supply voltage V _SS application point, a gate electrode G is connected to the terminal 3, and a substrate electrode B is connected to the V _DD application point. P channel depletion type MOS transistor 8
The voltage output terminal 6 is connected to the substrate electrode B of the N-channel MOS transistor 1. Further, a parasitic capacitance 9 is equivalently connected to the terminal 6.

FIG. 6 is a sectional view showing an element structure when the circuit shown in FIG. 5 is actually integrated. In the figure, there is a P well region 22 in the N type semiconductor substrate 21.
is formed. The source region 23 and drain region 24 of the MOS transistor 2 , the MOS
A drain region 25 and a source region 26 of transistor 8 are respectively formed. Further, in the surface region of the P well region 22, a source region 27 and a drain region 28 of the MOS transistor 7 , and a source region 29 and a drain region 30 of the MOS transistor 1 are formed, respectively, by diffusion of N type impurities. Further, at the boundary between the P well region 22 and the substrate 21, a P-type contact region 3 with a high impurity concentration for making contact with the P well region 22 surrounds the P well region 22.
1 is formed. Each of the source regions 23, 26,
Source electrodes S are taken out from 27 and 29, drain electrodes D are taken out from each of the drain regions 24, 25, 28, and 30, and the MOS transistors 1 and 7 are taken out from the contact region 31. The substrate electrode B is taken out. Also, each MOS
Gate structures are formed on the substrate 21 between the drain and source regions of the transistor, and each gate electrode G is taken out from each gate structure. Then, the substrate electrodes B of the MOS transistors 2 and 8 are taken out from the substrate 21. Note that the parasitic capacitance 9 is connected to the substrate 21 and the P well region 22.
This is due to the PN junction that occurs between

Next, the operation of the apparatus configured as described above will be explained. First, the clock signal φ is set to H level (V _DD ),
Set the clock signal to L level (V _SS )
Both MOS transistors 1 and 2 are turned on. Next, in this state, a V _SS level, for example 0V, is supplied as the voltage V _IN of the analog input signal IN. At this time, since the depletion type MOS transistor 8 is turned on, the voltage output terminal 6 of the voltage buffer circuit 5
The voltage is the difference voltage between the analog input signal voltage V _IN and the threshold value V _thD of the MOS transistor 8. That is, since the output voltage of the voltage buffer circuit 5 is applied to the P-well region 22 in FIG. 6, if this voltage is V _p-well , this can be expressed by the following equation.

V _p-well = V _IN −V _thD ...(1) By turning on the MOS transistor 8,
The parasitic capacitance 9 connected to the voltage output terminal 6 of the voltage buffer circuit 5 is set to _VDD (for example, +5V) in advance.
If the battery had been charged to 1, this voltage would drop to the value expressed by equation (1) above.

By the way, when the voltage at the voltage output terminal 6 is +5V, the source electrode S of the MOS transistor 8
Also, since the power supply voltage _VDD of +5V is always supplied to the substrate electrode B of this MOS transistor 8, immediately after the MOS transistor 8 is turned on, this MOS transistor 8
The back gate bias voltage _VBB of is 0V. Therefore, the threshold value at this time is V _thD1 in Figure 7.
The current characteristic between the drain and the source at this time becomes a straight line a in FIG. 7. Next, after the MOS transistor 8 is turned on, when the voltage V _p-well approaches the value expressed by the above equation (1), the source electrode S of the MOS transistor 8
The voltage will approach 0V from +5V, and as a result, the back gate bias voltage _VBB of the MOS transistor 8 will gradually increase.
Along with this, the threshold value of the MOS transistor 8 shifts to the left in FIG. 7, and at the same time, the straight line representing the drain-source current characteristic also shifts to the left in parallel. Therefore, the threshold value V _thD2 of the MOS transistor 8 after the shift is as shown in FIG.
If the straight line b indicating the current characteristics between the drain and source of MOS transistor 8 is an enhancement type, the voltage V _p-well is approximately 0V.
It drops to a value close to 0V.

Next, assume that the analog input signal voltage V _IN increases from 0V in the positive direction. When the value of V _IN -V _p-well becomes larger than the threshold value V _thN of the MOS transistor 7 shown in FIG. 7, the MOS transistor 7 is turned on and the parasitic capacitance 9 is charged by the power supply V _DD . begins to be At this time, MOS transistor 8 is in an off state. When the MOS transistor 7 is turned on and a current corresponding to the N-channel enhancement type drain-source current characteristic shown by the straight line c in FIG. 7 flows through the MOS transistor 7, the voltage V _p of the voltage output terminal 6 increases. _-well
increases to V _IN −V _thN . Specifically, in a typical CMOS process, V _thN = +1V, V _DD =
If the voltage is +5V, bias can be made up to V _p-well =5-1=+4V. That is, the input analog signal voltage
When V _IN increases from 0V to +5V, a bias voltage varying from 0V to +4V is applied to the substrate electrode B of the MOS transistor 1.

This time, conversely, assume that the analog input signal voltage V _IN decreases from +5V to 0V. When V _IN decreases from +5V, the value of V _IN -V _p-well decreases below the threshold value V _thN of MOS transistor 7.
MOS transistor 7 is turned on. On the other hand, in MOS transistor 8, the back gate bias voltage
Assume that the threshold value V _thD1 when V _BB is 0V is set to +0.6V. And when V _IN = +5V, as mentioned above,
If V _p-well = +4V, the back gate bias voltage V _BB of MOS transistor 8 at this time is 5-4
= about +1V. In this case, if the threshold value V _thD of MOS transistor 8 is shifted to +0.2V, when V _IN drops to 4 + 0.2 = +4.2V, MOS transistor 8 is turned on and the voltage
V _p-well drops to a value close to 0V via this MOS transistor.

Figure 8 shows the threshold values of MOS transistors 1 and 7 as +1.2V, and the threshold value of MOS transistor 2 as -
1.2V, threshold of MOS transistor 8 +0.7V
FIG. 3 is a characteristic diagram showing the change characteristics of the voltage V _p-well of the voltage output terminal 6 with respect to the analog input signal voltage V _IN when the voltage V p-well is set to the analog input signal voltage V IN. as shown
Since V _p-well changes almost proportionally to V _IN ,
The voltage between the source and the substrate of the MOS transistor 1, that is, the back gate bias voltage, can always be maintained at a substantially constant value, and as a result, changes in the on-resistance of the MOS transistor 1 due to threshold fluctuations can be almost eliminated.

Next, when clock signal φ is set to L level and clock signal φ is set to H level, both MOS transistors 1 and 2 are turned off, so that
Both resistances R _N and R _P have extremely large values, and as a result, the analog input signal IN is not transmitted to the terminal 4 and the analog output signal OUT is not taken out.

FIG. 9 shows the resistance R _N of MOS transistor 1 when the analog input signal voltage V _IN supplied to terminal 3 is varied from 0V to +5V when both MOS transistors 1 and 2 are on in the above embodiment device.
and the resistance R _P of MOS transistor 2, and R _N and R _P
The resistance between terminals 3 and 4 expressed as a parallel resistance of
This represents the characteristics of each R _ON . In the characteristic diagram of the conventional device shown in Fig. 3 above, when the analog input signal voltage V _IN is around +2.5V, the N-channel MOS
ΔV _th of transistor 1 increased and the value of R _N changed greatly, but in the above embodiment device, as shown in FIG. 9, R _N and R _P are different when the analog input signal voltage V _IN is It changes in a line-symmetric manner around +2.5V. This is the analog input signal voltage V _IN to the substrate electrode B of N-channel MOS transistor 1.
This is because the back gate bias effect of the MOS transistor 1 is kept constant by supplying a voltage approximately proportional to the voltage, thereby minimizing the change in R _N due to the fluctuation of the threshold value. Therefore, terminal 3,
The resistance R _ON between 4 and 4 has almost flat characteristics, and can be kept at a constant value without being affected by the analog input signal voltage V _IN . As a result, the analog output signal OUT
It is possible to minimize the distortion generated in the process.

Further, in the above embodiment, when setting the voltage of the voltage output terminal 6 in the voltage buffer circuit 5 , the N-channel MOS transistor 7 and the P-channel MOS transistor
Both of the MOS transistors 8 and 8 do not turn on, and the voltage buffer circuit 5
Since no current flows between V _DD and V _SS via the MOS transistors 7 and 8 in series, the increase in current consumption due to the provision of this voltage buffer circuit 5 is extremely small. Furthermore, if there is no need to consider current consumption, a simple resistor may be connected in place of the depletion type MOS transistor 8 in the P channel.

FIG. 10 is a circuit diagram of another embodiment of the invention. In this embodiment, instead of directly connecting the drain electrode D of the N-channel MOS transistor 7 in the voltage buffer circuit 5 to the V _DD application point, the clock signal is supplied to the gate electrode G of P.
A new voltage buffer circuit 42 is configured by connecting through an enhancement type MOS transistor 41 in a channel.

The voltage buffer circuit 5 receives an analog input signal.
N-channel MOS transistor 1 transmitting IN
Since it is necessary to operate only when both the MOS transistor 2 and the P channel MOS transistor 2 are turned on, by adding the MOS transistor 41 whose gate input is the clock signal, the analog input signal
The MOS transistor 41 is turned on only when IN is transmitted to the terminal 4, and the voltage V _p-well corresponding to the analog input signal voltage V _IN is obtained at the voltage output terminal 6.

FIG. 11 is a circuit diagram of still another embodiment of the present invention. In this embodiment, the MOS transistors 7, 8, 4 in the embodiment shown in FIG.
Instead of the voltage buffer circuit 42 consisting of
In addition to MOS transistors 7, 8, and 41, N
An enhancement type MOS transistor 43 in the channel and a depletion type MOS transistor in the P channel.
A new voltage buffer circuit 45 is constructed by adding a MOS transistor 44. That is, the drain electrode D of the newly added MOS transistor 43 is connected to the drain electrode D of the MOS transistor 41, the source electrode S and substrate electrode B are connected to the terminal 6, and the gate electrode G is connected to the terminal 4. Other added to
The source electrode S of the MOS transistor 44 is connected to the terminal 6, the drain electrode D is connected to the _VSS application point, the substrate electrode B is connected to the _VDD application point, and the gate electrode G is connected to the terminal 4.
are connected to each.

That is, in this embodiment, two sets of voltage buffer circuits as in the embodiment shown in FIG. 4 are provided, and two MOS transistors 1,
2, supplying the analog input signal IN before passing through
By supplying the analog output signal OUT after passing through MOS transistors 1 and 2 as the other input, the voltage at the voltage output terminal 6 can be made to respond quickly to changes in the analog input signal voltage V _IN . This is what I did. Also in this embodiment, by providing the MOS transistor 41, the MOS transistor 41 is turned on only when transmitting the analog input signal IN to the terminal 4, and the analog input signal voltage is output to the voltage output terminal 6. This is to obtain a voltage V _p-well corresponding to V _IN .

By the way, as shown in the cross-sectional view of FIG. 6,
The drain region 30 of the MOS transistor 1 is of N type,
Since the P well region 22 is of P type and the substrate 21 is of N type, the drain region 30 is an emitter region, the P well region 22 is a base region, and the substrate 21 is a collector region as shown in FIG. A bipolar transistor Q of the type Q is equivalently generated. If a large current flows between the source and drain of the MOS transistor in the state where the bipolar transistor Q is generated, a large voltage drop will occur due to the on-resistance of this MOS transistor 1, and the voltage in the drain region 30 will drop from the source to the drain. It is much lower than in area 29. Since a voltage corresponding to the voltage V _IN of the source region 29 is supplied to the P well region 22 by the voltage buffer circuit 5, a state in which the base and emitter of the bipolar transistor Q is forward biased occurs. At this time, the bipolar transistor Q is turned on, but since the substrate 21 is maintained at V _DD , wasteful current flows to the drain region 30 through the bipolar transistor Q, resulting in an increase in current consumption. will increase.

FIG. 13 is a circuit configuration diagram of another embodiment of the present invention, which prevents an increase in current consumption when a large current flows between terminals 3 and 4 as described above. In this embodiment, instead of the P channel MOS transistor 41 in the embodiment circuit shown in FIG.
A transistor 46 is provided, and an N-channel enhancement type MOS transistor 4 whose gate electrode G is connected to the terminal 4 is provided between the MOS transistor 46 and the MOS transistor 7.
A voltage buffer circuit 49 is constructed by inserting a P-channel depletion type MOS transistor 48 inserted between the voltage output terminal 6 and V _SS and having its gate electrode G connected to the terminal 4. It was designed to do so. That is, in this embodiment, the operation of the voltage buffer circuit 49 is controlled by turning on or off the MOS transistor 46 using the clock signal φ.
A MOS transistor 47 is provided and this gate electrode G
The analog output signal voltage V _OUT is supplied to the gate electrode G by connecting the terminal 4 to the terminal 4.
The voltage of the source electrode S of the MOS transistor 47, that is, the voltage of the drain electrode D of the MOS transistor 7, is always kept below the analog output signal voltage V _OUT . Therefore, the voltage at _the base region of the bipolar transistor Q in FIG. Note that the depletion type MOS transistor 48 discharges the capacitor 9 connected to the voltage output terminal 6 to generate a voltage.
This is provided to increase the speed when lowering V _p-well to around 0V.

Note that the present invention is not limited to the above-mentioned embodiment; for example, in the embodiment circuit shown in FIG.
We have explained the case where the gate electrodes G of the MOS transistors 7 and 8 are both connected to the terminal 3 and the analog input signal IN is supplied to the gates of the MOS transistors 7 and 8. G may also be connected to terminal 4 to provide an analog output signal OUT.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to provide an analog switch device that can maintain a constant resistance value between input and output terminals and can obtain an output signal with less distortion.

[Brief explanation of drawings]

Figure 1 is a circuit configuration diagram of a conventional analog switch device, Figure 2 is a cross-sectional view of the structure of a MOS field effect transistor that constitutes the device, Figure 3 is a characteristic diagram of the conventional device, and Figure 4 is the invention. 5 is a specific diagram thereof, FIG. 6 is a sectional view showing the element structure when the circuit shown in FIG. 5 is integrated, and FIGS. 7 and 8 are respectively for the above embodiment FIG. 9 is a characteristic diagram of the embodiment device shown in FIGS. 5 and 6, FIG. 10 is a circuit configuration diagram of another embodiment of the present invention, and FIG. 11 is a characteristic diagram of the embodiment shown in FIGS. FIG. 12 is a circuit configuration diagram of still another embodiment of
FIG. 13 is a diagram showing a state in which a bipolar transistor is equivalently generated in the cross-sectional view of the figure, and is a circuit configuration diagram of another embodiment of the present invention. 1, 7, 43, 46, 47... N-channel enhancement type MOS field effect transistor,
2,41...P channel enhancement type
MOS type field effect transistor, 3... Analog input signal supply terminal, 4... Analog output signal extraction terminal, 5, 42, 45, 49... Voltage buffer circuit (voltage conversion means), 6... Voltage output terminal , 8, 44, 48... P channel depletion type MOS field effect transistor, 9...
Parasitic capacitance, 21...N-type semiconductor substrate, 22...P
Well region, 23, 26, 27, 29... Source region, 24, 25, 28, 30... Drain region, 31... Contact region, S... Source electrode, D... Drain electrode, G... Gate electrode , B
...Substrate electrode.

Claims (1)

[Claims] 1. A source electrode and a drain electrode for inputting an analog signal or for outputting the analog signal, and a gate electrode and a substrate electrode for inputting a control signal for conducting conduction control are provided. A first MOS type field effect transistor for a switch; and a voltage corresponding to the input analog signal voltage or output analog signal voltage is supplied to the substrate electrode of the first MOS type field effect transistor, and the voltage of the input analog signal is a voltage conversion circuit that minimizes a change in the resistance of the first MOS field effect transistor for the switch in response to a change in resistance and minimizes distortion of the output analog signal, the voltage conversion circuit having one power supply and a voltage output a second N-channel enhancement type MOS field effect transistor inserted between the terminal and the input analog signal or the output analog signal is supplied to the gate electrode; and between the voltage output terminal and the other power supply. An analog switch device comprising: a P-channel depletion type third MOS field effect transistor which is inserted and the input analog signal or the output analog signal is supplied to the gate electrode. 2. A first switch for the switch, which is provided with a source electrode and a drain electrode for inputting an analog signal or for outputting this analog signal, and a gate electrode and a substrate electrode for inputting a control signal for conducting conduction control. A voltage according to the input analog signal voltage or the output analog signal voltage is supplied to the substrate electrode of the MOS type field effect transistor and the first MOS type field effect transistor, so that the voltage for the switch in response to the voltage change of the input analog signal is controlled. and a voltage conversion circuit that minimizes a change in resistance of the first MOS field effect transistor, the voltage conversion circuit being inserted between one of the power supplies and the voltage output terminal to signal the input analog signal or the output analog signal. is inserted between the voltage output terminal and the other power source, and the input analog signal or the output analog signal is supplied to the gate electrode. a third MOS field effect transistor of the depletion type with a P channel, which is inserted between one power source and the voltage output terminal, and the fourth MOS field effect transistor with the P channel is of the enhancement type, and the control signal is inputted to the gate electrode. An analog switch device comprising a MOS field effect transistor.