JPH0226843U - - Google Patents
Info
- Publication number
- JPH0226843U JPH0226843U JP10518888U JP10518888U JPH0226843U JP H0226843 U JPH0226843 U JP H0226843U JP 10518888 U JP10518888 U JP 10518888U JP 10518888 U JP10518888 U JP 10518888U JP H0226843 U JPH0226843 U JP H0226843U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- digital signal
- receiving
- signal
- metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 3
- 238000012360 testing method Methods 0.000 claims 5
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Description
第１図は本考案実施例装置のブロツク構成図。
第２図は本考案実施例装置の接続方法の一例を示
す図。第３図は本考案実施例装置の実装形態を示
す斜視図。
１……操作部、２……送信回路、３……受信回
路、４……表示部、５……変調回路、６……出力
端子、７……入力端子、８……復調回路、９……
制御回路。
FIG. 1 is a block diagram of an apparatus according to an embodiment of the present invention.
FIG. 2 is a diagram showing an example of the connection method of the device according to the present invention. FIG. 3 is a perspective view showing an implementation form of the device according to the present invention. DESCRIPTION OF SYMBOLS 1... Operation unit, 2... Transmission circuit, 3... Receiving circuit, 4... Display unit, 5... Modulation circuit, 6... Output terminal, 7... Input terminal, 8... Demodulation circuit, 9... …
control circuit.
Claims (1)
試験用のデイジタル信号を発生する送信回路と、 上記試験用のデイジタル信号またはこのデイジ
タル信号と同等の信号が被試験回線を介して到来
する信号を受信してエラービツトを検出する受信
回路と、 この受信回路の検出情報を表示する表示部とが
一つの筐体に実装されたエラービツト測定器にお
いて、 上記送信回路が発生するデイジタル信号をメタ
リツク回線に送信する信号に変調する変調回路と
、 この変調回路の出力信号をメタリツク通信回線
に直接接続する送信端子およびメタリツクケーブ
ル通信回線に直接接続する受信端子と、 この受信端子に到来するデイジタル信号を復調
して上記受信回路に与える復調回路と、 上記送信回路、上記受信回路、上記変調回路お
よび上記復調回路を共通に上記操作部の入力にし
たがつて制御する制御回路と が上記一つの筐体内に実装されたことを特徴とす
るエラービツト測定器。[Scope of Claim for Utility Model Registration] An operating unit for setting and inputting test conditions by operation; a transmitting circuit that generates a digital signal for testing according to the test conditions input to the operating unit; and a digital signal for testing as described above. A receiving circuit that receives a signal or a signal equivalent to this digital signal via the line under test and detects error bits, and a display section that displays detection information of this receiving circuit are mounted in one housing. A modulation circuit that modulates the digital signal generated by the transmission circuit into a signal to be transmitted to the metallic line, a transmission terminal that directly connects the output signal of this modulation circuit to the metallic communication line, and a metallic cable communication line. a receiving terminal directly connected to the receiving terminal; a demodulating circuit that demodulates the digital signal that arrives at the receiving terminal and supplies it to the receiving circuit; and the transmitting circuit, the receiving circuit, the modulating circuit, and the demodulating circuit are commonly connected to the operating section. An error bit measuring device characterized in that a control circuit for controlling according to the input of the error bit is mounted in the one housing described above.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10518888U JPH0226843U (en) | 1988-08-08 | 1988-08-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10518888U JPH0226843U (en) | 1988-08-08 | 1988-08-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0226843U true JPH0226843U (en) | 1990-02-21 |
Family
ID=31337575
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10518888U Pending JPH0226843U (en) | 1988-08-08 | 1988-08-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0226843U (en) |
-
1988
- 1988-08-08 JP JP10518888U patent/JPH0226843U/ja active Pending
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