JPH02269478A - Inverter circuit and its control - Google Patents

Abstract

PURPOSE: To eliminate the dependence on the cosϕ and on the direction of a current by bringing only the semiconductor switching element of one phase into a conducting state and at the same time closing the other semiconductor switching element regardless of the operation signal. CONSTITUTION: This circuit is provided with two semiconductor switching elements 1, 2 connected in series between two poles of a DC power source, and provided with a control circuit 6 for operating the semiconductor switching elements 1, 2 by a pulse width modulation operation signal 11. Only the semiconductor switching elements 1, 2 of one phase are controlled into a conducting state and at the same time the other semiconductor switching elements 2, 1 are closed independently of the operation signal 11 in such a manner that the control circuit connects the pole of the DC power source having a polarity corresponding to the polarity of the current flowing into an AC output terminal 5 to the AC output terminal 5 by the operation signal 11. Therefore, a predetermined output voltage can be generated regardless of the cosϕ given by the load and regardless of the direction of the current.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an inverter circuit for converting direct current from a direct current source into at least single-phase alternating current. comprising two semiconductor switching elements for each phase connected in series, a recovery diode in parallel with each semiconductor switching element being arranged in a blocking direction with respect to the DC source and an AC output terminal between the two semiconductor switching elements; The semiconductor switching device is further provided with a control circuit for operating the semiconductor switching element using a pulse width modulated operating signal. The invention also provides an inverter circuit for converting direct current into at least one phase alternating current, comprising two semiconductor switching elements connected in parallel, in each phase, a recovery diode connected between two poles of the direct current source. An alternating current can be extracted from an alternating current output terminal between two semiconductor switching elements, and the semiconductor switching elements are operated by a pulse width modulated operating signal.

PRIOR ART An inverter circuit (US Pat. No. 4,617,622) is known which is operated by a pulse width modulated signal and a control circuit. The signals of this control circuit can take logical values of 0 and 1. At a value of 1, the semiconductor switching element connected to the positive pole of the DC source is in a conductive state, and a semiconductor switching element connected to the negative pole is in a cut-off state, and at a value O, the opposite is true. Action occurs on a rising or falling edge of the operating signal. The scanning ratio, ie the ratio of the duration during which the signal has the value l in one period to the total length of the period, governs the voltage at the AC output terminal. The voltage at the AC output terminal, which refers to the voltage at the negative pole of the DC source, corresponds to the product of the voltage difference between the two poles of the DC source and the scanning ratio. If the DC source is constructed symmetrically, ie the voltage at the negative pole is exactly the same as the voltage at the positive pole, then a zero voltage is obtained at the AC output terminal with a scanning ratio of 0.5. By varying the scan ratio over time, for example in the form of a sinusoid, if the period of the pulse width modulation is considerably shorter than the period of the sinusoid, then
The output voltage of the inverter can be changed over time. That is, the modulation frequency must be significantly higher than the alternating current frequency.

In the ideal case, the output voltage of the inverter is exactly proportional to the scan ratio of the pulse width modulated signal. However, in reality,
All controllable semiconductor switching elements require some time to turn off. This switching off time is defined as the period from the moment when the switching element is to be turned off by an operating signal, for example by a transition from the value 1 to the value 0, to the moment when the current flowing through the switching element disappears, i.e. when the switching element is turned off. It is calculated up to the moment when the element is actually turned off. In contrast, the switching-off time, ie the time from before the arrival of the "manipulation" signal due to the rising edge of the manipulation signal, for example from the value O to the value 1, until the full current is reached is significantly shorter. This phenomenon is particularly noticeable for certain types of bipolar transistors.

Thus, in U.S. Pat. No. 4,617,622, each control line is provided with a time period prior to the ignition of each semiconductor switching element that must be at least equal to the switching-off time of the other switching element. That is, a delay means is provided to delay the start of the operation. When the delay time is to be shortened, one switching element is operated while the other switching element is not yet closed, and for each operation there is a short circuit between the poles of the DC source. To prevent harmful harmonics, another delay element is introduced in the signal path of the pulse width modulated operating signal, the delay of which is variable and reduced proportionally to the load current. For positive currents, the delay occurs only on falling edges, and for negative currents, only on rising edges. This scheme is particularly suitable for compensating for linear current dependence in the switching off time of semiconductors.

The switching-off time of a semiconductor switching element depends on the type and manufacturing method of the semiconductor, statistical variations, i.e., differences between individual samples of semiconductors of the same type and manufacturing method, temperature changes, and the fact that the switching-off time increases with increasing temperature. It varies widely depending on many factors such as , load current, etc. Also, there must be a sufficient safety margin such that under most operating conditions the ignition delay is considerably longer than the actual switching-off time of the semiconductor. Each delay means typically delays the operating signal by a time three to four times longer than the actual switching-off time of the semiconductor.

(Problems with the Prior Art) However, as a result of the delay time being too long, the actual scan ratio does not match the desired scan ratio, and as a result, the output voltage of the inverter does not follow exactly as prescribed. The positive current flowing to the inverter output is smaller than the desired value, and the negative current flowing to the inverter output is larger than the desired value. negative current direction means that current flows into the inverter output.When the inverter has a resistive load, that is, when the current and voltage When there is no phase difference between
sφ=0), the amplitude of the output voltage matches the predetermined voltage.

This phenomenon is particularly disadvantageous when operating asynchronous motors at variable frequencies. Particularly at low frequencies, where the amplitude of the fundamental voltage is also low, even a small voltage loss will be catastrophic, since the motor torque will be greatly reduced at extremely low voltages.

However, it is known that large torque is desirable, especially when starting from a stopped state. Usually, the problem is solved by correcting the scan ratio of the pulsed browning 1m signal in the control circuit to increase the voltage. Although this alleviates the problem of excessively low torque, when the torque decreases CaSφ decreases, resulting in excessively high voltage being supplied to the motor under no-load conditions. the result,
The motor requires unreasonably high idling current at low frequencies, which increases the risk of overheating. In ordinary 1xR compensation, where the voltage is increased according to the load current, the current and C
Since there is no clear relationship with O3-, the problem remains unsolved. Attempts have also been made to lower the modulation frequency of pulse width modulated steering signals. However, it is still preferable to keep the modulation frequency as high as possible, as this will increase losses and motor noise.

(Object of the invention) Therefore, the object of the invention is to
The object of the present invention is to provide an inverter circuit of the above-mentioned type that can generate a predetermined output voltage independently of φ and independently of the direction of the current.

(Structure of the Invention) This object of the present invention is to provide an inverter circuit of the type described above, in which a control circuit, in response to an operation signal, outputs a pole of a DC source having a polarity corresponding to the polarity of a current flowing through an AC output terminal. This problem can be solved by controlling only the semiconductor switching element of one phase to be in a conductive state so as to be connected to the terminal, and configuring the other semiconductor switching element to be closed regardless of the operation signal.

Therefore, according to the present invention, since no short circuit occurs between the positive and negative electrodes of the DC source, the semiconductor switching element can be operated without considering the occurrence of a short circuit. Therefore, it is not necessary to provide an excessively long delay in the signal path of the operating signal in order to change the scanning ratio, so that the output voltage can more accurately follow the desired course. Since no voltage loss occurs, there is no dependence of such loss on cosφ or current direction.

In a preferred embodiment, the control circuit comprises blocking means, which are opened by the control logic to allow the operating signal to act on the semiconductor element or to be blocked, depending on the polarity of the current at the AC output terminal. . When the blocking means is opened, the means open the signal path for the operating signal, which then influences the control electrode of the semiconductor switching element. This embodiment makes it possible to control the inverter circuit very simply. The operation signal can be generated in a conventional manner. No complicated modifications to the operating signal generator are necessary. If this is not desirable due to the state of the circuit, the operating signal is simply prevented from reaching the semiconductor switching element.

The interrupting means is formed by an AND gate, the output terminal of which is connected to the corresponding control electrode of the associated semiconductor switching element, and one input terminal of the semiconductor switching element is connected to one input terminal of the semiconductor switching element.
It is advantageous to actuate the operating signal for the associated semiconductor switching element and to actuate the output signal of the control logic on the other input terminal. AND gates are particularly simple to use as blocking means. As long as a signal corresponding to this one input terminal, for example a logic 1, acts, the signal of the other input terminal appears at the output terminal. On the other hand, when a logical value O is supplied to the first input terminal of the AND gate. Regardless of the source of the signal at the other input terminal,
This value 0 appears at the output terminal.

Advantageously, each delay means arranged between each disconnection means and the associated semiconductor switching element delays the part of the operating signal which causes the operation of the semiconductor switching element by a predetermined delay time. The part of the operation signal that operates the semiconductor element is, for example, a rising edge for the semiconductor switching element that connects the positive pole of the DC source to the output terminal of the inverter, and the part of the other semiconductor that connects the negative pole of the DC source to the output terminal of the inverter. As for the switching element, it is, for example, the falling edge of the operating signal. This configuration has the following advantages: That is, when the switching-on time, that is, the time from the arrival of each edge of the operating signal to the full current, is significantly shorter than the switching-off time, the scan ratio will be greater than the desired value, resulting in an excessively high output voltage. This phenomenon appears at the output terminal of the inverter, but by providing a delay time, this phenomenon can be significantly corrected.

It is advantageous if the delay means can be switched between short and long delay times.

As already mentioned, the switching-off time depends inter alia on the strength of the current. Depending on the load, short or long delay times can be selected for the switching-off correction time if the dependence of the switching-off time on different currents has to be taken into account.

However, depending on the polarity of the current at the output terminal of the inverter, it is particularly advantageous to carry out the switching by means of the control logic, so that the delay means for the semiconductor switching elements to be rendered conductive are switched to a short delay time. This ensures that it is the switching elements that are always to be instantaneously turned on that are affected by the short delay time. If the other semiconductor switching element is switched inadvertently during the next change in the level of the operating signal, i.e. during a rising edge or a falling edge, the switching there will occur over a correspondingly long delay time. Because it occurs,
Here, too, short-circuit conditions can be reliably prevented.

In a narrow current range of about 0, it is often difficult to determine the polarity of the current. For this purpose, at values of the alternating current within a predetermined range above and below zero, the control logic opens the disconnection means of both semiconductor switching elements.

As a result, both switching elements are supplied with an operating signal, but since the current is virtually constant, no losses occur.

Advantageously, when both blocking means are opened, the control logic switches the delay means to a long delay time. In that case, for safety reasons, one semiconductor switching element can only be ignited when the other is securely closed. The loss that occurs at this time does not cause the problem as described above because no current is actually flowing.

The control logic includes means for detecting the direction and amount of current flowing through the output terminals of the inverter and for generating a release signal for one of the two interrupting means when the current is not less than zero and for generating a release signal for one of the two interrupting means when the current is not less than zero. Advantageously, a comparison means is provided, which sometimes generates a release signal for the other blocking means. Therefore, both signals are generated when the current is substantially zero. This is a simple way to ensure that the two-handed conductor switching element operates in a narrow range of current values around zero.

Preferably, the release signal for the cut-off means of one semiconductor switching element causes the delay means of the other semiconductor switching element to change from a short delay time to a long delay time. As a result, both cut-off means are opened, so that at the moment when an actuating signal can be applied to both semiconductor switching elements, a switch is always made to a long delay time.

In a preferred embodiment, the inverter circuit produces three phases of alternating current, each electrically 120 degrees out of phase.

This embodiment is particularly advantageous for use with asynchronous three-phase AC motors.

In a method of the aforementioned kind, as long as the current at the output terminals of the inverter has one polarity, the operating signal is supplied only to the semiconductor switching elements that connect the AC output terminals to the poles of the same polarity, and to the other semiconductor switching elements. The problem is solved by keeping the signal blocked.

(Embodiments) Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings showing a single-phase inverter.

The inverter shown in the accompanying drawing has two poles of DC source U+,
Two semiconductor switching elements connected in series between U! , 2. Each semiconductor switching element1.
In parallel with 2, a recovery diode 3.4 is provided in each case. Both recovery diodes 3.4 have a blocking polarity with respect to the voltage direction of the DC source. An alternating current can be connected to the inverter output terminal 5 between these two semiconductor switching elements.

An operation signal is inputted to each semiconductor switching element 1.2 by the control circuit 6. The control circuit 6 has an operation signal generator 7 that generates an operation signal 11 . This operation signal is
It is a pulse width modulation signal that takes two logical values of 0.1. One of the semiconductor switching elements 1, which connects the positive pole U of the DC source to the AC output terminal 5, becomes conductive due to the change in the operating signal from level O to level 1, that is, is ignited or operated, and connects the negative pole U of the DC source to the AC output terminal 5. - is connected to the AC output terminal 5, and the other semiconductor switching element 2 is ignited or operated by the change from level 1 to level 0. After ignition, the operated semiconductor switching element 1.2 returns from 1 to 0 for semiconductor switching element 1 and from 0 to 1 for semiconductor switching element 2 until the operating signal changes the level again. Until it is restored, it continues to carry current, that is, remains open. To enable the use of the same semiconductor switching elements, the operating signals for the semiconductor switching elements 2 are inverted by an inverter 19. However, a rising edge or a falling edge does not immediately switch off the respective semiconductor switching element 1.2, but only causes a switch-off. There is a so-called "switching-off time" between the occurrence of this edge and the actual interruption (ie, the cessation of all current through the respective semiconductor element).

The operating signal 11 is not applied directly to the firing electrode of the semiconductor switching element. Each semiconductor switching element is provided with an ignition delay means 12.13, which is connected to the control electrode of the respective semiconductor switching element 1.2. The ignition delay means 12.13 receive and receive a human input signal from the shutoff means 8.9 in the form of an AND gate. Each gate has two input terminals, one of which receives the operating signal 11 from the generator 7. The other input terminal of the disconnection means 8.9 is connected to the control logic 1.
Connected to 0. The control logic 10 generates a signal at the output terminal 17 that indicates that the current is not less than zero (
(ie, greater than or equal to zero), it takes a logic 1 value. This signal is supplied to the interrupting means 8 of the semiconductor switching element l, which is connected to the positive pole of the DC source. The other output terminal of the control logic 10 is activated when the current is not greater than zero, i.e. less than or equal to zero.
Outputs a logic 1 signal. This signal is supplied to the cut-off means 9 of the semiconductor switching element 2, which is connected to the negative pole of the DC source. Output lines 17 and 18 output a logic 0 when not outputting a logic 1 value. Control logic 10 connects AC output terminal 5 to generate a signal on output line 17.18.
It has a current converter 14 that detects the strength and polarity of the alternating current. The signal obtained by the current converter 14 is supplied to an abbreviated comparator 15 that determines whether the current is less than or equal to zero, and an abbreviated comparator 16 that determines whether the current is greater than or equal to zero. be done. Both comparators 15.
16, when the result of the above comparison is yes, i.e.
A logic 1 signal level is generated when the condition is met, and a logic 0 signal level is generated otherwise.

The ignition delay means 12.13 can be switched between two different delay times of different lengths. This switching is effected by a signal on output line 17.18 of control logic 10. When the comparator 15 determines that the current is less than or equal to zero, the delay time of the delay means 12 is set to a long value.

When the comparator 15 determines that the condition is not satisfied,
That is, when it is determined that the current is greater than zero, the delay means 12 is set to a short delay time. The delay means 13 is set to a long delay time when the comparator 16 determines that the current is greater than or equal to zero. on the other hand,
The delay time of the delay means 13 is set to a short value when the comparator 16 determines that the current is smaller than zero.

Assume that an inverter is used to generate an approximately sinusoidal alternating current at the alternating current output terminal 5. The operating signal generator 7 generates a pulse-width modulated operating signal 11, which is fed to two blocking means 8.9. Semiconductor switching element 1 that connects the positive pole U of the DC source to the AC output terminal 5
The interrupting means 8 are opened only when the control logic 10 detects that the current at the AC output terminal 5 is greater than or equal to zero. In this case, the operating signal 11 can reach the control electrode of the semiconductor switching element 1 via the delay means 12, so that the semiconductor switching element 1 is operated.

Current can therefore flow from the positive pole U+ of the DC source to the AC output terminal 5, where a positive current, ie a current flowing out of the inverter, is generated. Depending on the duration of the operating pulse of the operating signal 11, the semiconductor switching element I is closed again after a predetermined time. After a slight delay, that is, after the switching-off time has elapsed, the current from the positive electrode U+ of the DC source to the AC output terminal 5 stops. In a resistive load where the current and voltage are in phase, the current stops altogether.

However, when there is an inductive load on the AC output terminal 5, the current tends to continue flowing. Therefore, as long as the upper semiconductor switching element 1 is closed, current flows from the negative pole U- of the DC source to the AC output terminal 5 via the recovery diode 4. While the positive current is flowing to the AC output terminal 5, the lower semiconductor switching element 2 remains closed. The scanning ratio of the operation signal is changed somewhat sinusoidally.

Therefore, in the positive half-wave, the pulses operating the upper switching element 1 are longer than the pauses between pulses.

Therefore, the voltage at the AC output terminal 5 also changes sinusoidally. While the current at the AC output terminal 5 is in the positive half wave, only the semiconductor switching element 1 is operated. The semiconductor switching element 2 remains permanently switched off. In any case, no short circuit occurs between the positive pole U and the negative pole U- of the DC source.

At the end of the positive half wave, the current at the AC output terminal approaches zero.

In this range, the current converter 14 can no longer reliably determine whether the direction of the current is positive or negative. Therefore,
The control logic produces a logic one signal on both of its output terminal lines 17,180. As a result, both blocking means 8.9 for the control signal are made conductive. Operation signal 11
both semiconductor switching elements 1. through delay means 12.13 which are both switched to a long delay time.
The second control electrode is reached. Semiconductor switching elements are
It is normally operated for a short period of time, ie the time required for the current to leave a narrow range around the zero value in the negative direction. Thereafter, the current converter 14 can again reliably determine that only negative current flows through the AC output terminal 5, ie that current flows from the load into the inverter.

During the negative half wave, the cutoff means 8 is cut off for the upper semiconductor switching element 1, and the operation signal 11 is transmitted to the cutoff means 9.
It only reaches the semiconductor switching element 2 via the delay means 12 and the delay means 12. The switching elements 1.2 are operated alternately even though the effective value of the current at the AC output terminals is equal to zero.

In an inductive load, there is a phase difference between the current and voltage. In this case, a situation may occur where a positive voltage is applied to the load and a negative current is flowing. While negative current is flowing,
Since no current flows through the semiconductor switching element 1, it is immaterial whether the semiconductor switching element 1 can be operated or not. In this case, the required current is supplied via the recovery diode 4 which is connected in parallel to the lower semiconductor switching element 2. In the opposite case,
When the voltage is primarily negative and the current is positive, the current distribution is exactly the opposite. That is, the upper recovery diode 3 conducts current, but it is immaterial whether the lower semiconductor switching element 2 can be operated or not. The operation signal 11 is supplied to the semiconductor switching element 1 to intermittently create a conductive connection state between the positive terminal U+ of the DC source and the AC output terminal 5 when the current becomes positive again. This is only when switching element 1 is also able to conduct current.

The delay means 12.13 can in principle be omitted. However, in most cases, the switching-off time is longer than the switching-on time, so the scanning ratio, and therefore the output voltage of the inverter, will be larger than the desired value.

Therefore, the delay means 12.13 has a delay corresponding to the switching-off time of the semiconductor switching element 1.2. However, the delay time should not be set too large, thereby preventing a transient dead period. The exception is in regions where the current has a value approximately equal to zero. In this range, it is difficult for the current converter 14 to determine whether the polarity of the current is positive or negative. Therefore,
The blocking means 8.9 are both opened and the operating signal 11 is sent to both semiconductor switching elements 1.2. Even in this operating state, in order to prevent a short circuit from occurring between the poles U+ and U- of the direct current source, the delay means 12.13 is activated for a long delay time, i.e. for the switching off time of the semiconductor switching element 1.2. Set to a delay time that is a multiple. The delay means is always connected to the other semiconductor switching element 1.
．． 2 is operated depending on the state of the interrupting means associated with both delay means 12.13, even if both interrupting means 8.9 send a control signal 11 to the semiconductor switching element 1.2. It is guaranteed that a long delay time will always be set.

Naturally, the scanning ratio of the operating signal 11 can vary according to any function of time, producing, over time, an inverter output voltage that varies according to the same function of time.

In either case, it is possible to reliably generate an inverter output voltage that substantially corresponds to the desired voltage while preventing short circuits from occurring between the poles of the DC source.

[Brief explanation of drawings]

The figure is a block diagram of a single-phase inverter. 1.2...Semiconductor switching element, 3.4...
・Recovery diode, 5: AC output terminal, 6: Control circuit, 8.9: Cutoff means, 0: Control logic, 1: Pulse width modulation operation signal, 2.13... Ignition delay means, 4... Current converter, 5.16... Comparator.

Claims (12)

[Claims] (1) An inverter circuit for converting direct current from a direct current source into at least one phase of alternating current, comprising two semiconductor switching elements for each phase connected in series between two poles of the direct current source. , a recovery diode in parallel with each semiconductor switching element is arranged in a blocking direction with respect to the DC source and an AC output terminal is arranged between the two semiconductor switching elements; The control circuit (6) includes a control circuit for operating the element, and the control circuit (6) connects the pole of the DC source with the polarity corresponding to the polarity of the current flowing through the AC output terminal to the AC output terminal (5) according to the operation signal (11). controlling only the semiconductor switching elements (1, 2) of one phase to be in a conductive state so as to connect the semiconductor switching elements (1, 2) to the conductive state, and closing the other semiconductor switching element (2, 1) independently of the operation signal (11). An inverter circuit featuring: (2) the control circuit is opened by the control logic (10) depending on the polarity of the current at the AC output terminal (5);
The operation signal (11) is transferred to the semiconductor switching elements (1, 2)
An inverter circuit according to claim 1, characterized in that it comprises interrupting means (8, 9) which are switched over or shut off. (3) The cutoff means (8, 9) consist of an AND gate, the output terminal of which is connected to the control electrode of the associated semiconductor switching element (1, 2), and one input terminal of which is connected to the control electrode of the associated semiconductor switching element (1, 2). Semiconductor switching elements (1, 2)
3. The inverter circuit according to claim 2, wherein the inverter circuit is configured to be influenced by an operation signal (11) for one input terminal, and the other input terminal is influenced by an output signal of the control logic (10). (4) Between each of the cutoff means (8, 9) and the associated semiconductor switching element (1, 2), the portion of the operation signal that causes the operation of the semiconductor switching element is delayed by a predetermined delay time. The inverter circuit according to claim 2 or 3, further comprising delay means (12, 19). (5) The inverter circuit according to claim 4, wherein the delay means (12, 13) are configured to be switchable between a short delay time and a long delay time. (6) The delay means (12, 13) are switched according to the control logic (
10) delay means (12, 13) of the semiconductor switching elements (1, 2) to be rendered conductive;
6. The inverter circuit according to claim 5, wherein is switched to a short delay time. (7) characterized in that, at alternating current within a predetermined range above and below zero, said control logic (10) is configured to open said cutoff means (8, 9) of both said semiconductor switching elements; The inverter circuit according to any one of claims (2) to (6). (8) When both said shut-off means (8, 9) are opened, said control logic (10) controls said delay means (12, 13).
) The inverter circuit according to claim 7, wherein the inverter circuit is configured to switch the delay time to a long delay time. (9) The control logic (10) is connected to the AC output terminal (5).
) for detecting the direction and amount of current flowing through the circuit (14) and generating a release signal for one of the interrupting means (8) when said current is not less than zero and for the other one when said current is not greater than zero. Inverter circuit according to any one of claims 2 to 8, characterized in that it comprises comparison means (15, 16) for generating a release signal for the cut-off means (9). (10) One of the semiconductor switching elements (1, 2)
The delay means (13, 12) of the other semiconductor switching element (2, 1) are configured to be switched from a short delay time to a long delay time by a release signal for the cutoff means (8, 9) of the other semiconductor switching element (2, 1). The inverter circuit according to claim 9, characterized in that: (11) The inverter circuit has an electrical phase of 120
The inverter circuit according to any one of claims 1 to 10, wherein the inverter circuit generates three-phase alternating currents that are shifted by degrees. (12) Each phase has two semiconductor switching elements,
Controlling an inverter circuit according to any one of claims 1 to 11 for converting direct current into at least single-phase alternating current, wherein the parallel-connected recovery diodes are connected between two poles of the direct current source. The method includes: wherein the alternating current is drawn from the alternating current output terminal between two of the semiconductor switching elements, the semiconductor switching elements being operated by a pulse axis modulated operating signal, and wherein the current has one polarity at the alternating current output terminal. The inverter circuit is characterized in that, while the AC output terminals are connected to the same polarity, the operation signal is supplied only to the semiconductor switching elements that connect the AC output terminals to the same polarity, and the other semiconductor switching elements remain cut off. Control method.