JPH02271676A - Mis semiconductor device - Google Patents

Abstract

PURPOSE:To prevent junction breakdown from being produced even when a title device is used in an input/output circuit, etc., by providing an electric field concentration electrode in contact, via an insulation film, with a relatively high concentration impurity region in a drain area. CONSTITUTION:An electric field concentration electrode 41 is provided, which makes contact with, via an insulating film 31, with a relatively high concentration impurity region 27. An originally narrow width depletion layer around the relatively high concentration impurity region 27 in a drain region 17 is further narrowed by an electric field concentration electrode 41, and the electric field is concentrated there. Accordingly, even though the drain region 17 includes a relatively low concentration impurity region 44 and the relatively high concentration impurity region 27, junction yield can be produced uniformly along the electric field concentration electric field concentration electrode 41. Hereby, junction breakdown is difficult to be produced even through the device is used in an input/output circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an MIS type semiconductor device in which at least a drain region has a relatively low concentration impurity region and a relatively high concentration impurity region. It is something.

[Summary of the invention]

The present invention provides an input/output circuit, etc. in the MIS type semiconductor device as described above by providing an electric field concentration electrode in contact with a relatively high concentration impurity region of the drain region via an insulating film. It is designed so that joint failure is unlikely to occur even when used for.

[Conventional technology]

4 to 6 show input and output circuits commonly used in MOS-ICs.

FIG. 4 shows an input circuit 13 disposed between the input pad 11 and the internal circuit 12.
is a protective nMOS transistor 14 and a resistive element 15.
and a stray capacitance element 16.

In this state, when a positive high voltage pulse as shown in FIG. 7 is input to the input pad 11, as shown in FIG. At the same time, the drain region of the nMOS transistor 14 breaks down, reducing the input pulse to the breakdown voltage. The internal circuit 12 is protected by clamping it to .

FIG. 9 shows the state of the nMOS transistor 14 at this time. That is, when a positive pulse is input to the capacitor 11, the depletion layer 18 around the drain region 17 expands, but the width of the depletion layer 18 is narrow under the gate electrode 21 due to the electric field caused by the gate electrode 21.

Then, the electric field is concentrated in this part, and junction breakdown is more likely to occur in this part than in other parts. Therefore, junction breakdown occurs uniformly along the gate electrode 14, and the heat generation at the breakdown portion is not very large, so this breakdown is reversible and non-destructive.

On the other hand, when a negative high voltage pulse is input to the input pad 11, the time constant of the resistance element 15 and the stray capacitance element 16 blunts the steep input pulse, and the nMOS transistor 14 conducts in the forward direction. By clamping the input pulse to a low voltage, internal circuitry 12 is protected.

In the input circuit 22 shown in FIG. 5, a CMOS transistor 24 consisting of an nMO3h transistor 14 and a pMO3h transistor 23 serves as a protection transistor.

In this input circuit 22, when a positive high voltage pulse is input to the input pad 11, the nMOS transistor 23 is turned on in the forward direction, and when a negative high voltage pulse is input to the input pad 11, the nMOS transistor 14 is turned on in the forward direction. CR
Coupled with the delay effect due to the time constant, this protects the internal circuit 12.

FIG. 6 shows an output circuit 26 disposed between the output pad 25 and the internal circuit 12. This output circuit 26
The input circuit 22 also functions similarly to the input circuit 22 shown in FIG.

[Problem to be solved by the invention]

However, the input circuit 13.22 and the output circuit 2 as described above
6 nMOS) If LDD structure transistors are used for the transistor 14 and the nMOS transistor 23, the MOS
-Highly reliable MOS-IC with reduced IC electrostatic strength
The problem is that they are not able to obtain
Nikkei Microdevice J 1988.10 P, 10
3-111).

That is, in the nMOS transistor 14 having the LDD structure as shown in FIG. 10, the electric field under the gate electrode 21 is relaxed, so junction breakdown occurs not under the gate electrode 21 (between the n Occurs at the joint.

However, since there is no concentration of electric field due to the gate electrode 21 at this junction, it is not possible to uniformly cause junction breakdown in a predetermined region as in the case shown in FIG. 9.

In other words, junction breakdown occurs in a small area due to crystal defects, non-uniformity of impurity concentration, etc., and current concentrates in this small area. As a result, heat generation in this portion increases, and bond breakdown becomes irreversible, leading to bond failure.

Even in the input circuit shown in FIG. 5 and the output circuit shown in FIG. 6, when a steep high voltage pulse is input, before one of the nMOS transistor 14 and the nMOS transistor 23 becomes conductive in the forward direction, The other may surrender.

In this case, if LDD structure transistors are used for these transistors 14 and 23, junction breakdown will occur as described above, and the electrostatic charge and strength of the MOS-IC will decrease.

To solve this problem, it is conceivable to use transistors with an LDD structure only in the internal circuit 12, and use transistors with a normal structure as shown in FIG. 9 in the input circuits 13, 22 and the output circuit 26. However, this complicates the manufacturing process and increases manufacturing costs.

[Means to solve the problem]

The MIS type semiconductor device according to the present invention includes an electric field concentration electrode 41 that is in contact with a relatively high concentration impurity region 27 via an insulating film 36.

[Effect]

In the Mis type semiconductor device according to the present invention, the drain region 1
The originally narrow depletion layer around the relatively high-concentration impurity region 27 of the electrodes 7 is further narrowed by the electric field produced by the electric field concentration electrode 41, and the electric field is concentrated in this portion.

Therefore, even if the drain region 17 has a relatively low concentration impurity region 44 and a relatively high concentration impurity region 27, junction breakdown can occur uniformly along the electric field concentration electrode 41. I can do it.

〔Example〕

Below, CM with shallow trench isolation
An embodiment of the present invention applied to an OS inverter will be described with reference to FIGS. 1 to 3.

FIG. 1 shows the entire structure of this embodiment, and FIG. 2 shows the manufacturing process of the nMOS transistor part.

In this manufacturing process, as shown in Figure 2A, first the n-type S
A p-well 28 is formed on the i-substrate 31, and a two-layer polycrystalline Si/SiO□ film 32 is formed on the surface of the Si substrate 31, and then shallow trenches 33a and 33b are formed. Channel stoppers (not shown) are formed on the bottom and side surfaces.

Next, the second B
As shown in the figure, the SiO□ film 34 film strip 4 is formed, and as shown in FIG.
Etch back membrane 34.

Next, as shown in FIG. 2D, photoresists 35a and 35b are patterned to cover a predetermined portion of shallow trench 33a and the entire shallow trench 33b.

Next, as shown in FIG. 2E, photoresist 3.5a,
34 SiO□ films not covered by 35b 4 crystals St/
The SiO□ film 32 is removed by etching back, and then the photoresists 35a and 35b are also removed.

Next, as shown in FIG. 2F, a layer of S as a gate insulating film is applied to the exposed portion of the Si substrate 31 where the SiO□ film 34 is not coated.
The entire iO□ film 36 is deposited, and then a polycrystalline Si film 37 is deposited.

At this time, if the dimension w1 in FIG. 2D is made approximately twice the thickness of the polycrystalline Si film 37, the 5iOz film 34 is etched in the shallow trench 33a in the step of FIG. 2E. A crystalline Si film 37 is deposited flatly.

Next, as shown in FIG. 2G, photoresists 38a and 38b are patterned to cover a predetermined portion of the shallow trench 33a and a portion where a gate electrode is to be formed.

Next, as shown in FIG. 2H, photoresists 38a, 3
Using 8b as a mask, polycrystalline Si film 37 and 5iOzll
! By etching 36, the electric field concentration electrode 41 and the gate electrode 21 are formed, and then the photoresists 38a and 38b are removed.

Next, as shown in FIG. 21, n-11 regions 43 and 44 of the source region 42 and drain region 17 are formed, sidewall spacers 45 are formed on the gate electrode 21 and the electric field concentration electrode 41, and the source n4h of region 42 and drain region 17
1 region 46.27 is formed.

Note that the n" region 27 of the drain region 17 and the p well 28
The joint portion with the electrode 41 needs to be located at a shallower position than the electric field concentration electrode 41 in the shallow trench 33a.

Further, it is necessary that the n'' region 27 of the drain region 17 and the electric field concentration electrode 41 be in contact with each other via the 5in2 film 36 on the side surface of the shallow trench 33a. It needs to be located inside the shallow trench 33a.

Therefore, it is necessary to set the dimension w2 in FIG. 2G to a value greater than or equal to the sum of the thickness of the side wall spacer 45 and the alignment error.

Note that although the above manufacturing process is for the nMO3) transistor 14, the pMO3I transistor 23 can also be manufactured by the same process.

Thereafter, wiring to the input path 11 or the output path 25 is performed, and the present embodiment shown in FIG. 1 is completed.

The CMOS inverter of this embodiment is connected to the input circuit 22 of FIG.
To use it, the gate electrode 21 of the nMO3) transistor 14 is grounded, and the gate electrode 47 of the transistor 23 is connected to the power source (2). Connect to.

In addition, this CMOS inverter is connected to the output circuit 26 in FIG.
For use in this case, the gate electrodes 21.47 are connected to each other or separately to the internal circuit 12.

In this embodiment as described above, the junction between the n' region 27 of the drain region 17 and the p well 28 is made of a sinusoid.

Since the electric field concentration electrode 41 is in contact with the membrane 36,
Similar to the case shown in FIG. 9, junction breakdown occurs in the region surrounded by the dashed line in FIG.

In other words, as shown by diagonal lines in FIG. 3, the electric field concentration electrode 4
Joint breakdown occurs uniformly along 1.

This also applies to the area surrounded by the dashed line of the 9MO3) transistor 23 in FIG. Therefore, junction breakdown does not occur ((, M
OS-IC can be manufactured.

Moreover, as is clear from the manufacturing process shown in Figure 2,
MOS-I with shallow trench isolation
If applied to C, there is no need to add any special manufacturing process.
This example can be manufactured.

〔Effect of the invention〕

In the MIS semiconductor device according to the present invention, even if the drain region has a relatively low concentration impurity region and a relatively high concentration impurity region, junction breakdown is uniformly achieved along the electric field concentration electrode. Therefore, even when used in input/output circuits, junction breakdown is less likely to occur.

[Brief explanation of drawings]

Fig. 1 is a side sectional view of one embodiment of the present invention, Fig. 2 is a side sectional view sequentially showing the manufacturing process of the main parts of one embodiment, and Fig. 3 is a side sectional view showing the operating state of the main parts of one embodiment. FIG. 4 and 5 are circuit diagrams of an input circuit to which the present invention can be applied, FIG. 6 is a circuit diagram of an output circuit to which the present invention can be applied, FIG. 7 is a waveform diagram of input pulses, and FIG. 8 is a circuit diagram of an output circuit to which the present invention can be applied. FIG. 3 is a waveform diagram of the output of the input circuit. 9 and 10 are side sectional views of a reference example of the present invention and a conventional example, respectively. In addition, in the symbols used in the drawings, 17-----
・・Drain region 27−・−−−−−−−−−−1−
-------・--・n'' area 36----------
・−・−−−1−・・・・−5in2 membrane 41 −−−
−−−−−・−・−・・−・−・−−1−−Electric excavation 44 for electric field concentration−−−−−−−・−−−1−・−・−・・
-・-・-n− area. Output ports Fig. 6

Claims (1)

[Claims] In an MIS type semiconductor device in which at least a drain region has a relatively low concentration impurity region and a relatively high concentration impurity region, the drain region is insulated from the relatively high concentration impurity region. An MI characterized by comprising an electric field concentration electrode in contact with a membrane.
S-type semiconductor device.