JPH0227322A - Active matrix substrate - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an active matrix substrate used, for example, in combination with a liquid crystal for color display.

(Prior art) Recently, when displaying color using a liquid crystal, a large number of thin film transistors (Th1n FilIIT) are used on an insulating substrate.
An active matrix substrate is used in which transistors (TFT) are arranged in a matrix.

This active matrix substrate has two, for example, an insulating substrate, on which a large number of picture element electrodes are arranged.

Further, a large number of TPTs are arranged in a matrix adjacent to each picture element electrode. The drain electrode of each TPT is electrically connected to each picture element electrode, and each TPT functions as a switching element for each electrically connected picture element electrode.

Each gate electrode of the TPTs arranged in a row in one direction is electrically connected to one gate wiring extending in that direction.

Each source electrode of the TPTs arranged in a row in the other direction is connected to one source wiring extending in that direction.

Then, a scanning signal is inputted to each gate wiring, a data signal is inputted to each source wiring, and the TPT to which the inputted signal is input operates, and a voltage is applied to the pixel electrode connected to the TPT. is applied.

An example of an active matrix substrate for color display is shown in the fifth example.
As shown in the figure. The active matrix substrate is red (R)
The three primary color pixels of green (G) and blue (B) drive each pixel of the liquid crystal layer, which is arranged in a so-called delta shape in which the same colors are not adjacent to each other and the three primary color pixels form a triangle. used to. Each picture element of the liquid crystal layer is such that red, green, and blue picture elements are alternately repeated in a predetermined order.

They are arranged in parallel at a constant pitch in the direction of the gate wiring 71. Each picture element in each picture element column parallel to the gate wiring 71 is shifted by a half pitch from each picture element in the picture element column adjacent to the picture element column. Each picture element electrode 72 of the active matrix substrate is arranged to face each picture element. Therefore, each source line 73 orthogonal to each gate line 71 is wired between adjacent picture element electrodes 72 of each picture element electrode row, as shown in FIG.

Between each picture element electrode row, the wiring is parallel to the gate wiring 71. At this time, the picture element electrodes 72 located on one side of each source wiring 73 passing between the picture element electrodes 72 in one picture element electrode row, and the picture element electrode rows adjacent to that picture element electrode row. The pixel electrode 72 located on the other side of the source wiring 73 drives a pixel having the same color. The source wiring 7
3 is electrically connected to the TPT 74 connected to these picture element electrodes 72. As a result, one source wiring 73
The colors of the picture elements that are controlled are the same, the signal processing circuit for forming a color image is simplified, and crosstalk between each color is reduced.

Each gate wiring 71 and source wiring 73 is one normal.

It is composed of a conductive metal film laminated on an insulating substrate. FIG. 7 shows a cross-sectional structure of the intersection between the gate wiring 71 and the source wiring 73 (cross-sectional view taken along the line ■-■ in FIG. 6). At the intersection of the gate wiring 71 and the source wiring 73, a laminated structure of an amorphous silicon (hereinafter abbreviated as a-5i) film 75 and a protective insulating film 76 is interposed to prevent short circuit between the two. Ru. As shown in FIG. 7, the gate wiring 71, which is wired to extend in a predetermined direction on an insulating substrate 77, is covered with a gate insulating film 78. Membranes 75 are laminated.

A protective insulating film 76 is laminated on the a-3i film 75. On the protective insulating film 76 is an n-type amorphous silicon film (hereinafter abbreviated as a-5i film (n+)) 79.
are layered. The a-3i(n) film 79 covers the protective insulating film 76 in the width direction of the gate wiring 71.

On each side of the protective insulating film 76, it is laminated directly on the a-Si film 75. A source wiring 73 is laminated on the a-5i(n') film 79 and the gate insulating film 78 so as to cover the a-5i(n'') film 79 in the width direction of the gate wiring 71. .

(Problem to be Solved by the Invention) As described above, in the portion where each source wiring 73 and gate wiring 71 intersect, the a-St film 75. protective insulating film 76,
The a-5t(n”) film 79 allows the source wiring, %5
A step extending in a direction perpendicular to 173 is formed. In particular, the a-5i film 75 and the a-Sign'') film 79 are formed by etching at the same time in the same pattern.

As shown in Figure 7, the lower a-5tn175 has the following information:
There is a risk that the structure will be such that the source wiring 73 digs deeper than the aSt(n+) film 79. When it comes to a structure like this.

The etching liquid soaks into the biting part, and a crack is generated in the source wiring 73 extending in the width direction.
3 may be disconnected. in this way.

Normally, if even one of the several hundred source wires 73 is disconnected, a linear defect will occur on one display screen, and the display performance will be significantly degraded.

The gate wiring 71 and the source wiring 73 are made as thin as possible in order to improve the aperture ratio (effective area ratio) of the liquid crystal panel. As described above, each gate wiring 71 and source wiring 73 is configured by laminating a conductive metal film on an insulating substrate 77.

Therefore, each gate wiring 71 and source wiring 73 may easily peel off from the insulating substrate 77.

Further, each source wiring 73 is provided between each pixel electrode row.

The gate wiring 71 is wired in parallel. For this reason.

There is a problem in that the area of the picture elements decreases between each picture element electrode row, and the aperture ratio decreases.

The present invention solves the above-mentioned conventional problems.

The purpose of this is to eliminate the risk of disconnection of the source wiring even at the intersection between the source wiring and the gate wiring.
An object of the present invention is to provide an active matrix substrate that can significantly improve the aperture ratio by reducing the area occupied by each wiring.

(Means for Solving the Problem) The present invention includes a plurality of pixel electrode rows in which a plurality of pixel electrodes are arranged in parallel in a predetermined direction at a predetermined pitch on an insulating substrate, and a drain electrode for each pixel electrode. An active matrix substrate having a plurality of thin film transistors arranged in a matrix so as to be connected to each other, and in which respective picture element electrodes in adjacent picture element electrode rows are arranged side by side with a shift of half a pitch. .

Each pixel electrode row is wired in parallel with a gate wire electrically connected to the gate electrode of each thin film transistor connected to each pixel electrode in the pixel electrode row, and a gate wire that is electrically connected to the gate electrode of each thin film transistor connected to each pixel electrode in the pixel electrode row. It passes between the picture element electrodes of the electrode rows that are shifted by half a pitch from each other, and is electrically connected to the source electrode of each thin film transistor connected to a predetermined picture element electrode on the side of the pass area in each picture element electrode row. has been
Further, each picture element electrode row includes a source wiring layered in an insulating state on the gate wiring so as to cover the entire width of each gate wiring.

This achieves the above objective.

(Example) The present invention will be described below with reference to Examples.

As shown in FIG. 1, the active matrix substrate of the present invention includes a large number of picture element electrodes 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20 . −
... is installed. Each picture element electrode 20 corresponds to the color of red (R) in the liquid crystal layer laminated on the active matrix substrate.
, green (G), and blue (B). The liquid crystal layer is.

Red (R) and green (G) at a constant pitch in a predetermined direction.

It is composed of a plurality of picture element rows in which picture elements of the three primary colors of blue (B) are alternately arranged in parallel, and each picture element in the adjacent picture element rows is shifted by a half pitch. The colors of the adjacent picture elements are different, and the three adjacent picture elements are red and green.

They are arranged in a so-called delta shape, forming a triangle with each color of blue.

Each picture element electrode 20 is arranged in large numbers on an insulating substrate.

It is arranged opposite to each picture element in the liquid crystal layer.

Each picture element 20 arranged in parallel at a constant pitch in a predetermined direction constitutes a picture element electrode array 2, 2, . . . . The picture element electrodes 20 of the adjacent picture element electrode rows 2 are arranged side by side, shifted by half a pitch from each other. The three adjacent picture element electrodes 20, 20.20 of the adjacent picture element electrode rows 2 are arranged opposite to each picture element of red (R), green (G), and blue (B) in the liquid crystal. There is. A TFT 50 is electrically connected to each picture element electrode 20.

Between each picture element electrode row 2, a gate wiring 3o is wired parallel to each picture element electrode row 2. Then, each picture element electrode row 2
The source wirings 40°, 40, . Each source wiring 40 is in a stacked state with each gate wiring 30 between each pixel electrode row 2, as described later. Each source wiring 4o.

When passing between predetermined picture element electrodes 2o and 20 of one picture element electrode row 2, the gate wiring 3o is stacked by an amount corresponding to half the pitch of the juxtaposition pitch of each picture element electrode 20. The pixel electrode row 2 passes between the pixel electrodes 20 that are shifted by half a pinch in a predetermined direction from the adjacent pixel electrode rows 20 . The directions in which the source wiring 40 is shifted by half a pitch between the respective picture element electrode rows 2 are alternately opposite directions. As a result of the source wiring 40 being wired in this manner, in the direction shifted by half a pitch between each pixel electrode row 2, a predetermined pixel located on the side of the passage M in the pixel electrode row 2 of the source wire 40 is located. electrode 20
The picture element electrode 20 to which each TFT 50 is connected is always facing a picture element of the same color. And each TPT50
The source electrode and one source wiring 40 are electrically connected via a connecting portion 41. The connection portion 41 is laminated in an insulated state from the gate wiring 30.

As shown in FIG. 2, between each adjacent picture element electrode row 2, each source wiring 40 has a length corresponding to half the pitch of the parallel pitch of each picture element electrode 20. Sakaki,
It is in a stacked state.

FIG. 3 shows a cross-sectional structure of the intersection (a cross-section taken along the line ■--■ in FIG. 2). The gate wiring 30 wired on the insulating substrate 10 is covered with a gate insulating film 61, and an a-3t film 62 is laminated on the gate insulating film 61. The a-Si film 62 covers the entire gate wiring 30 in the width direction. A protective insulating film 63 is laminated on the a-Si film 62 except on each side thereof. An amorphous silicon film (a-5t(n'') film) 64 is laminated on the protective insulating film 63 and the a-5i film 62 to cover the protective insulating film 63 in the width direction of the gate wiring 300. Furthermore, in order to cover the a-5t(n'') film 64 in the width direction of the gate arrangement a30, the a-5t(n'') film 64 is
) film 64 and the gate insulating film 61.
40 are stacked.

In this way, the source wiring 40 covers the entire gate wiring 30 in the width direction and covers the gate wiring tflA30 along its extending direction. It is longer along the line. Therefore, there is almost no possibility that cracks will occur over the entire step, and there is no possibility that the source wiring 40 will be disconnected.

A predetermined picture element electrode 2 is placed on the gate wiring 30 on the side of the part where the gate wiring 30 and the source wiring 40 are stacked.
A TFT 50 electrically connected to 0 is provided.

Each TPT 50 has an insulating substrate 10 as shown in FIG.
The gate electrode 3 is formed on a part of the gate wiring 30 layered above.
1. Gate electrode 3 of this gate wiring 30
1 is covered with a gate insulating film 52, and the gate insulating film 5 corresponds to the upper part of the gate electrode 31.
2, an a-5i film 53 is laminated on the a-S
On the central part of the t-film 53 except for each side.

A protective insulating film 54 is laminated. Then, on each side of the protective insulating film 54 and on each side of the a-Si film 53,
5i(n'') film 55 is laminated.
On one side of the film 55, the gate wiring 3
0, the connection portions 41 of the source wirings 40 in a stacked state are extended and stacked, and the source electrodes 42 are formed at the tips of the connection portions 41. A portion of the source wiring 40 constituting the source electrode 42 is layered on the gate insulating film 52 . A drain electrode 56 is laminated on the other side of the a-5i(n'') film 55. A part of the drain electrode 56 is laminated on the gate insulating film 52, and a part of the drain electrode 56 is laminated on the gate insulating film 52. A part of the picture element electrode 20 is stacked on the drain electrode 56 stacked on the drain electrode 52 .

An active matrix substrate having such a configuration is manufactured as follows. First, on an insulating substrate 10 such as a glass substrate, a gate wiring 30 is formed with a thickness of 100 to 4000 mm.
form. Then, by plasma CVD.

Gate insulating film with thickness of 1000~3000, 100~
After successively depositing an A-5I film to a thickness of 200 mm and a protective insulating film to a thickness of 1000 to 4000 mm, the protective insulating film is patterned into a predetermined shape by etching. Then phosphorus dope A-5 to the thickness of 100-1000 people
An i(n'') film is deposited, and the a-5i(n'') film and the a-5i film are simultaneously patterned into a predetermined shape. Next, a source wiring is formed by depositing, for example, Ti as a source wiring metal and patterning it into a predetermined shape.

After that, 1 example is transparency! A picture element electrode is formed by depositing an ITO film and patterning it into a predetermined shape. As a result, two active matrix substrates of the present invention are obtained.

(Effects of the Invention) As described above, in the active matrix substrate of the present invention, a part of the source wiring becomes a part of the gate wiring.

Since they are stacked in an insulating state, the area occupied by the source wiring on the insulating substrate can be reduced.

The aperture ratio of a liquid crystal display panel can be improved. Moreover, since a part of the source wiring is stacked on the gate wiring so as to cover a part of the gate wiring in the entire width direction, there is almost no possibility that the source wiring will be disconnected at the stacked part with the gate wiring.

Figure 1 is a partial plan view showing an example of the active matrix substrate of the present invention, Figure 2 is an enlarged view of its main parts, and Figure 3 is a cross section taken along the line ■-■ in Figure 2. figure.

4 is a cross-sectional view taken along line IV-IV in FIG. 2, FIG. 5 is a partial plan view showing an example of a conventional active matrix substrate, FIG. 6 is an enlarged view of the main part, and FIG. It is a sectional view taken along the line ■-■ in the figure.

10... Insulating substrate, 20... Picture element electrode, 30...
・Gate wiring.

31... Gate electrode, 40... Source wiring, 41.
・Connection part.

42-...Source electrode, 50"4FT, 53.6
2-a-St film.

54.63...Protective insulating film, 55.64...
a-5i(n”) membrane.

that's all

Claims (1)

[Claims] 1. A plurality of pixel electrode rows in which a plurality of pixel electrodes are arranged in parallel at a predetermined pitch in a predetermined direction on an insulating substrate, and a drain electrode is connected to each pixel electrode, respectively. 1. An active matrix substrate having a plurality of thin film transistors arranged in a matrix, and each picture element electrode in adjacent picture element electrode rows being arranged side by side with a shift of half a pitch, wherein each picture element electrode Gate wires are electrically connected to the gate electrodes of the thin film transistors connected to each pixel electrode in the pixel electrode row, and the gate wires are wired parallel to the pixel electrode row, and the gate wires are electrically connected to the gate electrodes of the thin film transistors connected to each pixel electrode in the pixel electrode row, and the gate wires are connected to each other between adjacent pixel electrode rows. passing between the picture element electrodes shifted by half a pitch, and electrically connected to the source electrode of each thin film transistor connected to a predetermined picture element electrode on the side of the pass region in each picture element electrode row, Further, between each pixel electrode row, a source wiring is insulated and laminated on the gate wiring so as to cover the entire width of each gate wiring.